AEAS-7500 AVAGO | Alldatasheet
Document overview
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- PDF pages: 8
Technical content
Features
- Two Sine/Cosine true differential outputs with 1024 periods for unit alignment
- Integrated highly collimated illumination system
- 11 digital tracks plus 2 sin/cos tracks generate precise 16 bit Gray code
- Ultra fast, 1µs cycle for serial data output word equals 16MHz
- The 12 bits MSB is functionable up to 12000 RPM, 16 bit up to 1000RPM
- MSB can be inverted for changing the counting direc- tion
- Monitor track for tracking the light level of the LED
- Watch dog with alarm output pin LERR
- -25 °C to + 85 °C operating temperature Benefits
- No battery or capacitor required for position detection during power failure
- Immediate position detection on power up
Applications
- Rotary application up to 16 bits / 360° absolute position
- Cost effective solution for direct integration into OEM systems
- Linear positioning system AEAS - 7500 Ultra-Precision 16 bit Gray Code Absolute Encoder Module Data Sheet
The photocurrent of the photodiodes is fed into a tran - simpedance amplifier. The analog output of the amplifier has a voltage swing of(dark/light) about 1.3V. Every output is transformed by precision comparators into digital signals (D1-D11). The threshold is at VDD/2(=Analog-reference), regulated by the monitor channel. Monitor Channel with LED Control at pins LEDR and LERR The analog output signal of the monitor channel is regu- lated by the LED current. An external bipolar transistor(to be connected by user) sets this level to VDD/2 (control voltage at pin LEDR). Thus the signal swing of each output is symmetrical to VDD/2(=Analog-reference) The error bit at pin LERR is triggered if the Ve of the internal bipolar transistor is larger than VDD/2 Signals Channels A0, A09 with signal conditioning and cali - bration These two channels give out a sine and cosine wave, which are 90 degree phase shifted. These signals have amplitudes, which are almost constant due to the LED current monitor- ing. Due to amplifier mismatch and mechanical misalign- ment the signals have gain and offset errors. These errors are eliminated by an adaptive signal conditioning circuitry. The conditioning values are on-chip preprogrammed by factory. The analog output signals of A0 and A09 are sup- plied as true-differential voltage with a peak to peak value of 2.0V at the pins A09P , A09N, A0P , A0N. Interpolator for Channels A0,A09 The interpolator generates the digital signals D0,D09 and D-1 to D-4. The interpolated signals D-1 to D-4 extend the 12 bit Gray code of the signals D11….D0 to form a 16 bit Gray code. D0 and D09 are digitized from A0 and A09. The channels A0-A11 and A09 have very high dynamic bandwidth, which allows a real time monotone 12Bit Gray code at 12000 RPM. The interpolated 16 bit Gray code can be used up to 1000RPM only. At more than 1000RPM, only the 12 bit Gray code from the MSB side can be used. LSB gray code Correction (Pin KORR) This function block synchronizes the switching points for the 11 bit gray code of the digital signals D1 to D11 with D0 and D09 (digitized signal of A0 and A09). The accuracy of the complete 12 bit gray is defined by the precision of the signals D0/D09. As these two signals are generated by the gain and offset conditioned analog signals A0 and A09, they are very precise. This Gray code correction only works for the full 12 bit (4096 steps per revolution). The correction is not for the 4 excess interpolated bits of the 16 bit Gray code. Gray code correction can be switched on or off by putting the pin KORR =1(on) or =0(off ). MSBINV and DOUT pins The serial interface consists of a shift register. The most significant bit, MSB(D11) will always be sent first to DOUT. The MSB can be inverted (change code direction) by using pin MSBINV. DIN and NSL pins The Serial input DIN allows the configuration as ring reg- ister for multiple transmissions or for cascading 2 or more encoders. DIN is the input of the shift register that shifts the data to DOUT. The NSL pin controls the shift register, to switch it between load (1) or shift(0) mode. Under load mode, DOUT will give the logic of the MSB, i.e. D11. Under shift mode (0), coupled with the SCL, the register will be clocked, and gives out the serial word output bit by bit. As the clock frequency can be up to 16 MHz, the transmis- sion of the full 16 bit word can be done within 1 µs. Valid data of DOUT should be read when the SCL clock is low. Please refer to timing diagram Figure 4.
- For other options of absolute encoder module, please refer to factory.
- Dimensions are in millimeters
- Note: Codewheel and readhead mounting tolerances for radial, tangential and Z gap are:
Figure 1. Package Dimensions
Absolute Maximum Ratings 1, 2 Recommended Operating Condition
Electrical Characteristics
Electrical Characteristics over Recommended Operating Range, typical at TA=25 °C and VD = 5V Notes: 1. LSB accuracy will also depend on mechanical precision of the shaft, bearings, hub etc. As the AEAS-7500 is a detached encoder set as differ- ent from AEAS-7000 series, which are modular, where final testing, programming and assembly take place at the customer facility, final ac- curacies of the encoder cannot be guaranteed by Avago. 2. Accuracy would be influenced by installation control and the bearing and shaft type being used. 3. Other test conditions to determine accuracy are briefly listed as follows: (a) At nominal radial, tangential and gap position (b) On dual preloaded bearing with absolute assembly total runout of not exceeding 0.01 mm TIR (c) Both VDD & VDDA RC filters placed not more than 20mm from header pins Notes: 1. Voltage ripple of supply voltage, Vripple, should be within 100mVpp or less for improved accuracy. Notes: 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter Symbol Limits Units DC Supply Voltage VD -0.3 to + 6.0 V Input Voltage Vin -0.3 to +VD +0.3 V Output Voltage Vout -0.5 to +VD +0.3 V Moisture Level (Non-Condensing) %RH 85 % Operating Temperature TA -25 to 85 °C Storage Temperature TS - 40 to 100 °C Parameter Symbol Values Units NotesMin. Typ. Max. DC Supply Voltage VD + 4.5 + 5.0 +5.5 V 1 Operating Temperature TA - 25 25 +85 °C Input High Level VIH 0.7*VD VD V Input Low Level VLH 0 0.3*VD V Parameter Symbol Condition Values UnitsMin Typ. Max Total Operating Current Itotal 25 mA Digital Input-Pull Down Current Ipd -20 -5 mA Digital Input-Pull Up Current Ipu 30 160 mA Digital Ouput-H-Level VOH IOH = 2 mA VD -0.5 V VD V Digital Ouput-L-Level VOL IOL = - 2 mA 0 0.5 V SCL Clock Frequency fSCL 16 MHz Duty Cycle SCL Clock TLH TLH = H/(L+H) 0.4 0.6 Accuracy within one revolution1, 2, 3 fSCL = 5MHz RPM =80 Vripple <50mVpp ±2 bit Signal frequency of A0, A09 fA0, fA09 250 kHz
Figure 2. Pinout Configuration
- Internal pu/pd = internal pull-up (typ. 50uA)/ pull-down (typ. 10uA) CMOS-transistor-Rs
1 NC Do not use
2 KORR Digital-input 1 = Gray Code Correction Active CMOS, internal pu
3 PROBE_ON Digital-Input Do not use CMOS, internal pd
4 PCL Digital Input
5 STCAL Digital Input
6 MSBINV Digital-Input 1 = Most Significant Bit, MSB, inverted CMOS, internal pd
8 NSL Digital-Input Shift-register Shift (=0) / Load(=1) Control CMOS, internal pu
9 SCL Digital-Input
10 DOUT Digital Output Shift-Register Data Out (MSB first) CMOSS, 2mA
11 DO Digital Output DO signal CMOS, 2mA
1 DPROBE Digital Output DO9 signal CMOS, mA
1 VDD Supply Voltage +V Supply Digital
1 GND Ground for supply voltage GND for V supply analog/digital
16 GND Ground for supply voltage GND for V supply analog/digital
19 VDDA Supply Voltage +V Supply Analog
0 A0N Analog Output A0 negative (- True dif) CMOS, analog out
1 LERR Digital Output IR-LED Current Limit Signal CMOS, mA
Figure 5. Schematic for using AEAS-7500 as close to the VDD and VDDA pins as possible. A09. Recommended to be used for testing purpose only. at a critical stage affecting the performance of the encoder. be shifted out to DOUT bit by bit per every clock pulse. can be serially transferred out in 1 us.
Ordering Information
Single-turn, -25 to +85oC, detached encoder set, 5V, se- rial, 16 bit Note: For alignment process, please refer to Avago Technologies’ website for application note or contact factory. For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United States and other countries. Data subject to change. Copyright © 2006 Avago Technologies Pte. All rights reserved. 5989-3095EN - March 29, 2006