AEAS-7000 AVAGO | Alldatasheet
Document overview
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- PDF pages: 8
Technical content
Features
- Minimum mechanical alignment during installation
- Two Sine/Cosine true differential outputs with 1024 periods for unit alignment
- Integrated highly collimated illumination system
- 11 digital tracks plus 2 sin/cos tracks generate precise 16 bit Gray code
- Ultra fast, 1 µs cycle for serial data output word equals 16 MHz
- On-chip interpolation and code correction
- MSB can be inverted for changing the counting direction
- Internally built-in monitor track for tracking the light level of the LED.
- Watch dog with alarm output
- –25°C to +85°C operating temperature
Applications
- Rotary application up to 16 bit/360° absolute position
- Linear positioning system
- Cost effective solution for direct integration into OEM systems
The photocurrent of the photo diodes is fed into a trans-impedance amplifier. The analog output of the amplifier has a voltage swing of (dark/light) about 1.3 V. Every output is transformed by precision comparators into digital signals (D1-D11). The threshold is at VDD/2 (=Analog-reference), regulated by the monitor channel. Monitor Channel with LED Control at Pins LEDR and LERR The analog output signal of the monitor channel is regulated by the LED current. An internal bipolar transistor sets this level to VDD/2 (control voltage at pin LEDR). Thus the signal swing of each output is symmetrical to VDD/2 (=Analog-reference) The error bit at pin LERR is triggered if the Ve of the internal bipolar transistor is larger than VDD/2. Signals Channels A0, A09 with Signal Conditioning and Calibration These two channels give out a sine and cosine wave, which are 90 degree phase shifted. These signals have amplitudes which are almost constant due to the LED current monitoring. Due to amplifier mismatch and mechanical misalignment, the signals have gain and offset errors. These errors are eliminated by an adaptive signal conditioning circuitry. The conditioning values are on-chip preprogrammed by factory. The analog output signals of A0 and A09 are supplied as true- differential voltage with a peak to peak value of 2.0 V at the pins A09P, A09N, A0P, A0N. Interpolator for Channels A0,A09 The interpolator generates the digital signals D0,D09 and D-1 to D-4. The interpolated signals D-1 to D-4 extend the 12 bit Gray code of the signals D11….D0 to form a 16 bit Gray code. D0 and D09 are digitized from A0 and A09. The channels A0-A11 and A09 have very high dynamic bandwidth, which allows a real time monotone 12 bit Gray code at 12000 RPM. The interpolated 16 bit Gray code can be used up to 1000 RPM only. At more than 1000 RPM, only the 12 bit Gray code from the MSB side can be used. LSB Gray Code Correction (Pin KORR) This function block synchronizes the switching points for the 11 bit Gray code of the digital signals D1 to D11 with D0 and D09 (digitized signal of A0 and A09). This Gray code correction only works for the 12 bit MSB(4096 steps per revolution). The correction is not for the 4 excess interpolated bits of the 16 bit Gray code. Gray code correction can be switched on or off by putting the pin KORR =1(on) or =0(off). MSBINV and DOUT Pins The serial interface consists of a shift register. The most significant bit, MSB (D11) will always be sent first to DOUT. The MSB can be inverted (change code direction) by using pin MSBINV. DIN and NSL Pins The serial input DIN allows the configuration as ring register for multiple transmissions or for cascading 2 or more encoders. DIN is the input of the shift register that shifts the data to DOUT. The NSL pin controls the shift register, to switch it between load (1) or shift (0) mode. Under load mode, DOUT will give the logic of the MSB, i.e., D11. Under shift mode (0), coupled with the SCL, the register will be clocked, and gives out the serial word output bit by bit. As the clock frequency can be up to 16 MHz, the transmission of the full 16 bit word can be done within 1µs. Valid data of DOUT should be read when the SCL clock is low. Please refer to timing diagram (Figure 3).
Figure 1. Package Dimensions
- For other options of absolute encoder module, please refer to factory.
- Dimensions are in millimeters
- Codewheel and readhead mounting tolerances for radial, tangential and Z gap are:
Absolute Maximum Ratings 1, 2 Recommended Operating Condition Notes: 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is stress r ating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of th is specification is not implied. 2. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Notes: 1. Voltage ripple of supply voltage, Vripple, should be within 100mVpp or less for improved accuracy. Parameter Symbol Limits Units DC Supply Voltage VD -0.3 to + 6.0 V Input Voltage V in -0.3 to +VD +0.3 V Output Voltage V out -0.3 to +VD +0.3 V Relative Air Humidity (non-condensing) RH 85 % Operating Temperature T A - 25 to +85 °C Storage T emperature T S - 35 to +85 °C Parameter Symbol Values Units NotesMin. Typ. Max. DC Supply Voltage VD + 4.5 + 5.0 +5.5 V 1 Operating Temperature T A - 25 25 +85 °C Input High Level V IH 0.7*VD VD V Input Low Level V LH 00 . 3 * V D V
Electrical Characteristics
Electrical Characteristics over Recommended Operating Range, typical at TA=25 °C and VD = 5V Notes: 1. LSB accuracy will also depend on mechanical precision of the shaft, bearings, hub etc. Final accuracy of the encoder module is dependent on the precision of the total assembly. 2. Accuracy would be influenced by installation control and the bearing and shaft type being used. 3. Other test conditions to determine accuracy are briefly listed as follows: (a) At nominal radial, tangential and gap position (b) On dual preloaded bearing with absolute assembly total runout of not exceeding 0.01 mm TIR (c) Both VDD & VDDA RC filters placed not more than 20mm from header pins Parameter Symbol Condition Values UnitsMin T ypical Max T otal Operating Current I total 25 mA Digital Input-Pull Down Current I pd -20 -5 µA Digital Input-Pull Up Current I pu 30 160 µA Digital Ouput-H-Level V OH IOH = 2 mA VD -0.5 V VD V Digital Ouput-L-Level V OL IOL = - 2 mA 0 0.5 V SCL Clock Frequency f SCL 16 MHz Duty Cycle SCL Clock T LH TLH = H/(L+H) 0.4 0.6 Accuracy within one revolution 1, 2, 3 fSCL = 5MHz RPM =80 Vripple <50mVpp ±2 bit Signal frequency of A0, A09 f A0, fA09 250 kHz
2 KORR Digital-input 1 = Gray Code Correction Active CMOS, internal pu
3 PROBE_ON Digital-Input Do not use CMOS, internal pd
4 PCL Digital Input
5 STCAL Digital Input
6 MSBINV Digital-Input 1 = Most Significant Bit, MSB, inverted CMOS, internal pd
8 NSL Digital-Input Shift-register Shift (=0) / Load(=1) Control CMOS, internal pu
9 SCL Digital-Input
10 DOUT Digital Output Shift-Register Data Out (MSB first) CMOSS, 2mA
11 DO Digital Output DO signal CMOS, 2mA
12 DPROBE Digital Output DO9 signal CMOS, 2mA
13 VDD Supply Voltage +5V Supply Digital
14 GND Ground for supply
16 GND Ground for supply
19 VDDA Supply Voltage +5V Supply Analog
20 A0N Analog Output A0 negative (- True dif) CMOS, analog out
21 LERR Digital Output IR-LED Current Limit Signal CMOS, 2mA
22 LEDR Analog Output Do not use CMOS, analog out
Figure 2. Pinout Configuration
- Internal pu/pd = internal pull-up (typ. 50 µA)/ pull-down (typ. 10 µA) CMOS-transistor-Rs
ESD WARNING: HANDLING PRECAUTIONS SHOULD BE TAKEN TO AVOID STATIC DISCHARGE.
Figure 3. Timing Diagram Figure 4. Schematic for using AEAS-7000 will always be sent out to DOUT first. LEDR, do not connect to this pin. put as close to the VDD and VDDA pins as possible. the negative versions of A09P and A0P.
1 FRAME = 16 BITS
1 = 5V G = Gray code S = serial output mode - 7000 - 1 G S S - Standard (-25˚C to +85˚C) D - 13 bits G - 16 bits
Ordering Information
AEAS-7000-1GSD0 Single-turn, -25 to +85°C, detached encoder set, 5V, serial, 13 bit AEAS-7000-1GSG0 Single-turn, -25 to +85°C, detached encoder set, 5V, serial, 16 bit HEDS-8933 M echanical Alignment Tool for AEAS-7000 Note: For alignment process, please refer to Avago Technologies website (www.avagotech.com) for application note or contact factory. For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countrie s. Data subject to change. Copyright © 2006 Avago Technologies Pte. All rights reserved. Obsoletes 5988-9627EN 5989-4140EN - May 29, 2006