ADNB-6011-EV AVAGO | Alldatasheet

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Technical content

Bundle Part Number Part Number Description ADNB-6011-EV ADNS-6010 Laser Mouse Sensor ADNV-6340 Single-Mode Vertical-Cavity Surface Emitting Laser (VCSEL) ADNS-6120 Laser Mouse Round Lens ADNS-6230-001 Laser Mouse VCSEL Assembly Clip Bundle Part Number Part Number Description ADNB-6012-EV ADNS-6010 Laser Mouse Sensor ADNV-6340 Single-Mode Vertical-Cavity Surface Emitting Laser (VCSEL) ADNS-6130-001 Laser Mouse Trim Lens ADNS-6230-001 Laser Mouse VCSEL Assembly Clip 6340 laser diode form a complete and compact laser mouse tracking system. There are no moving parts, which means high reliability and less maintenance for the end user. In addition, precision optical alignment is not required, facilitating high volume assembly. Avago Technologies Lasers must be used with Avago Technolo- gies sensors and lenses to ensure proper product opera- tion and compliance to eye safety regulations. This document will begin with some general information and usage guidelines on the bundles, followed by indi - vidual detailed information on ADNS-6010 laser mouse sensor, ADNV-6340 VCSEL, ADNS-6120 and ADNS-6130- 001 lenses, and ADNS-6230-001 clip.

Description

The Avago Technologies ADNB-6011-EV and ADNB-6012- EV laser mouse bundles are the world’s first laser-illumi- nated systems enabled for high performance navigation. Driven by Avago Technologies’ LaserStream Technology, the mouse can operate on many surfaces that prove difficult for traditional LED-based optical navigation. Its high-performance architecture is capable of sensing high-speed mouse motion – with resolution up to 2000 counts per inch, velocities up to 45 inches per second (ips) and accelerations up to 20G. This sensor is powered for the extremely high sensitive user. The ADNS-6010 sensor along with the ADNS-6120 or ADNS-6130-001 lens, ADNS-6230-001 clip and ADNV- ADNB-6011-EV and ADNB-6012-EV High Performance Laser Mouse Bundles include: ADNB-6011-EV and ADNB-6012-EV High Performance Laser Mouse Bundles Data Sheet

Figure 1. Assembly drawing of ADNB-6011-EV (top, front and cross-sectional view)

Figure 2. Exploded view drawing mounted onto defined features on the base plate. mode, reliable operating conditions.

Figure 3. Recommended PCB mechanical cutouts and spacing

  1. Insert the sensor and all other electrical components
  2. Wave solder the entire assembly in a no-wash solder

aperture from direct solder contact.

  1. Place the lens onto the base plate.
  2. Remove the protective kapton tape from the optical

contaminants from entering the aperture.

  1. Insert the PCB assembly over the lens onto the base
  2. Remove the protective kapton tape from the VCSEL.
  3. Insert the VCSEL assembly into the lens.
  4. Slide the clip in place until it latches. This locks the
  5. Tune the laser output power from the VCSEL to meet
  6. Install the mouse top case. There must be a feature

to the correct vertical height.

6130-001 trim lens (or ADNS-6120 round lens). Figure 4. Cross section of PCB assembly Figure 5. Schematic Diagram for 3-Button Scroll Wheel USB PS/2 Mouse

13 XTALOUT

3 RESET

16 KBit EEPROM (optional)

sives that may damage the lens should NOT be used.

Value (kohm) Match_Bit (Reg 0x2C, Bit7) 2A 18.7 0 3A 12.7 0 Notes (for Figure 5)

  • Caps for pins 11, 12, 16 and 18 MUST have trace lengths LESS than 5 mm on each side.
  • Pins 16 and 18 caps MUST use pin 17 GND.
  • Pin 9, if used, should not be connected to PCB GND to reduce po- tential RF emissions.
  • The 0.1 uF caps must be ceramic.
  • Caps should have less than 5 nH of self inductance.
  • Caps should have less than 0.2 W ESR.
  • NC pins should not be connected to any traces.
  • Surface mount parts are recommended.
  • Care must be taken when interfacing a 5V microcontroller to the ADNS-6010. Serial port inputs on the sensor should be con- nected to open-drain outputs from the microcontroller or use an active drive level shifter. NPD and RESET should be connected to 5V microcontroller outputs through a resistor divider or other level shifting technique.
  • VDD3 and GND should have low impedance connections to the power supply.
  • Because the RBIN pin sets the XY_LASER current, the following PC board layout practices should be followed to reduce the chance of uncontrolled laser drive current caused from a leakage path between RBIN and ground. One hypothetical source of such a leakage path is PC board contamination due to a liquid, such as a soft drink, being deposited on the printed circuit board. o The RBIN resistor should be located close to the sensor pin 13. The traces between the resistor and the sensor should be short. o The pin 13 solder pad and all exposed conductors connected to pin 13 should be surrounded by a guard trace connected to VDD3 and devoid of a solder mask. o The pin 13 solder pad, the traces connected to pin 13, and the RBIN resistor should be covered with a conformal coating. o The RBIN resistor should be a thru-hole style to increase the dis- tance between its terminals. This does not apply if a conformal coating is used. LASER Drive Mode The LASER has 2 modes of operation: DC and Shutter. In DC mode, the LASER is on at all times the chip is powered except when in the power down mode via the NPD pin. In shutter mode the LASER is on only during the portion of the frame that light is required. The LASER mode is set by the LASER_MODE bit in the Configuration_bits regis- ter. For optimum product lifetime, Avago Technologies recommends the default Shutter mode setting (except for calibration and test). Eye Safety The ADNS-6010 and the associated components in the schematic of Figure 5 are intended to comply with Class 1 Eye Safety Requirements of IEC 60825-1. Avago Tech- nologies suggests that manufacturers perform testing to verify eye safety on each mouse. It is also recommended to review possible single fault mechanisms beyond those described below in the section “Single Fault Detection” . Under normal conditions, the ADNS-6010 generates the drive current for the laser diode (ADNV-6340). In order to stay below the Class 1 power requirements, resistor Rbin must be set at least as high as the value in the bin table of Figure 5, based on the bin number of the laser diode and LP_CFG0 and LP_CFG1 must be programmed to appropriate values. Avago Technologies recommends using the exact Rbin value specified in the bin table to ensure sufficient laser power for navigation. The sys - tem comprised of the ADNS-6010 and ADNV-6340 is designed to maintain the output beam power within Class 1 requirements over component manufacturing tolerances and the recommended temperature range when adjusted per the procedure below and when implemented as shown in the recommended application circuit of Figure 5. For more information, please refer to Avago Technologies ADNB-6001, ADNB-6002, ADNB- 6011 and ADNB-6012 Laser Mouse Eye Safety Calculation Application Note 5088. LASER Power Adjustment Procedure 1. The ambient temperature should be 25C +/- 5C. 2. Set VDD3 to its permanent value. 3. Ensure that the laser drive is at 100% duty cycle. 4. Program the LP_CFG0 and LP_CFG1 registers to achieve an output power as close to 506uW as pos - sible without exceeding it. Good engineering practices should be used to guaran - tee performance, reliability and safety for the product design. Avago Technologies has additional information and detail, such as firmware practices, PCB layout sugges- tions, and manufacturing procedures and specifications that could be provided.

current source and set the LASER_NEN output high. due to PC board contamination. fault detection circuit on the XY_LASER pin. Figure 6. Single Fault Detection and Eye-safety Feature Block Diagram

  1. The system is adjusted according to the above pro -
  2. The system is operated within the recommended op -
  3. The VDD3 value is no greater than 50mV above its

value at the time of adjustment.

  1. No allowance for optical power meter accuracy is as -

The ADNS-6010 is based on LaserStream Technology, which measures changes in position by optically acquir- ing sequential images (frames) and mathematically de - termining the direction and magnitude of movement. ADNS-6010 contains an Image Acquisition System (IAS), a Digital Signal Processor (DSP), and a four wire serial port. The IAS acquires microscopic surface images via the lens and illumination system. These images are processed by the DSP to determine the direction and distance of motion. The DSP calculates the ∆x and ∆y relative displacement values. An external microcontroller reads the ∆x and ∆y information from the sensor serial port. The microcontroller then translates the data into PS2 or USB signals before sending them to the host PC or game console. Figure 7. Package outline drawing (top view)

1 NCS Chip select

2 MISO Serial data output (Master

3 SCLK Serial clock input

4 MOSI Serial data input (Master

5 NC No Connection

6 RESET Reset input

7 NPD Power down(active low

8 OSC_OUT Oscillator output

9 GUARD Oscillator GND for PCB guard

10 OSC_IN Oscillator input

11 REFC Reference capacitor

12 REFB Reference capacitor

13 RBIN Set XY_LASER current

14 XY_LASER LASER current output

15 NC No Connection

16 VDD3 Supply voltage

17 GND Ground

18 VDD3 Supply voltage

19 GND Ground

20 LASER_NEN Laser enable (active low)

Features

  • High speed motion detection – up to 45 ips and 20G
  • New LaserStream architecture for greatly improved optical navigation technology
  • Programmable frame rate over 7080 frames per sec - ond
  • SmartSpeed self-adjusting frame rate for optimum performance
  • Serial port burst mode for fast data transfer
  • 400, 800, 1600 or 2000 cpi selectable resolution
  • Single 3.3 volt power supply
  • Four-wire serial port along with Power Down, and Reset pins
  • Laser fault detect circuitry on-chip for Eye Safety Com- pliance

Applications

  • Mice for game consoles and computer games
  • Mice for desktop PC’s, Workstations, and portable PC’s
  • Laser Trackballs
  • Integrated input devices Pinout ADNS-6010 Laser Mouse Sensor

Figure 8. Package outline drawing

  1. Dimensions in millimeters (inches)
  2. Dimenstional tolerance: ±0.1 mm
  3. Coplanarity of leads: 0.1 mm
  4. Lead pitch tolerance: ±0.15 mm
  5. Cummulative pitch tolerance. ±0.15 mm
  6. Chamfer (25˚ x 2) on the taper side of the lead

Figure 9. Block diagram of ADNS-6010 optical mouse sensor

3.3 V POWER

Figure 10. Distance from lens reference plane to surface

  • Passes FCC B and worldwide analogous emission limits when assembled into a mouse with shielded cable and following Avago Technologies recommen- dations.
  • Passes IEC-1000-4-3 radiated susceptibility level when assembled into a mouse with shielded cable and fol - lowing Avago Technologies recommendations.
  • Passes EN61000-4-4/IEC801-4 EFT tests when assem- bled into a mouse with shielded cable and following Avago Technologies recommendations.
  • UL flammability level UL94 V-0.

Recommended Operating Conditions Absolute Maximum Ratings Parameter Symbol Minimum Maximum Units Notes Storage Temperature TS -40 85 °C Operating Temperature TA -15 55 °C Lead Solder Temp 260 °C For 10 seconds, 1.6mm below seat- ing plane. Supply Voltage VDD3 -0.5 3.7 V ESD 2 kV All pins, human body model MIL

883 Method 3015

Input Voltage VIN -0.5 VDD3+0.5 V NPD, NCS, MOSI, SCLK, RESET, OSC_IN, OSC_OUT, REFC, RBIN Output current IOUT 7 mA MISO, LASER_NEN Input Current IIN 15 mA XY_LASER current with RBIN 12.7KΩ LP-CFG0 = 0x00; LP_CFG1 = 0xFF Parameter Symbol Minimum Typical Maximum Units Notes Operating Temperature TA 0 40 °C Power supply voltage VDD3 3.10 3.30 3.60 Volts Power supply rise time VRT 1 us 0 to 3.0V Supply noise(Sinusoidal) VNB 3080 mV p-p 10kHz- 300KHZ300KHz- 50MHz Oscillator Frequency fCLK 23 24 25 MHz Set by ceramic resonator Serial Port Clock Fre- quency fSCLK 2500 MHzkHz Active drive, 50% duty cycleOpen drain drive with pull-ups on, 50 pF load Resonator Impedance XRES 55 W Distance from lens refer- ence plane to surface Z 2.18 2.40 2.62 mm Results in +/- 0.2 mm mini- mum DOF, see Figure 10 Speed S 45 in/sec Acceleration A 20 G Frame Rate FR 2000 7080 Frames/ s See Frame_Period register section Resistor value for LASER Drive Current set Rbin See Bin Table in Figure 5 kOhms ADNV-6340 VCSEL Voltage at XY_LASER Vxy_laser 0.7 VDD3 V

Parameter Symbol Min. Typ. Max. Units Notes VDD to RESET tOP 250 ms From VDD = 3.0V to RESET sampled Data delay after RESET tPU-RESET 180 ms From RESET falling edge to valid motion data at 2000 fps and shutter bound 20k. Input delay after reset TIN-RST 550 ms From RESET falling edge to inputs active (NPD, MOSI, NCS, SCLK) Power Down tPD 600 ms From NPD falling edge to initiate the power down cycle at 2000 fps (tpd = 1 frame period + 100ms ) Wake from NPD tPUPD tCOMPUTE 75 ms From NPD rising edge to valid motion data at 2000 fps and shutter bound 20k. Max assumes surface change while NPD is low Data delay after NPD tCOMPUTE 3.1 ms From NPD rising edge to all registers contain data from new images at 2000 fps (See Figure 11). RESET pulse width tPW-RESET 10 ms MISO rise time tr-MISO 40 200 ns CL = 50pF MISO fall time tf-MISO 40 200 ns CL = 50pF MISO delay after SCLK tDLY-MISO 120 ns From SCLK falling edge to MISO data valid, no load conditions MISO hold time thold- MISO 250 ns Data held until next falling SCLK edge MOSI hold time thold- MOSI 200 ns Amount of time data is valid after SCLK rising edge MOSI setup time tsetup- MOSI 120 ns From data valid to SCLK rising edge SPI time between write commands tSWW 50 ms From rising SCLK for last bit of the first data byte, to rising SCLK for last bit of the second data byte. SPI time between write and read commands tSWR 50 ms From rising SCLK for last bit of the first data byte, to rising SCLK for last bit of the second address byte. SPI time between read and subse- quent commands tSRWtSRR 250 ns From rising SCLK for last bit of the first data byte, to fall- ing SCLK for first bit of the second address byte. SPI read address- data delay tSRAD 50 ms From rising SCLK for last bit of the address byte, to falling SCLK for first bit of data being read. All registers except Motion & Motion_Burst SPI motion read address-data delay tSRAD- MOT 75 ms From rising SCLK for last bit of the address byte, to falling SCLK for first bit of data being read. Applies to 0x02 Mo- tion, and 0x50 Motion_Burst, registers NCS to SCLK active tNCS-SCLK 120 ns From NCS falling edge to first SCLK rising edge SCLK to NCS inac- tive tSCLK-NCS 120 ns From last SCLK falling edge to NCS rising edge, for valid MISO data transfer NCS to MISO high-Z tNCS-MISO 250 ns From NCS rising edge to MISO high-Z state PROM download and frame capture byte-to-byte delay tLOAD 10 ms (See Figure 24 and 25) NCS to burst mode exit tBEXIT 4 ms Time NCS must be held high to exit burst mode Transient Supply Current IDDT 68 mA Max supply current during a VDD3 ramp from 0 to 3.6 V Input Capacitance C IN 14-22 pF OSC_IN, OSC_OUT

Figure 11. NPD Rising Edge Timing Detail

ignored and the output is tri-stated. will be high Z, and MOSI & SCLK will be ignored. Figure 15. Relative Responsivity further use until burst-mode is terminated.

read before the data is ready, it will return all zeros. 636 bytes will be approximately 2/3 of the next frame. zeros. Pixel data is in the lower six bits of each byte. description for more information.

  1. MSB = 1 for all bytes. Bit 6 = 0 for all bytes except pixel 0 of both frames which has bit 6 = 1 for use as a frame marker.
  2. Reading beyond pixel 899 will return the first pixel of the second partial frame.
  3. tCAPTURE = 10 s + 3 frame periods.
  4. This figure illustrates reading a single complete frame of 900 pixels. An additional 636 pixels from the next frame are available.

Figure 25. Frame capture burst mode timing

Figure 26. Pixel address map (surface referenced) The pixel output order as related to the surface is shown below.

  1. The ADNS-6010 and the micro-controller might get
  2. Invalid addresses: Writing to an invalid address will
  3. Termination of a transmission by the micro-controller

accomplish this the micro-controller should raise NCS. after aborted transmissions.

  1. The micro-controller can verify success of write opera-

and comparing written data to read data.

  1. The micro-controller can verify the synchronization of

and inverse product ID registers.

  1. The microcontroller can read the SROM_ID register to

happen, pulse RESET and reload the SROM code.

State of Signal Pins After VDD is Valid Pin Before Reset During Reset After Reset SPI pullups undefined off on (default) NCS hi-Z control func- tional hi-Z control func- tional functional MISO driven or hi-Z (per NCS) driven or hi-Z (per NCS) low or hi-Z (per NCS) SCLK undefined ignored functional MOSI undefined ignored functional XY_LASER undefined hi-Z functional RESET functional high (externally driven) functional NPD undefined ignored functional LASER_NEN undefined high (off ) functional State of Signal Pins During Power Down Pin NPD low After wake from PD SPI pullups off pre-PD state NCS hi-Z control functional functional MISO low or hi-Z (per NCS) pre-PD state or hi-Z SCLK ignored functional MOSI ignored functional XY_LASER high (off ) functional RESET functional functional NPD low (driven externally) functional REFC VDD3 REFC OSC_IN low OSC_IN OSC_OUT high OSC_OUT LASER_NEN high (off ) functional Reset Circuit The ADNS-6010 does not perform an internal power up self-reset; the reset pin must be raised and lowered to reset the chip. This should be done every time power is applied. During power-up there will be a period of time after the power supply is high but before any clocks are available. The table below shows the state of the various pins during power-up and reset when the RESET pin is driven high by a micro-controller. Notes on Power-up and the serial port Power Down Circuit The following table lists the pin states during power down. The chip is put into the power down (PD) mode by low- ering the NPD input. When in PD mode, the oscillator is stopped but all register contents are retained. To achieve the lowest current state, all inputs must be held exter - nally within 200mV of a rail, either ground or VDD3. The chip outputs are driven low or hi-Z during PD to prevent current consumption by an external load.

The ADNS-6010 registers are accessible via the serial port. The registers are used to read motion data and status as well as to set the device configuration. Address Register Read/Write Default Value 0x00 Product_ID R 0x1C 0x01 Revision_ID R 0x20 0x02 Motion R 0x20 0x03 Delta_X R 0x00 0x04 Delta_Y R 0x00 0x05 SQUAL R 0x00 0x06 Pixel_Sum R 0x00 0x07 Maximum_Pixel R 0x00 0x08 Reserved 0x09 Reserved 0x0a Configuration_bits R/W 0x49 0x0b Extended_Config R/W 0x08 0x0c Data_Out_Lower R Any 0x0d Data_Out_Upper R Any 0x0e Shutter_Lower R 0x85 0x0f Shutter_Upper R 0x00 0x10 Frame_Period_Lower R Any 0x11 Frame_Period_Upper R Any 0x12 Motion_Clear W Any 0x13 Frame_Capture R/W 0x00 0x14 SROM_Enable W 0x00 0x15 Reserved 0x16 Configuration II R/W 0x34 0x17 Reserved 0x18 Reserved 0x19 Frame_Period_Max_Bound Lower R/W 0x90 0x1a Frame_Period_Max_Bound_Upper R/W 0x65 0x1b Frame_Period_Min_Bound_Lower R/W 0x7E 0x1c Frame_Period_Min_Bound_Upper R/W 0x0E 0x1d Shutter_Max_Bound_Lower R/W 0x20 0x1e Shutter_Max_Bound_Upper R/W 0x4E 0x1f SROM_ID R Version dependent 0x20-0x2b Reserved 0x2c LP_CFG0 R/W 0x7F 0x2d LP_CFG1 R/W 0x80 0x2e-0x3c Reserved 0x3d Observation R/W 0x00 0x3e Reserved 0x3f Inverse Product ID R 0xE3 0x40 Pixel_Burst R 0x00 0x50 Motion_Burst R 0x00 0x60 SROM_Load W Any

Revision_ID Address: 0x01 Access: Read Default Value: 0x20 Bit 7 6 5 4 3 2 1 0 Field RID7 RID6 RID5 RID4 RID3 RID2 RID1 RID0 Data Type: 8-Bit unsigned integer. USAGE: This register contains the IC revision. It is subject to change when new IC versions are released. NOTE: The downloaded SROM firmware revision is a separate value and is available in the SROM_ID register. Product_ID Address: 0x00 Access: Read Default Value: 0x1C Bit 7 6 5 4 3 2 1 0 Field PID7 PID6 PID5 PID4 PID3 PID2 PID1 PID0 Data Type: 8-Bit unsigned integer USAGE: This register contains a unique identification assigned to the ADNS-6010. The value in this register does not change; it can be used to verify that the serial communications link is functional.

Motion Address: 0x02 Access: Read Default Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field MOT Reserved LP_Valid OVF Reserved RES1 Fault RES0 Data Type: Bit field. USAGE: Register 0x02 allows the user to determine if motion has occurred since the last time it was read. If so, then the user should read registers 0x03 and 0x04 to get the accumulated motion. It also tells if the motion buffers have overflowed, if fault is detected, and the current resolution setting. Notes for Motion: 1. Reading this register freezes the Delta_X and Delta_Y register values. Read this register before reading the Delta_X and Delta_Y registers. If Delta_X and Delta_Y are not read before the motion register is read a second time, the data in Delta_X and Delta_Y will be lost. 2. Avago Technologies RECOMMENDS that registers 0x02, 0x03 and 0x04 be read sequentially. See Motion burst mode also. 3. Internal buffers can accumulate more than eight bits of motion for X or Y. If either one of the internal buffers over- flows, then absolute path data is lost and the OVF bit is set. This bit is cleared once some motion has been read from the Delta_X and Delta_Y registers, and if the buffers are not at full scale. Since more data is present in the buffers, the cycle of reading the Motion, Delta_X and Delta_Y registers should be repeated until the motion bit (MOT) is cleared. Until MOT is cleared, either the Delta_X or Delta_Y registers will read either positive or negative full scale. If the motion register has not been read for long time, at 400 cpi it may take up to 16 read cycles to clear the buffers, at 2000 cpi, up to 80 cycles. Alternatively, writing to the Motion_Clear register (register 0x12) will clear all stored motion at once. Field Name Description MOT Motion since last report 0 = No motion 1 = Motion occurred, data ready for reading in Delta_X and Delta_Y registers LP_Valid This bit is an indicator of complementary value contained in registers 0x2C and 0x2D. 0 = register 0x2C and 0x2D do not have complementary values 1 = register 0x2C and 0x2D contain complementary values OVF Motion overflow, ∆Y and/or ∆X buffer has overflowed since last report 0 = no overflow 1 = overflow has occurred Fault Indicates that the RBIN and/or XY_LASER pin is shorted to GND. 0 = no fault detected 1 = fault detected RES1, RES0 Resolution in counts per inch (cpi). Resolution values are approximate. Cpi Bit2(RES1) Bit0(RES0) 400 0 0 800 0 1 1600 1 0 2000 1 1 Please see register 0x0a to set cpi

Delta_X Address: 0x03 Access: Read Default Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field X7 X6 X5 X4 X3 X2 X1 X0 Data Type: Eight bit 2’s complement number. USAGE: X movement is counts since last report. Absolute value is determined by resolution. Reading clears the reg - ister. 00 01 02 7E 7F +127+126+1 +2 FFFE8180 0-1-2-127-128Motion Delta_X Delta_Y Address: 0x04 Access: Read Default Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Data Type: Eight bit 2’s complement number. USAGE: Y movement is counts since last report. Absolute value is determined by resolution. Reading clears the reg - ister. 00 01 02 7E 7F +127+126+1 +2 FFFE8180 0-1-2-127-128Motion Delta_Y

Reserved Address: 0x08 Reserved Address: 0x09 Pixel_Sum Address: 0x06 Access: Read Default Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Data Type: High 8 bits of an unsigned 16-bit integer. USAGE: This register is used to find the average pixel value. It reports the upper byte of a 16-bit counter which sums all 900 pixels in the current frame. It may be described as the full sum divided by 256. To find the average pixel value, use the following formula: Average Pixel = Register Value * 256 / 900 = Register Value/3.51 The maximum register value is 221 (63 * 900/256 truncated to an integer). The minimum is 0. The pixel sum value can change on every frame. Maximum_Pixel Address: 0x07 Access: Read Default Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field 0 0 MP5 MP4 MP3 MP2 MP1 MP0 Data Type: Six bit number. USAGE: Maximum Pixel value in current frame. Minimum value = 0, maximum value = 63. The maximum pixel value can vary with every frame.

Configuration_bits Address: 0x0a Access: Read/Write Default Value: 0x49 Bit 7 6 5 4 3 2 1 0 Field 0 LASER_MODE Sys Test RES1 1 RES0 Reserved Reserved Data Type: Bit field USAGE: Register 0x0a allows the user to change the configuration of the sensor. Shown below are the bits, their default values, and optional values. Field Name Description BIT 7 Must always be zero LASER_MODE LASER Shutter Mode 0 = Shutter mode off (LASER always on) 1 = Shutter mode on (LASER only on when illumination is required) Sys Test System Tests 0 = no tests 1 = perform all system tests, output 16 bit CRC via Data_Out_Upper and Data_Out_Lower registers. NOTE: The test will fail if SROM is loaded. Perform a hardware reset before executing this test. Reload SROM after the test is completed. NOTE: The test will fail if a laser fault condition exists. NOTE: Since part of the system test is a RAM test, the RAM and SROM will be overwritten with the default values when the test is done. If any configuration changes from the default are needed for operation, make the changes AFTER the system test is run. The system test takes 200ms (@24MHz) to complete. NOTE: Do not access the Synchronous Serial Port during system test. RES Resolution in counts per inch. Resolution values are approximate. Cpi Bit4(RES1) Bit2(RES0) 400 0 0 800 1 0 1600 0 1 2000 1 1 Also see register 0x02i BIT 3 Must always be one

Extended_Config Address: 0x0b Access: Read/Write Default Value: 0x08 Bit 7 6 5 4 3 2 1 0 Field Busy Reserved Reserved Reserved 1 Serial_NPU NAGC Fixed_FR Data Type: Bit field USAGE: Register 0x0b allows the user to change the configuration of the sensor. Shown below are the bits, their default values, and optional values. Field Name Description Busy Read-only bit. Indicates if it is safe to write to one or more of the following registers: Frame_Period_Max_Bound_Upper and Frame_Period_Max_Bound_Lower Frame_Period_Min_Bound_Upper and Frame_Period_Min_Bound_Lower Shutter_Max_Bound_Upper and Shutter_Max_Bound_Lower After writing to the Frame_Period_Maximum_Bound_Upper register, at least two frames must pass before writing again to any of the above registers. This bit may be used in lieu of a timer since the actual frame rate may not be known when running in auto mode. 0 = writing to the registers is allowed 1 = do not write to the registers yet BIT 3 Must always be one Serial_NPU Disable serial port pull-up current sources on SCLK, MOSI and NCS 0 = no, current sources are on 1 = yes, current sources are off NAGC Disable AGC. Shutter will be set to the value in the Shutter_Maximum_Bound registers. 0 = no, AGC is active 1 = yes, AGC is disabled Fixed_FR Fixed frame rate (disable automatic frame rate control). When this bit is set, the frame rate will be determined by the value in the Frame_Period_Maximum_Bound registers. 0 = automatic frame rate 1 = fixed frame rate

Data_Out_Lower Address: 0x0c Access: Read Default Value: Undefined Bit 7 6 5 4 3 2 1 0 Field DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Data_Out_Upper Address: 0x0d Access: Read Default Value: Undefined Bit 7 6 5 4 3 2 1 0 Field DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 Data Type: Sixteen bit word USAGE: Data in these registers come from the system self test or the SROM CRC test. The data can be read out in either order. System Test: This test is initiated via the Configuration_Bits register. It performs several tests to verify that the hardware is functioning correctly. Perform a hardware reset just prior to running the test. SROM contents and register settings will be lost. SROM Content: Performs a CRC on the SROM contents. The test is initiated by writing a particular value to the SROM_ Enable register. Data_Out_Upper Data_Out_Lower System test results: 0xA9 0xD5 SROM CRC Test Result: 0xBE 0xEF

Figure 29. Shutter Values at 2000cpi (White Paper) Data Type: Sixteen bit unsigned integer. mode using the Extended_Config register.

Figure 30. Mean Shutter vs. Z (White Paper) Bound_Upper and Shutter_Max_Bound_Lower registers.

Motion_Clear Address: 0x12 Access: Write Default Value: Undefined Data Type: Any. USAGE: Writing any value to this register will cause the Delta_X, Delta_Y, and internal motion registers to be cleared. Use this as a fast way to reset the motion counters to zero without resetting the entire chip. Frame_Period_Lower Address: 0x10 Access: Read Default Value: Undefined Bit 7 6 5 4 3 2 1 0 Field FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0 Frame_Period_Upper Address: 0x11 Access: Read Default Value: Undefined Bit 7 6 5 4 3 2 1 0 Field FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8 Data Type: Sixteen bit unsigned integer. USAGE: Read these registers to determine the current frame period and to calculate the frame rate. Units are clock cycles. The formula is Frame Rate = Clock Frequency/Register value To read from the registers, read Frame_Period_Upper first followed by Frame_Period Lower. To set the frame rate manually, disable automatic frame rate mode via the Extended_Config register and write the desired count value to the Frame_Period_Max_Bound registers. The following table lists some Frame_Period values for popular frame rates with a 24MHz clock. Frames/second Counts Frame_Period Decimal Hex Upper Lower 7080 3,390 0D3E 0D 3E 5000 4,800 12C0 12 C0 3000 8,000 1F40 1F 40 2000 12,000 2EE0 2E E0

Frame_Capture Address: 0x13 Access: Read/Write Default Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 Data Type: Bit field. USAGE: Writing 0x83 to this register will cause the next available complete 1 2/3 frames of pixel values to be stored to SROM RAM. Writing to this register is required before using the Frame Capture burst mode to read the pixel values (see the Synchronous Serial Port section for more details). Writing to this register will stop navigation and cause any firmware loaded in the SROM to be overwritten. A hardware reset is required to restore navigation, and the firmware must be reloaded using the PROM Download burst method. This register can also be used to read the frame capture data. The same data available by reading the Pixel_Burst register using burst mode is available by reading this register in the normal fashion. The data pointer is automatically incremented after each read so all 1536 pixel values (1 and 2/3 frames) may be obtained by reading this register 1536 times in a row. Both methods share the same pointer such that reading pixel values from this register will increment the pointer causing subsequent reads from the Pixel_Burst register (without initiating a new frame dump) to start at the current pointer location. This register will return all zeros if read before the frame capture data is ready. See the Frame Capture description in the Synchronous Serial Port section for more information. This register will not retain the last value written. Reads will return zero or frame capture data. SROM_Enable Address: 0x14 Access: Write Default Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 Data Type: 8-bit number. USAGE: Write to this register to start either PROM download or SROM CRC test. Write 0x1D to this register, wait at least 1 frame period, and write 0x18 to this register before downloading PROM firmware to the SROM_Load register. The download will not be successful unless this sequence is followed. See the Synchronous Serial port section for details. Write 0xA1 to start the SROM CRC test. Wait 7ms plus one frame period, then read result from the Data_Out_Lower and Data_Out_Upper registers. Navigation is halted and the SPI port should not be used during this test. Reserved Address: 0x15

Configuration II Address: 0x16 Access: Read/Write Default Value: 0x34 Bit 7 6 5 4 3 2 1 0 Field Reserved Reserved Reserved Reserved Reserved 1 Force_disable Reserved Data Type: Bit field USAGE: Write to this register Reserved Address: 0x17-0x18 Field Name Description BIT 2 Must be set to one Force_disable 0 = LASER_NEN functions as normal 1 = LASER_NEN output high. May be useful for product test.

Frame_Period_Max_Bound_Lower Address: 0x19 Access: Read/Write Default Value: 0x90 Bit 7 6 5 4 3 2 1 0 Field FBM7 FBM6 FBM5 FBM4 FBM3 FBM2 FBM1 FBM0 Frame_Period_Max_Bound_Upper Address: 0x1A Access: Read/Write Default Value: 0x65 Bit 7 6 5 4 3 2 1 0 Field FBM15 FBM14 FBM13 FBM13 FBM11 FBM10 FBM9 FBM8 Data Type: 16-bit unsigned integer. USAGE: This value sets the maximum frame period (the MINIMUM frame rate) which may be selected by the auto - matic frame rate control, or sets the actual frame period when operating in manual mode. Units are clock cycles. The formula is Frame Rate = Clock Frequency / Register value To read from the registers, read Upper first followed by Lower. To write to the registers, write Lower first, followed by Upper. To set the frame rate manually, disable automatic frame rate mode via the Extended_Config register and write the desired count value to these registers. Writing to the Frame_Period_Max_Bound_Upper and Lower registers also activates any new values in the following registers:

  • Frame_Period_Max_Bound_Upper and Lower
  • Frame_Period_Min_Bound_Upper and Lower
  • Shutter_Max_Bound_Upper and Lower Any data written to these registers will be saved but will not take effect until the write to the Frame_Period_Max_ Bound_Upper and Lower is complete. After writing to this register, two complete frame times are required to imple- ment the new settings. Writing to any of the above registers before the implementation is complete may put the chip into an undefined state requiring a reset. The “Busy” bit in the Extended_Config register may be used in lieu of a timer to determine when it is safe to write. See the Extended_Config register for more details. The following table lists some Frame_Period values for popular frame rates (clock rate = 24MHz). In addition, the three bound registers must also follow this rule when set to non-default values: Frame_Period_Max_Bound ≥ Frame_Period_Min_Bound + Shutter_Max_Bound. Frames/second Counts Frame_Period Decimal Hex Upper Lower 7080 3,390 0D3E 0D 3E 5000 4,800 12C0 12 C0 3000 8,000 1F40 1F 40 2000 12,000 2EE0 2E E0

Frame_Period_Min_Bound_Lower Address: 0x1B Access: Read/Write Default Value: 0x7E Bit 7 6 5 4 3 2 1 0 Field FBm7 FBm6 FBm5 FBm4 FBm3 FBm2 FBm1 FBm0 Frame_Period_Min_Bound_Upper Address: 0x1C Access: Read/Write Default Value: 0x0E Bit 7 6 5 4 3 2 1 0 Field FBm15 FBm14 FBm13 FBm13 FBm11 FBm10 FBm9 FBm8 Data Type: 16-bit unsigned integer. USAGE: This value sets the minimum frame period (the MAXIMUM frame rate) which may be selected by the automatic frame rate control. Units are clock cycles. The formula is Frame Rate = Clock Rate / Register value To read from the registers, read Upper first followed by Lower. To write to the registers, write Lower first, followed by Upper, then execute a write to the Frame_Period_Max_Bound_Upper and Lower registers. The minimum allowed write value is 0x0E7E; the maximum is 0xFFFF. Reading this register will return the most recent value that was written to it. However, the value will take effect only after a write to the Frame_Period_Max_Bound_Upper and Lower registers. After writing to Frame_Period_Max_ Bound_Upper, wait at least two frame times before writing to Frame_Period_Min_Bound_Upper or Lower again. The “Busy” bit in the Extended_Config register may be used in lieu of a timer to determine when it is safe to write. See the Extended_Config register for more details. In addition, the three bound registers must also follow this rule when set to non-default values: Frame_Period_Max_Bound ≥ Frame_Period_Min_Bound + Shutter_Max_Bound.

SROM_ID Address: 0x1F Access: Read Default Value: Version dependent Bit 7 6 5 4 3 2 1 0 Field SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 Data Type:8-Bit unsigned integer. USAGE: Contains the revision of the downloaded Shadow ROM firmware. If the firmware has been successfully down- loaded and the chip is operating out of SROM, this register will contain the SROM firmware revision, otherwise it will contain 0x00. Note: The IC hardware revision is available by reading the Revision_ID register (register 0x01). Shutter_Max_Bound_Lower Address: 0x1D Access: Read/Write Default Value: 0x20 Bit 7 6 5 4 3 2 1 0 Field SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0 Shutter_Max_Bound_Upper Address: 0x1E Access: Read/Write Default Value: 0x4E Bit 7 6 5 4 3 2 1 0 Field SB15 SB14 SB13 SB12 SB11 SB10 SB9 SB8 Data Type: 16-bit unsigned integer. USAGE: This value sets the maximum allowable shutter value when operating in automatic mode. Units are clock cycles. Since the automatic frame rate function is based on shutter value, the value in these registers can limit the range of the frame rate control. To read from the registers, read Upper first followed by Lower. To write to the registers, write Lower first, followed by Upper, then execute a write to the Frame_Period_Max_Bound_Upper and Lower registers. To set the shutter manually, disable the AGC via the Extended_Config register and write the desired value to these registers. Reading this register will return the most recent value that was written to it. However, the value will take effect only after a write to the Frame_Period_Max_Bound_Upper and Lower registers. After writing to Frame_Period_Max_Bound_ Upper, wait at least two frame times before writing to Shutter_Max_Bound_Upper or Lower again. The “Busy” bit in the Extended_Config register may be used in lieu of a timer to determine when it is safe to write. See the Extended_Config register for more details. In addition, the three bound registers must also follow this rule when set to non-default values: Frame_Period_Max_Bound ≥ Frame_Period_Min_Bound + Shutter_Max_Bound.

LP_CFG0 Address: 0x2C Access: Read/Write Default Value: 0x7F Bit 7 6 5 4 3 2 1 0 Field Match LP6 LP5 LP4 LP3 LP2 LP1 LP0 Data Type: 8-bit unsigned integer USAGE: This register is used to set the laser current and bin matching parameter. It is to be used together with register 0x2D where register 0x2D must contain the complement of register 0x2C in order for the laser current to be pro - grammed. Writing to this register causes a fault test to be performed on the XY_LASER pin. The test checks for stuck low and stuck high conditions. During the test, LASER_NEN will be driven high and XY_LASER will pulse high for 12us and pulse low for 12us (times are typical). Both pins will return to normal operation if no fault is detected. LP_CFG1 Address: 0x2D Access: Read/Write Default Value: 0x80 Bit 7 6 5 4 3 2 1 0 Field LPC7 LPC6 LPC5 LPC4 LPC3 LPC2 LPC1 LPC0 Data Type: 8-bit unsigned integer USAGE: The value in this register must be a complement of register 0x2C for laser current to be as programmed, oth- erwise the laser current is set to 33.85%. Registers 0x2C and 0x2D may be written in any order after power ON reset or SROM download. Field Name Description Match Match the sensor to the VCSEL characteristics. Set per the bin table specification for the VCSEL bin in use. LP6 - LP0 Controls the 7 bit DAC for adjusting laser current.One step is equivalent to (1/192)*100% = 0.5208% drop of relative laser current.Refer to the table below for example of relative laser current settings. LP6- LP3 LP2 LP1 LP0 Relative Laser Current 0000 0 0 0 100% 0000 0 0 1 99.48% 0000 0 1 0 98.96% 0000 0 1 1 98.43% 0000 1 0 0 97.92% : : : : : 1111 1 0 1 34.90% 1111 1 1 0 34.38% 1111 1 1 1 33.85%

Observation Address: 0x3D Access: Read/Write Default Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field OB7 Reserved OB5 Reserved Reserved Reserved OB1 OB0 Data Type: Bit field USAGE: Each bit is set by some process or action at regular intervals, or when the event occurs. The user must clear the register by writing 0x00, wait an appropriate delay, and read the register. The active processes will have set their corresponding bit(s). This register may be used as part of a recovery scheme to detect a problem caused by EFT/B or ESD. Reserved Address: 0x3E Reserved Address: 0x2f-0x3C Inverse_Product_ID Address: 0x3F Access: Read Default Value: 0xE3 Bit 7 6 5 4 3 2 1 0 Field NPID7 NPID6 NPID5 NPID4 NPID3 NPID2 NPID1 NPID0 Data Type: Inverse 8-Bit unsigned integer USAGE: This value is the inverse of the Product_ID, located at the inverse address. It can be used to test the SPI port. Field Name Description OB7 0 = Chip is not running SROM code 1 = Chip is running SROM code OB5 0 = NPD pulse was not detected 1 = NPD pulse was detected OB1 Set once per frame OB0 Set once per frame

SROM_Load Address: 0x 60 Access: Write Default Value: N/A Bit 7 6 5 4 3 2 1 0 Field SL7 SL6 SL5 SL4 SL3 SL2 SL1 SL0 Data Type: Eight bit unsigned integer USAGE: The SROM_Load register is used for high-speed programming of the ADNS-6010 from an external PROM or microcontroller. See the Synchronous Serial Port section for use details. Motion_Burst Address: 0x50 Access: Read Default Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field MB7 MB6 MB5 MB4 MB3 MB2 MB1 MB0 Data Type: Various, depending on data USAGE: The Motion_Burst register is used for high-speed access to the Motion, Delta_X, Delta_Y, SQUAL, Shutter_Up- per, Shutter_Lower, and Maximum_Pixel registers. See the Synchronous Serial Port section for use details. Pixel_Burst Address: 0x40 Access: Read Default Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Data Type: Eight bit unsigned integer USAGE: The Pixel_Burst register is used for high-speed access to all the pixel values from one and 2/3 complete frame. See the Synchronous Serial Port section for use details.

Single-Mode Vertical-Cavity Surface Emitting Laser (VCSEL) Figure 31. Outline drawing for ADNV-6340 VCSEL.

  • Advanced Technology VCSEL chip
  • Single Mode Lasing operation
  • Non-hermetic plastic package
  • 832-865 nm wavelength
  • Enhanced ESD up to 2-KV

This advanced class of VCSELs was engineered by Avago Technologies providing a laser diode with a single lon - gitudinal as well as a single transverse mode. In contrast to most oxide-based single-mode VCSELs, these VCSELs remain within a single mode operation over a wide range of output power. When compared to an LED, the ADNV- 6340 has a significantly lower power consumption mak- ing it an ideal choice for optical navigation applications. (5.25) AT SHOULDER 7.22 5.25 ± 0.65 AT LEAD TIP 5.722X 90° 3.28 CATHODE FLAT 4.70 ± 0.05 (BASE) 1° MAX. 0.90 0.50 0.25 5.36 4.3 KAPTON TAPE = BIN NUMBER = BIN LETTER = SUBCONTRACTOR CODE = DIE SOURCE W X Y Z +3° - 5 °

Figure 32. Suggested ADNV-6340 PCB mounting guide.

  1. Stresses greater than those listed under “Absolute

period of time may affect device reliability.

  1. The maximum ratings do not reflect eye-safe opera -

7050 laser sensor datasheet.

  1. The inherent design of this component causes it to be

Figure 35. Junction temperature rise vs. forward current. Figure 36. Recommended reflow soldering profile.

120 SEC

ADNS-6120 and ADNS-6130-001 Laser Mouse Lens Figure 37. ADNS-6120 laser mouse round lens outline drawings and details The ADNS-6120 and ADNS-6130-001 laser mouse lens are designed for use with Avago Technologies laser mouse sensors and the illumination subsystem provided by the ADNS-6230-001 VCSEL assembly clip and the ADNV-6340 Single-Mode Vertical-Cavity Surface Emitting Lasers (VCSEL). Together with the VCSEL, the ADNS-6120 or ADNS-6130-001 laser mouse lens provides the directed illumination and optical imaging necessary for proper operation of the laser mouse sensor. ADNS-6120 or ADNS-6130-001 laser mouse lens is a precision molded optical component and should be handled with care to avoid scratching of the optical surfaces.

Figure 40. Logo locations

Figure 41. Illustration of base plate mounting features for ADNS-6120 laser mouse round lens All specifications are based on the Mechanical Assembly Requirements. Technologies sales representative.

Figure 42. Illustration of base plate mounting features for ADNS-6130-001 laser mouse trim lens

Laser Mouse VCSEL Assembly Clip Figure 43. Outline Drawing for ADNS-6230-001 VCSEL Assembly Clip The ADNS-6230-001 VCSEL Assembly Clip is designed to provide mechanical coupling of the ADNV-6340 VCSEL to the ADNS-6120 or ADNS-6130-001 Laser Mouse Lens. This coupling is essential to achieve the proper illumina- tion alignment required for the sensor to operate on a wide variety of surfaces.

For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries. Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0104EN AV02-0118EN - August 17, 2007