ADNS-3090

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Document overview

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Technical content

Features

/g120 High speed motion detection – up to 60 ips and 20g /g120 Enhanced architecture for greatly improved optical navigation technology /g120 Programmable frame rate over 6400 frames per second /g120 SmartSpeed self-adjusting frame rate for optimum performance /g120 Serial port burst mode for fast data transfer /g120 1800 cpi or 3500 cpi selectable resolution /g120 Single 3.3 volt power supply /g120 Four-wire serial port along with Chip Select, Power Down, and Reset pins

Applications

/g120 Mice for game consoles and computer games /g120 Mice for desktop PC’s, Workstations, and portable PC’s /g120 Trackballs /g120 Integrated input devices ADNS-3090 High-Performance Optical Mouse Sensor Data Sheet

1 NCS Chip select

2 MISO Serial data output

3 SCLK Serial clock input

4 MOSI Serial data input

5 LED_CTRL LED control output

6 RESET Reset input

7 NPD Power down

8 OSC_OUT Oscillator output

9 GUARD Oscillator GND for PCB guard

10 OSC_IN Oscillator input

11 NC No connect

12 OPTP Connect to VDD3

13 REFC Reference capacitor

14 REFB Reference capacitor

15 VDD3 Supply voltage

16 GND Ground

17 VDD3 Supply voltage

18 NC No connect

19 GND Ground

20 NC No connect

Figure 1. Package outline drawing (top view)

Figure 2. Package outline drawing damage and/or degradation which may be induced by ESD.

align it to the sensor, base plate, and clip with the LED. the alignment features on the base plate. Figure 3. Recommended PCB mechanical cutouts and spacing defined features on the base plate. stop and features on the package that align to the lens.

Figure 4. 2D Assembly drawing of ADNS-3090 (top and side view) that require a different PCB mounting method to optimize the navigation performance. Refer Application Notes AN 5035 for further information.

Figure 5. Exploded view drawing

1. Insert the sensor and all other electrical components
2. Insert the LED into the assembly clip and bend the
3. Insert the LED/clip assembly into PCB.
4. Wave Solder the entire assembly in a no-wash solder

needed to protect the sensor during the solder process. lead shoulders do not normally rest on the PCB surface.

1. Place the lens onto the base plate.

Figure 6. Block diagram of ADNS-3090 optical mouse sensor

3.3 V POWER

1. Remove the protective kapton tape from optical
2. Insert PCB assembly over the lens onto the base plate

erture ring should self-align to the lens.

1. The optical position reference for the PCB is set by the
2. Install mouse top case. There MUST be a feature in the

Figure 7. Cross section of PCB assembly nologies supplied IGES file and ADNS-2120-001 flange.

Figure 8. Schematic Diagram for USB, PS/2 mouse application with ADNS-3090

1. Caps for pins 15 and 17 MUST have trace lengths LESS than 5 mm to nearest ground pin.
2. Pins 15 and 17 caps MUST use pin 16 GND.
3. Pin 9, if used, should not be connected to PCB GND to reduce potential RF emissions.
4. The 0.1 uF caps must be ceramic.
5. Caps should have less than 5 nH of self inductance.
6. Caps should have less than 0.2 Ω ESR.
7. NC pins should not be connected to any traces.
8. Surface mount parts are recommended.
9. Care must be taken when interfacing a 5V microcontroller to the ADNS-3090. Serial port inputs on the sensor should be connec ted to open-

through a resistor divider or other level shifting technique.

1. VDD3 and GND should have low impedance connections to the power supply.
2. Capacitors connected to pin 15 and 17 should be connected to pin 16 and then to pin 19.

24 MHz

1.3 K/g58

15 D -

6 MHz

1 K/g58

24 MHz and 6 MHz close to chip

1 NCS

10 K/g58

following Avago Technologies’ recommendations. lowing Avago Technologies’ recommendations. Avago Technologies’ recommendations. /g120 UL flammability level UL94 V-0. mouse according to usage instructions above. Figure 9. Distance from lens reference plane to surface

Parameter Symbol Minimum Typical Maximum Units Notes Storage Temperature T S -40 85 oC Operating Temperature T A -15 55 oC Lead Solder Temp 260 oC For 7 second, 1.6mm below seat- ing plane. Supply Voltage V DD3 -0.5 3.7 V ESD 2 kV All pins, human body model MIL 883 Method 3015 Input Voltage V IN -0.5 V DD3+0.5 V NPD, NCS, MOSI, SCLK, RESET, OSC_IN, OSC_OUT, REFC. Output current I out 20 mA LED_CTRL, MISO Recommended Operating Conditions Parameter Symbol Minimum Typical Maximum Units Notes Operating Temperature T A 04 0 ° C Power supply voltage V DD3B 3.10 3.30 3.60 Volts Power supply rise time V RT 1 us 0 to 3.0V Supply noise (Sinusoidal) VNB 30 mV p-p 10kHz- 300KHZ 300KHz-50MHz Oscillator capable Frequency fCLK 23 24 25 MHz Set by ceramic resonator Serial Port Clock Frequency fSCLK 2 500 MHz kHz Active drive, 50% duty cycle Open drain drive with pull-ups on, 50 pF load Resonator Impedance X RES 55 /g58 Distance from lens reference plane to surface Z 2.3 2.4 2.5 mm Results in ±0.2 mm DOF, See Figure 9 Speed S 0 60 in/sec @ 6469fps Acceleration A 20 g @ 6469fps Light level onto IC IRR INC 20 100 120 6,000 7,200 6,000 7,200 mW/m2 l = 639 nm, FR=1500 fps l = 875 nm, FR=1500 fps l = 639 nm, FR=6469 fps l = 875 nm, FR=6469 fps Frame Rate FR 2000 6469 Frames/s See Frame_Period register section LED Drive Current I LED 10 mA HLMP-ED80-XX000, bin N and brighter. Maximum frame rate may not be maintained on dark surfaces at the minimum LED drive current

Parameter Symbol Min. Typical Max. Units Notes VDD to RESET t OP 250 /g80s From VDD = 3.0V to RESET sampled Data delay after RESET tPU-RESET 35 ms From RESET falling edge to valid motion data at 2000 fps and shutter bound 8290. Input delay after reset TIN-RST 500 /g80s From RESET falling edge to inputs active (NPD, MOSI, NCS, SCLK) Power Down t PD 2.1 ms From NPD falling edge to initiate the power down cycle at 500fps (tpd = 1 frame period + 100ms ) Wake from NPD t PUPD 75 ms From NPD rising edge to valid motion data at 2000 fps and shutter bound 8290. Max assumes surface change while NPD is low. Data delay after NPD t COMPUTE 3.1 ms From NPD rising edge to all registers contain data from new images at 2000fps (see Figure 10) . RESET pulse width t PW-RESET 10 /g80s MISO rise time t r-MISO 40 200 ns C L = 50pF MISO fall time t f-MISO 40 200 ns C L = 50pF MISO delay afterSCLK tDLY-MISO 120 ns From SCLK falling edge to MISO data valid, no load conditions MISO hold time t hold-MISO 250 ns Data held until next falling SCLK edge MOSI hold time t hold-MOSI 200 ns Amount of time data is valid after SCLK rising edge MOSI setup time t setup-MOSI 120 ns From data valid to SCLK rising edge SPI time between write commands tSWW 50 /g80s From rising SCLK for last bit of the first data byte, to rising SCLK for last bit of the second data byte. SPI time between write and read commands t SWR 50 /g80s From rising SCLK for last bit of the first data byte, to rising SCLK for last bit of the second address byte. SPI time between read and subsequent commands t SRW tSRR 250 ns From rising SCLK for last bit of the first data byte, to falling SCLK for first bit of the second address byte. SPI read address-data delay t SRAD 50 /g80s From rising SCLK for last bit of the address byte, to falling SCLK for first bit of data being read. All registers except Motion & Motion_Burst SPI motion read address-data delay t SRAD-MOT 75 /g80s From rising SCLK for last bit of the address byte, to falling SCLK for first bit of data being read. Applies to 0x02 Motion, and 0x50 Motion_Burst, registers NCS to SCLK active t NCS-SCLK 120 ns From NCS falling edge to first SCLK rising edge SCLK to NCS inactive t SCLK-NCS 120 ns From last SCLK falling edge to NCS rising edge, for valid MISO data transfer NCS to MISO high-Z t NCS-MISO 250 ns From NCS rising edge to MISO high-Z state SROM download and frame capture byte-to-byte delay t LOAD 10 /g80s (see Figure 23 and 24) NCS to burst mode exit tBEXIT 4 /g80s Time NCS must be held high to exit burst mode Transient Supply Current IDDT 85 mA Max supply current during a V DD3 ramp from 0 to 3.6V

Figure 10. NPD Rising Edge Timing Detail IDD_AVG 52 mA DC average at 6469 fps. No DC load on LED_CTRL, MISO.

The synchronous serial port is used to set and read pa- rameters in the ADNS-3090, and to read out the motion information. The serial port is also used to load SROM data into the ADNS-3090. The port is a four-wire, serial port. The host micro-con- troller always initiates communication; the ADNS-3090 never initiates data transfers. The serial port cannot be activated while the chip is in power down mode (NPD low) or reset (RESET high). SCLK, MOSI, and NCS may be driven directly by a 3.3V output from a micro-controller, or they may be placed in an open drain configuration by enabling on-chip pull-up current sources. The open drain drive allows the use of a 5V micro-controller without any level shifting components. The port pins may be shared with other SPI slave devices. When the NCS pin is high, the inputs are ignored and the output is tri-stated. The lines which comprise the SPI port are: SCLK: Clock input. It is always generated by the master (the micro- controller). MOSI: Input data (Master Out/Slave In). MISO: Output data (Master In/Slave Out). NCS: Chip select input (active low). NCS needs to be low to activate the serial port; otherwise, MISO will be high-Z, and MOSI & SCLK will be ignored. NCS can also be used to reset the serial port in case of an error. Chip Select Operation The serial port is activated after NCS goes low. If NCS is raised during a transaction, the entire transaction is aborted and the serial port will be reset. This is true for all transactions including SROM download. After a transaction is aborted, the normal address-to-data or transaction-to-transaction delay is still required before beginning the next transaction. To improve communica- tion reliability, all serial transactions should be framed by NCS. In other words, the port should not remain enabled during periods of non-use because ESD and EFT/B events could be interpreted as serial communication and put the chip into an unknown state. In addition, NCS must be raised after each burst-mode transaction is complete to terminate burst-mode. The port is not available for further use until burst-mode is terminated.

Figure 17. Read operation

0 A 6 A 5 A 4 A 3 A 2 A 1 A 0

Figure 15. MOSI setup and hold time Figure 18. MISO delay and hold time on every rising edge of SCLK. MISO until the falling edge of SCLK. Figure 16. Write Operation

Figure 22. Motion burst timing

byte (hexadecimal representation) on a single line.

1. Perform hardware reset by toggling the RESET pin
2. Write 0x44 to register 0x20
3. Write 0x07 to register 0x23
4. Write 0x88 to register 0x24
5. Wait at least 1 frame period
6. Write 0x18 to register 0x14 (SROM_Enable register)
7. Begin burst mode write of data file to register 0x60

Figure 23. SROM download burst mode

be reloaded afterwards if required. before the data is ready, it will return all zeros. 636 bytes will be approximately 2/3 of the next frame. description for more information. Figure 24. Frame capture burst mode timing

1. MSB = 1 for all bytes. Bit 6 = 0 for all bytes except pixel 0 of both frames which has bit 6 = 1 for use as a frame marker.
2. Reading beyond pixel 899 will return the first pixel of the second partial frame.
3. tCAPTURE = 10ms + 3 frame periods.
4. This figure illustrates reading a single complete frame of 900 pixels. An additional 636 pixels from the next frame are available.

Figure 25. Pixel address map (surface referenced) The pixel output order as related to the surface is shown below.

• ··
• ·· Error detection and recovery 1. The ADNS-3090 and the micro-controller might get out of synchronization due to ESD events, power supply droops or micro-controller firmware flaws. In such a case, the micro-controller should pulse NCS high for at least 1 ms. The ADNS-3090 will reset the serial port (but not the control registers) and will be prepared for the beginning of a new transmission after the normal transaction delay. 2. Invalid addresses: Writing to an invalid address will have no effect. Reading from an invalid address will return all zeros. 3. Termination of a transmission by the micro-controller may sometimes be required (for example, due to a USB suspend interrupt during a read operation). To accomplish this the micro-controller should raise NCS. The ADNS-3090 will not write to any register and will reset the serial port (but not the control registers) and be prepared for the beginning of future transmissions after NCS goes low. The normal delays between reads or writes (t SWW, tswr, tSRAD, tSRAD-mot) are still required after aborted transmissions. 4. The micro-controller can verify success of write opera- tions by issuing a read command to the same address and comparing written data to read data. 5. The micro-controller can verify the synchronization of the serial port by periodically reading the product ID and inverse product ID registers. 6. The microcontroller can read the SROM_ID register to verify that the sensor is running downloaded SROM code. ESD or similar noise events may cause the sensor to revert to native ROM execution. If this should hap- pen, pulse RESET and reload the SROM instructions.

Notes on Power-up and the serial port Reset Circuit The ADNS-3090 does not perform an internal power up self-reset. The reset pin must be raised and lowered to reset the chip. This should be done every time power is applied. During power-up there will be a period of time after the power supply is high but before any clocks are available. The table below shows the state of the various pins during power-up and reset when the RESET pin is driven high by a micro-controller. Power Down Circuit The following table lists the pin states during power down. The chip is put into the power down (PD) mode by lowering the NPD input. When in PD mode, the oscilla- tor is stopped but all register contents are retained. To achieve the lowest current state, all inputs must be held externally within 200mV of a rail, either ground or V DD3. The chip outputs are driven low or hi-Z during PD to prevent current consumption by an external load. LED Drive Mode The LED has 2 modes of operation: DC and Shutter. In DC mode it is on at all times the chip is powered except when in the power down mode via the NPD pin. In shutter mode the LED is on only during the portion of the frame that light is required. The LED_MODE bit in the Configuration_bits register sets the LED mode. State of Signal Pins After VDD is Valid Pin Before Reset During Reset After Reset SPI pullups Undefined Off On (default) NCS Hi-Z control functional Hi-Z control functional Functional MISO Driven or hi-Z (per NCS) Driven or hi-Z (per NCS) Low or hi-Z (per NCS) SCLK Undefined Ignored Functional MOSI Undefined Ignored Functional LED_CTRL Undefined Low High RESET Functional High (externally driven) Functional NPD Undefined Ignored Functional State of Signal Pins During Power Down Pin NPD low After wake from PD SPI pullups off pre-PD state NCS hi-Z control functional functional MISO low or hi-Z (per NCS) pre-PD state or hi-Z SCLK ignored functional MOSI ignored functional LED_CTRL low high RESET functional functional NPD low (driven externally) functional REFC V DD3 REFC OSC_IN low OSC_IN OSC_OUT high OSC_OUT

The ADNS-3090 registers are accessible via the serial port. The registers are used to read motion data and status as well as to set the device configuration. Address Register Read/Write SROM Default Value 0x00 Product_ID R 0x17 0x01 Revision_ID R 0xNN 0x02 Motion R 0x00 0x03 Delta_X R 0x00 0x04 Delta_Y R 0x00 0x05 SQUAL R 0x00 0x06 Pixel_Sum R 0x00 0x07 Maximum_Pixel R 0x00 0x08 Reserved 0x09 Reserved 0x0a Configuration_bits R/W 0x09 0x0b Extended_Config R/W 0x00 0x0c Data_Out_Lower R Any 0x0d Data_Out_Upper R Any 0x0e Shutter_Lower R 0x85 0x0f Shutter_Upper R 0x00 0x10 Frame_Period_Lower R Any 0x11 Frame_Period_Upper R Any 0x12 Motion_Clear W Any 0x13 Frame_Capture R/W 0x00 0x14 SROM_Enable W 0x00 0x15 - 0x18 Reserved 0x19 Frame_Period_Max_Bound Lower R/W 0xE0 0x1a Frame_Period_Max_Bound_Upper R/W 0x2E 0x1b Frame_Period_Min_Bound_Lower R/W 0x7E 0x1c Frame_Period_Min_Bound_Upper R/W 0x0E 0x1d Shutter_Max_Bound_Lower R/W 0x00 0x1e Shutter_Max_Bound_Upper R/W 0x20 0x1f SROM_ID R 0x00 0x20-0x3c Reserved 0x3d Observation R/W 0x00 0x3e Reserved 0x3f Inverse Product ID R 0xF8 0x40 Pixel_Burst R 0x00 0x50 Motion_Burst R 0x00 0x60 SROM_Load W Any

Product_ID Address: 0x00 Access: Read Reset Value: 0x07 B i t 76543210 Field PID 7 PID6 PID5 PID4 PID3 PID2 PID1 PID0 Data Type: 8-Bit unsigned integer USAGE: This register contains a unique identification assigned to the ADNS-3090. The value in this register does not change; it can be used to verify that the serial communications link is functional. Revision_ID Address: 0x01 Access: Read Reset Value: 0xNN B i t 76543210 Field RID 7 RID6 RID5 RID4 RID3 RID2 RID1 RID0 Data Type: 8-Bit unsigned integer. USAGE: This register contains the IC revision. It is subject to change when new IC versions are released. NOTE: The downloaded SROM firmware revision is a separate value and is available in the SROM_ID register. Motion Address: 0x02 Access: Read Reset Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field MOT Reserved Reserved OVF Reserved Reserved Reserved RES Data Type: Bit field. USAGE: Register 0x02 allows the user to determine if motion has occurred since the last time it was read. If so, then the user should read registers 0x03 and 0x04 to get the accumulated motion. It also tells if the motion buffers have overflowed, and the current resolution setting. Field Name Description MOT Motion since last report or PD 0 = No motion 1 = Motion occurred, data ready for reading in Delta_X and Delta_Y registers OVF Motion overflow, Delta_Y and/or Delta_X buffer has overflowed since last report 0 = no overflow 1 = Overflow has occurred RES Resolution in counts per inch 0 = 3500 1 = 1800

Notes for Motion: 1. Reading this register freezes the Delta_X and Delta_Y register values. Read this register before reading the Delta_X and De lta_Y registers. If Delta_X and Delta_Y are not read before the motion register is read a second time, the data in Delta_X and Delta_Y will be lost. 2. Avago Technologies RECOMMENDS that registers 0x02, 0x03 and 0x04 be read sequentially. See Motion burst mode also. 3. Internal buffers can accumulate more than eight bits of motion for X or Y. If either one of the internal buffers overflows, then absolute path data is lost and the OVF bit is set. This bit is cleared once some motion has been read from the Delta_X and Delta_Y registers, and if the buffers are not at full scale. Since more data is present in the buffers, the cycle of reading the Motion, Delta_X and Delta_Y registers sh ould be repeated until the motion bit (MOT) is cleared. Until MOT is cleared, either the Delta_X or Delta_Y registers will read either positive or negative full scale. If the motion register has not been read for long time, at 1800 cpi it may take up to 72 read cycles to clear the buffers, at 35 00 cpi, up to 140 cycles. Alternatively, writing to the Motion_Clear register (register 0x12) will clear all stored motion at once. Delta_X Address: 0x03 Access: Read Reset Value: 0x00 B i t 76543210 Field X 7 X6 X5 X4 X3 X2 X1 X0 Data Type: Eight bit 2’s complement number. USAGE: X movement is counts since last report. Absolute value is determined by resolution. Reading clears the register. Delta_Y Address: 0x04 Access: Read Reset Value: 0x00 B i t 76 543210 Field Y 7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Data Type: Eight bit 2’s complement number. USAGE: Y movement is counts since last report. Absolute value is determined by resolution. Reading clears the register. 00 01 02 7E 7F +127+126+1 +2 FFFE8180 0-1-2-127-128Motion Delta_X 00 01 02 7E 7F +127+126+1 +2 FFFE8180 0-1-2-127-128Motion Delta_Y

Pixel_Sum Address: 0x06 Access: Read Reset Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field AP 7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Data Type: High 8 bits of an unsigned 16-bit integer. USAGE: This register is used to find the average pixel value. It reports the upper byte of a 16-bit counter which sums all 900 pixels in the current frame. It may be described as the full sum divided by 256. To find the average pixel value, use the following formula: Average Pixel = Register Value * 256 / 900 = Register Value/3.51 The maximum register value is 221 (63 * 900/256 truncated to an integer). The minimum is 0. The pixel sum value can change on every frame. Maximum_Pixel Address: 0x07 Access: Read Reset Value: 0x00 B i t 76543210 Field 0 0 MP 5 MP4 MP3 MP2 MP1 MP0 Data Type: Six bit number. USAGE: Maximum Pixel value in current frame. Minimum value = 0, maximum value = 63. The maximum pixel value can vary with every frame. Reserved Address: 0x08 Reserved Address: 0x09

Configuration_bits Address: 0x0a Access: Read/Write Reset Value: 0x09 B i t 76 543210 Field 0 LED_MODE Sys Test RES Reserved Reserved Reserved Reserved Data Type: Bit field USAGE: Register 0x0a allows the user to change the configuration of the sensor. Shown below are the bits, their default values, and optional values. Field Name Description BIT 7 Must always be zero LED_MODE LED Shutter Mode 0 = Shutter mode off (LED always on) 1 = Shutter mode on (LED only on when illumination is required) Sys Test System Tests 0 = no tests 1 = perform all system tests, output 16 bit CRC via Data_Out_Upper and Data_Out_Lower registers. NOTE: The test will fail if SROM is loaded. Perform a hardware reset before executing this test. Reload SROM after the test is completed. NOTE: Since part of the system test is a RAM test, the RAM and SRAM will be overwritten with the default values when the test is done. If any configuration changes from the default are needed for operation, make the changes AFTER the system test is run. The system test takes 200ms (@24MHz) to complete. NOTE: Do not access the Synchronous Serial Port during system test. RES Resolution in counts per inch 0 = 3500 1 = 1800

Extended_Config Address: 0x0b Access: Read/Write Reset Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field Busy Reserved Reserved Reserved Reserved Serial_NPU NAGC Fixed_FR Data Type: Bit field USAGE: Register 0x0b allows the user to change the configuration of the sensor. Shown below are the bits, their default values, and optional values. Field Name Description Busy Read-only bit. Indicates if it is safe to write to one or more of the following registers: Frame_Period_Max_Bound_Upper and Lower Frame_Period_Min_Bound_Upper and Lower Shutter_Max_Bound_Upper and Lower After writing to the Frame_Period_Max_Bound_Upper register, at least two frames must pass before writing again to any of the above registers. This bit may be used in lieu of a timer since the actual frame rate may not be known when running in auto mode. 0 = writing to the registers is allowed 1 = do not write to the registers yet Serial_NPU Disable serial port pull-up current sources 0 = no, current sources are on 1 = yes, current sources are off NAGC Disable AGC. Shutter will be set to the value in the Shutter_Max_Bound registers. 0 = no, AGC is active 1 = yes, AGC is disabled Fixed_FR Fixed frame rate (disable automatic frame rate control). When this bit is set, the frame rate will be determined by the value in the Frame_Period_Max_Bound registers. 0 = automatic frame rate 1 = fixed frame rate

Data_Out_Lower Address: 0x0c Access: Read Reset Value: Undefined B i t 76543210 Field DO 7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Data_Out_Upper Address: 0x0d Access: Read Reset Value: Undefined B i t 7654321 0 Field DO 15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 Data Type: Sixteen bit word. USAGE: Data in these registers come from the system self test or the SROM CRC test. The data can be read out 0x0d, or 0x0d first, then 0x0c. Data_Out_Upper Data_Out_Lower System test results: 0x1B 0xBF SROM CRC Test Result: 0xBE 0xEF System Test: This test is initiated via the Configuration_Bits register. It performs several tests to verify that the hardware is functioning correctly. Perform a hardware reset just prior to running the test. SROM contents and register settings will be lost. SROM CRC Test: Performs a CRC on the SROM contents. The test is initiated by writing a particular value to the SROM_ Enable register. Shutter_Lower Address: 0x0e Access: Read Reset Value: 0x85 Bit 7 6 5 4 3 2 1 0 Field S 7 S6 S5 S4 S3 S2 S1 S0

Frame_Period_Lower Address: 0x10 Access: Read Reset Value: Undefined Bit 7 6 5 4 3 2 1 0 Field FP 7 FP6 FP5 FP4 FP3 FP2 FP1 FP0 Frame_Period_Upper Address: 0x11 Access: Read Reset Value: Undefined Bit 7 6 5 4 3 2 1 0 Field FP 15 FP14 FP13 FP12 FP11 FP10 FP9 FP8 Data Type: Sixteen bit unsigned integer. USAGE: Read these registers to determine the current frame period and to calculate the frame rate. Units are clock cycles. The formula is Frame Rate = Clock Frequency/Register value To read from the registers, read Frame_Period_Upper first followed by Frame_Period Lower. To set the frame rate manually, disable automatic frame ra te mode via the Extended_Config register and write the desired count value to the Frame_Period_Maximum_Bound registers. The following table lists some Frame_Period values for popular frame rates with a 24MHz clock. Frames/second Counts Frame_Period Decimal Hex Upper Lower 6469 3,710 OE7E OE 7E 5000 4,800 12C0 12 C0 3000 8,000 1F40 1F 40 2000 12,000 2EE0 2E E0 Motion_Clear Address: 0x12 Access: Write Reset Value: Undefined Data Type: Any. USAGE: Writing any value to this register will cause the Delta_X, Delta_Y, and internal motion registers to be cleared. Use this as a fast way to reset the motion counters to zero without resetting the entire chip.

Frame_Capture Address: 0x13 Access: Read/Write Reset Value: 0x00 B i t 7654321 0 Field FC 7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 Data Type: Bit field USAGE: Writing 0x83 to this register will cause the next available complete 1 2/3 frames of pixel values to be stored to SROM RAM. Writing to this register is required before using the Frame Capture burst mode to read the pixel values (see the Synchronous Serial Port section for more details). Writing to this register will stop navigation and cause any firmware loaded in the SROM to be overwritten. A hardware reset is required to restore navigation, and the firmware must be reloaded using the SROM Download burst method. This register can also be used to read the frame capture data. The same data available by reading the Pixel_Burst register using burst mode is available by reading this register in the normal fashion. The data pointer is automatically incremented after each read so all 1536 pixel values (1 and 2/3 frames) may be obtained by reading this register 1536 times in a row. Both methods share the same pointer such that reading pixel values from this register will increment the pointer causing subsequent reads from the Pixel_Burst register (without initiating a new frame dump) to start at the current pointer location. This register will return all zeros if read before the frame capture data is ready. See the Frame Capture description in the Synchronous Serial Port section for more information. This register will not retain the last value written. Reads will return zero or frame capture data. SROM_Enable Address: 0x14 Access: Write Reset Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field SE 7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 Data Type: 8-bit number. USAGE: Write to this register to start either SROM download or SROM CRC test. Write 0x18 to this register before downloading SROM firmware to the SROM_Load register. The download will not be successful unless this register contains the correct value. Write 0xA1 to start the SROM CRC test. Wait 7ms plus one frame period , then read result from the Data_Out_Lower and Data_Out_Upper registers. Navigation is halted and the SPI port should not be used during this test. Reserved Address: 0x15 – 0x18

Frame_Period_Max_Bound_Lower Address: 0x19 Access: Read/Write Reset Value: 0xE0 Bit 7 6 5 4 3 2 1 0 Field FBm 7 FBm6 FBm5 FBm4 FBm3 FBm2 FBm1 FBm0 Frame_Period_Max_Bound_Upper Address: 0x1A Access: Read/Write Reset Value: 0x2E B i t 7654321 0 Field FBm 15 FBm14 FBm13 FBm12 FBm11 FBm10 FBm9 FBm8 Data Type: 16-bit unsigned integer. USAGE: This value sets the maximum frame period (the MINIMUM frame rate) which may be selected by the automatic frame rate control, or sets the actual frame period when operating in manual mode. Units are clock cycles. The formula is Frame Rate = Clock Frequency / Register value To read from the registers, read Upper first followed by Lower. To write to the registers, write Lower first, followed by Upper. To set the frame rate manually, disable automatic frame rate mode via the Extended_Config register and write the desired count value to these registers. Writing to the Frame_Period_Max_Bound_Upper and Lower registers also activates any new values in the following registers:

• Frame_Period_Max_Bound_Upper and Lower
• Frame_Period_Min_Bound_Upper and Lower
• Shutter_Max_Bound_Upper and Lower Any data written to these registers will be saved but will not take effect until the write to the Frame_Period_Max_ Bound_Upper and Lower is complete. After writing to this register, two complete frame times are required to implement the new settings. Writing to any of the above registers before the implementation is complete may put the chip into an undefined state requiring a reset. The “Busy” bit in the Extended_Config register may be used in lieu of a timer to determine when it is safe to write. See the Extended_Config register for more details. The following table lists some Frame_Period values for popular frame rates (clock rate = 24MHz). In addition, the three bound registers must also follow this rule when set to non-default values: Frame_Period_Max_Bound ≥ Frame_Period_Min_Bound + Shutter_Max_Bound.

Frame_Period_Min_Bound_Lower Address: 0x1B Access: Read/Write Reset Value: 0xAC (before SROM download) 0x7E (after SROM download) Bit 7 6 5 4 3 2 1 0 Field FBm 7 FBm6 FBm5 FBm4 FBm3 FBm2 FBm1 FBm0 Frame_Period_Min_Bound_Upper Address: 0x1C Access: Read/Write Reset Value: 0x0D (before SROM download) 0x0E (after SROM download) B i t 7654321 0 Field FBm 15 FBm14 FBm13 FBm12 FBm11 FBm10 FBm9 FBm8 Data Type: 16-bit unsigned integer. USAGE: This value sets the minimum frame period (the MAXIMUM frame rate) that may be selected by the automatic frame rate control. Units are clock cycles. The formula is Frame Rate = Clock Rate / Register value To read from the registers, read Upper first followed by Lower. To write to the registers, write Lower first, followed by Upper, then execute a write to the Frame_Period_Max_Bound_Upper and Lower registers. The minimum allowed write value is 0x7E0E; the maximum is 0xFFFF. Reading this register will return the most recent value that was written to it. However, the value will take effect only after a write to the Frame_Period_Max_Bound_Upper and Lower registers. After writing to Frame_Period_Max_ Bound_Upper, wait at least two frame times before writing to Frame_Period_Min_Bound_Upper or Lower again. The “Busy” bit in the Extended_Config register may be used in lieu of a timer to determine when it is safe to write. See the Extended_Config register for more details. In addition, the three bound registers must also follow this rule when set to non-default values: Frame_Period_Max_Bound ≥ Frame_Period_Min_Bound + Shutter_Max_Bound.

Shutter_Max_Bound_Lower Address: 0x1D Access: Read/Write Reset Value: 0x8C (before SROM download) 0x00 (after SROM download) Bit 7 6 5 4 3 2 1 0 Field SB 7 SB6 SB5 SB4 SB3 SB2 SB1 SB0 Shutter_Max_Bound_Upper Address: 0x1E Access: Read/Write Reset Value: 0x20 B i t 76543 2 10 Field SB 15 SB14 SB13 SB12 SB11 SB10 SB9 SB8 Data Type: 16-bit unsigned integer. USAGE: This value sets the maximum allowable shutter v alue when operating in automatic mode. Units are clock cycles. Since the automatic frame rate function is based on shutter value, the value in these registers can limit the range of the frame rate control. To read from the registers, read Upper first followed by Lower. To write to the registers, write Lower first, followed by Upper, then execute a write to the Frame_Period_Max_Bound_Upper and Lower registers. To set the shutter manually, disable the AGC via the Extended_Config register and write the desired value to these registers. Reading this register will return the most recent value that was written to it. However, the value will take effect only after a write to the Frame_Period_Max_Bound_Upper and Lower registers. After writing to Frame_Period_Max_Bound_ Upper, wait at least two frame times before writing to Shutter_Max_Bound_Upper or Lower again. The “Busy” bit in the Extended_Config register may be used in lieu of a timer to determine when it is safe to write. See the Extended_Config register for more details. In addition, the three bound registers must also follow this rule when set to non-default values: Frame_Period_Max_Bound ≥ Frame_Period_Min_Bound + Shutter_Max_Bound. SROM_ID Address: 0x1F Access: Read Reset Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field SR 7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 Data Type:8-Bit unsigned integer. USAGE: Contains the revision of the downloaded Shadow ROM firmware. If the firmware has been successfully down- loaded and the chip is operating out of SROM, this register will contain the SROM firmware revision, otherwise it will contain 0x00. Note: The IC hardware revision is available by reading the Revision_ID register (register 0x01). Reserved Address: 0x20 – 0x3C

Observation Address: 0x3D Access: Read/Write Reset Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field OB 7 Reserved OB 5 Reserved Reserved Reserved OB 1 OB0 Data Type: Bit field USAGE: Each bit is set by some process or action at regular intervals, or when the event occurs. The user must clear the register by writing 0x00, wait an appropriate delay, and read the register. The active processes will have set their cor- responding bit(s). This register may be used as part of a recovery scheme to detect a problem caused by EFT/B or ESD. Field Name Description OB7 0 = chip is not running SROM code 1 = chip is running SROM code Reserved Reserved OB5 NPD pulse was detected Reserved Reserved Reserved Reserved Reserved Reserved OB1 Set once per frame OB0 Set once per frame Reserved Address: 0x3E Inverse_Product_ID Address: 0x3F Access: Read Reset Value: 0xF8 Bit 7 6 5 4 3 2 1 0 Field NPID 7 NPID6 NPID5 NPID4 NPID3 NPID2 NPID1 NPID0 Data Type: Inverse 8-Bit unsigned integer USAGE: This value is the inverse of the Product_ID, located at the inverse address. It can be used to test the SPI port. Pixel_Burst Address: 0x40 Access: Read Reset Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field PB 7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Data Type: Eight bit unsigned integer USAGE: The Pixel_Burst register is used for high-speed access to all the pixel values from one and 2/3 complete frame. See the Synchronous Serial Port section for use details.

For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2010 Avago Technologies. All rights reserved. Obsoletes 5989-3422EN AV02-2469EN - August 24, 2010 Motion_Burst Address: 0x50 Access: Read Reset Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field MB 7 MB6 MB5 MB4 MB3 MB2 MB1 MB0 Data Type: Various, depending on data USAGE: The Motion_Burst register is used for high-speed access to the Motion, Delta_X, and Delta_Y, SQUAL, Shutter_ Upper, and Shutter_Lower and Maximum_Pixel registers. See the Synchronous Serial Port section for use details. SROM_Load Address: 0x 60 Access: Write Rset Value: N/A Data Type: Eight bit unsigned integer USAGE: The SROM_Load register is used for high-speed programming of the ADNS-3090 from an external SROM or microcontroller. See the Synchronous Serial Port section for use details.