ADNS-2051 AVAGO | Alldatasheet
Document overview
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- PDF pages: 40
Technical content
Features
- Precise optical navigation technology
- No mechanical moving parts
- Complete 2D motion sensor
- Serial interface and/or quadrature interface
- Smooth surface navigation
- Programmable frame speed up to 2300 frames per sec (fps)
- Accurate motion up to 14 ips
- 800 cpi resolution
- High reliability
- High speed motion detector
- No precision optical alignment
- Wave solderable
- Single 5.0 volt power supply
- Shutdown pin for USB suspend mode operation
- Power conservation mode during times of no movement
- On chip LED drive with regulated current
- Serial port registers – Programming – Data transfer
- 16-pin staggered dual inline package (DIP)
Applications
- Mice for desktop PCs, workstations, and portable PCs
- Trackballs
- Integrated input devices ADNS-2051 Optical Mouse Sensor Data Sheet
1 SCLK Serial port clock (input)
2 XA XA quadrature output
3 XB XB quadrature output
4 YB YB quadrature output
5 YA YA quadrature output
6 XY_LED LED control
7 REFA Internal reference
8 REFB Internal reference
9 OSC_IN Oscillator input
10 GND System ground
11 OSC_OUT Oscillator output
12 GND System ground
14 R_BIN LED current bin resistor
15 PD Power down pin, active high
16 SDIO Serial data (input and output)
Figure 1. Top view
Figure 2. Package outline drawing
0.50 CHAMFER
- DIMENSIONS IN MILLIMETERS (INCHES).
- DIMENSIONAL TOLERANCE: ± 0.1 mm.
- COPLANARITY OF LEADS: 0.1 mm.
- LEAD PITCH TOLERANCE: ± 0.15 mm.
- CUMULATIVE PITCH TOLERANCE: ± 0.15 mm.
- ANGULAR TOLERANCE: ± 3.0 DEGREES.
- CHAMFER (25 DEGREES x 2) ON THE TAPER SIDE OF THE LEAD.
- * THESE DIMENSIONS ARE FOR REFERENCES ONLY AND SHOULD NOT BE USED TO MECHANICALLY REFERENCE THE SENSOR.
Figure 5. Exploded view drawing
- Insert the sensor and all other electrical components
- Bend the LED leads 90° and then insert the LED into
- Insert the LED/clip assembly into PCB.
- Wave Solder the entire assembly in a no-wash solder
remove the kapton tape during wave soldering).
- Place the lens onto the base plate.
- Remove the protective kapton tape from optical
held vertically during the kapton removal process.
- Insert PCB assembly over the lens onto the base plate
aperture ring should self-align to the lens.
- The optical position reference for the PCB is set by the
- Install mouse top case. There MUST be a feature in the
ponents are interlocked to the correct vertical height.
Figure 6. Block diagram of ADNS-2051 optical mouse sensor Figure 7. PCB assembly
5 VOLT
IGES file and HDNS-2100 lens flange. the lens should NOT be used.
Figure 8. Application using SDIO pins
18 MHz
- Passes FCC B and worldwide analogous emission limits when assembled into a mouse with unshielded cable and following Avago recommendations.
- Passes EN61000-4-4/IEC801-4 EFT tests when assembled into a mouse with unshielded cable and following Avago recommendations.
- UL flammability level UL94 V-0.
- Provides sufficient ESD creepage/clearance distance to avoid discharge up to 15 kV when assembled into a mouse according to usage instructions above.
- For eye safety consideration, please refer to the technical report available on the web site, http://www.Avago.com
- The 15.0 kΩ resistor is determined by the absolute maximum rating of 50 mA for the HLMP-ED80- XX000. The other resistor values for brighter bins will guarantee good signals with reduced power. Notes on Bypass Capacitors:
- Caps for pins 7, 8 and 12, 13 MUST have trace lengths LESS than 5 mm.
- The 0.1 µF caps must be ceramic.
- Caps should have less than 5 nH of self inductance
- Caps should have less than 0.2 Ω ESR Surface mount parts are recommended. SDIO and SCLK pins should be grounded if not used.
Figure 9. Application using quadrature output pins
9 CEXT
3.3 V REGULATOR
Electrical Characteristics over recommended operating conditions. Typical values at 25˚C, VDD = 5.0 V, 18 MHz. (power down) or VDD; VDD = 4.25 V to 5.25 V. Output Low Voltage VOL 0.4 V @ IOL = 0.5 mA. Output High Voltage VOH 0.6 * VDD V @ IOH = 0.5 mA . Output Low Voltage VOL 1.1 V Refer to Figure 11. XY LED Current ILED 500 µA R1 < 200 Ω. Figure 11. Typical I-V characteristic of ADNS-
2051 XY_LED pin
Figure 12. PD timing normal mode Figure 13. PD timing sleep mode Figure 14. PD minimum pulse width Figure 15. Detail of PD falling edge timing five quadrature states can exist within one frame time. will be increased by the length of the PD time.
75 FRAMES
Figure 16. Quadrature states per frame (400 cpi mode)
Figure 17. Quadrature states per frame (800 cp imode)
Figure 18. Quadrature states per frame (800 cpi mode)
Figure 35. Power up serial port watchdog timer sequence
- The ADNS-2051 and the micro-controller might get
case, the micro-controller should raise PD for 100 µs.
- The ADNS-2051 has a transaction timer for the serial port.
the current transaction, the serial port will reset. – Writing to an invalid address will have no effect.
- Collision detection on SDIO
controller can begin driving SDIO any time afterthat. cause any communication difficulties).
- In case of synchronization failure, both the ADNS-2051
- Termination of a transmission by the micro-control -
accomplish this the micro-controller should raise PD.
- The micro-controller can verify success of write opera-
and comparing written data to read data.
- The micro-controller can verify the synchronization of
; Notes: ; CY7C63001 20pin package ; ADNS-2051 ; SDIO line connected to pin5 (P1.0) ; PD connected to pin 16 (P1.1) ; SCLK line connected to pin15 (P1.3) ; I/O port Port1_Data: equ 01h ; GPIO data port 1 Port1_Interrupt: equ 05h ; Interrupt enable for port 1 Port1_Pullup: equ 09h ; Pullup resistor control for port 1 ; Port bit definitions SDIO: equ 01h ; bit 0 PD: equ 02h ; bit 1 SCLK: equ 08h ; bit 3 Pt1_Current: equ 00h ; port1 current setting ; GPIO Isink registers Port1_Isink: equ 38h Port1_Isink0: equ 38h Port1_Isink1: equ 39h Port1_Isink3: equ 3Bh ; data memory variables spi_addr: equ 40h ; address of spi writes spi_data: equ 41h ; data of spi writes bit_counter: equ 44h ; SPI bit counter port1_wrote: equ 45h ; what we wrote last ; initialize Port 1 mov A, Pt1_Current ; select DAC setting iowr Port1_Isink0 ; isink current Port 1 bit[0] iowr Port1_Isink1 ; isink current Port 1 bit[1] iowr Port1_Isink3 ; isink current Port 1 bit[3] mov A, 0h ; enable Port 1 bit [7:0] pullups iowr Port1_Pullup mov A, ~(PD|SDIO) ; turn on the ADNS-2051 mov [port1_wrote], A mov A, [port1_wrote] iowr Port1_Data ; PD low, SCLK, SDIO mov A, 0 iowr Port1_Interrupt ; disable port 1 interrupts ; There are possible problems with the SPI port if the microcontroller starts executing ; instructionsbefore the ADNS-2051 sensor has powered up. See page 18 for details. ; It is assumed that power to the microcontroller is OK if the next instructions can be executed. ; These instructions will reset the SPI port of the sensor. SPI communication code for the Cypress CY7C63000 or CY7C63001 (Please consult factory for the CY7C63722 or CY7C63723 codes.) Note: This programming sequence is not covered in Avago's product warranty. It is only a recommended example when using the mentioned Cypress microcontrollers. For the latest updates on Cypress microcontrollers, please contact Cypress at email: usbapps@cypress.com or call (858) 613-7929 (US). The following code can be used to implement the SPI data communications. See the schematic in Figure 9.
Resync_sensor: mov A,~(SCLK|SDIO|PD) ; set the SCLK, SDIO and PD lines low and [port1_wrote], A mov A, [port1_wrote] iowr Port1_Data ; If the power to the sensor needs more time ; to stabilize, insert a delay here call delay700us ; wait about 4 milliseconds for the sensor call delay700us ; oscillator to stabilize call delay700us call delay700us call delay700us call delay700us mov A, (SCLK|SDIO|PD ; set the SCLK, SDIO and PD lines high or [port1_wrote], A ; this shuts down the oscillator and mov A, [port1_wrote] ; resets the SPI port iowr Port1_Data call delay700us ; wait for the PD to reset the part mov A, ~PD ; set the PD line low to put the sensor and [port1_wrote], A ; back into normal operation mov A, [port1_wrote] iowr Port1_Data call delay700us ; wait about 4 milliseconds for the sensor call delay700us ; oscillator to stabilize call delay700us call delay700us call delay700us call delay700us ; sensor SPI port now in sync ; ReadSPI routine ; Includes delays for long traces or cables between the uP and ADNS-2051 ; Has correct timing of SCLK and SDIO ; On entry: spi_addr = Address of SPI register in the ADNS-2051 ; spi_data = undefined ; On exit spi_addr = undefined ; spi_data = register contents from ADNS-2051 ReadSPI: mov A, 64 ; wait 200us (optional) mov [bit_counter], A ; (about 3us per loop) Waitrspi: nop nop nop nop nop nop dec [bit_counter] jnz Waitrspi ; read address mov A,~80h and [spi_addr], A ; lower MSB of address (read) call writeaddr ; wait 200us (about 3us per loop)(100us minimum required) mov A,64 ; wait for data to be ready mov [bit_counter], A Waitrspi2: nop nop nop nop nop nop dec [bit_counter] jnz Waitrspi2 mov A, 0h ; clear the data
mov [spi_data], A mov A, 08h mov [bit_counter], A mov A, SDIO or [port1_wrote], A mov A, [port1_wrote] ; write a 1 to SDIO iowr Port1_Data nextr: mov A, ~SCLK ; lower SCLK and [port1_wrote], A mov A, [port1_wrote] iowr Port1_Data nop ; wait for cable to settle nop ; if ADNS-2051 is connected to nop ; IC via short PCB traces, nop ; then the number of NOPs can nop ; reduced or eliminated nop nop mov A,[spi_data] ; shift next bit asl mov [spi_data], A ; shift next bit iord Port1_Data ; read SDIO and A, SDIO jz rdx rd1: mov A, 01h or [spi_data], A rdx: mov A, SCLK ; raise SCLK or [port1_wrote], A mov A, [port1_wrote] iowr Port1_Data nop ; wait for cable to settle nop nop nop nop nop nop dec [bit_counter] jnz nextr ret ; WriteSPI routine ; Includes delays for long traces or cables between the uP and ADNS-2051. ; Has correct timing of SCLK and SDIO ; On entry: spi_addr = Address of SPI register in the ADNS-2051 ; spi_data = Data to be written to the SPI register ; On exit spi_addr = undefined ; spi_data = undefined WriteSPI: mov A, 64 ; wait 200us (optional) mov [bit_counter], A ; about 3us per loop Waitspi: nop nop nop nop nop nop dec [bit_counter] jnz Waitspi ; write address
mov A, 80h or [spi_addr], A ; set MSB of address (write) call writeaddr jmp wrdata writeaddr: mov A, 08h ; 8 bits to shift out mov [bit_counter], A nexta: mov A, ~SCLK ; lower SCLK and [port1_wrote], A mov A, [port1_wrote] iowr Port1_Data mov A, [spi_addr] ; shift next bit asl mov [spi_addr], A jnc addr0 addr1: mov A, SDIO or [port1_wrote], A ; raise SDIO jmp addrx addr0: mov A, ~SDIO and [port1_wrote], A ; lower SDIO addrx: mov A, [port1_wrote] iowr Port1_Data nop ; wait for cable to settle nop nop nop nop nop nop mov A, SCLK ; raise SCLK or [port1_wrote], A mov A, [port1_wrote] iowr Port1_Data ; ADNS-2051 reads the address bit nop ; wait for cable to settle nop nop nop nop nop nop dec [bit_counter] jnz nexta ret wrdata: mov A, 08h ; 8 bits of data mov [bit_counter], A nextw: mov A, ~SCLK ; lower SCLK and [port1_wrote], A mov A, [port1_wrote] iowr Port1_Data mov A, [spi_data] ; shift next bit asl mov [spi_data], A jnc wr0 wr1: mov A, SDIO or [port1_wrote], A ; raise SDIO jmp wrx wr0: mov A, ~SDIO and [port1_wrote], A ; lower SDIO wrx: mov A, [port1_wrote] iowr Port1_Data nop ; wait for cable to settle nop nop nop nop nop nop
mov A, SCLK ; raise SCLK or [port1_wrote], A mov A, [port1_wrote] iowr Port1_Data ; ADNS-2051 reads the data bit nop ; wait for cable to settle nop nop nop nop nop nop dec [bit_counter] jnz nextw ret delay700us: mov A, ffh ; wait for 710us mov [bit_counter], A ; reuse bit_counter waitd0: nop nop nop nop nop nop ; 2us dec [bit_counter] jnz waitd0 ret Example calling syntax ; WriteSPI ; Set register 0a to 40h, LED blink mode mov A, 0ah ; move address into A mov [spi_addr], A ; move address into spi_addr mov A, 40h ; move data into A mov [spi_data], A ; move data into spi_data call WriteSPI ; call WriteSPI routine, on return, ; spi_addr and spi_data will be undefined ; ReadSPI ; Read register 02h, the motion register mov A, 02h ; move address into A mov [spi_addr], A ; move address into spi_addr call ReadSPI ; call ReadSPI, on return, data is in spi_data, ; spi_addr is undefined
The ADNS-2051 can be programmed through registers, via the serial port, and configuration and motion data can be read from these registers. Address Register 0x00 Product_ID 0x01 Revision_ID 0x02 Motion 0x03 Delta_X 0x04 Delta_Y 0x05 SQUAL Address Register 0x06 Average_Pixel 0x07 Maximum_Pixel 0x08 Reserved 0x09 Reserved 0x0a Configuration_bits 0x0b Reserved Address Register 0x0c Data_Out_Lower 0x0d Data_Out_Upper 0x0e Shutter_Lower 0x0f Shutter_Upper 0x10 Frame_Period_Lower 0x11 Frame_Period_Upper Bit 7 6 5 4 3 2 1 0 Field PID7 PID6 PID5 PID4 PID3 PID2 PID1 PID0 Data Type: Eight bit number with the product identifier. USAGE: The value in this register does not change, it can be used to verify that the serial communications link is OK. Product_ID Address: 0x00 Access: Read Reset Value: 0x02 Bit 7 6 5 4 3 2 1 0 Field RID7 RID6 RID5 RID4 RID3 RID2 RID1 RID0 Data Type: Eight bit number with current revision of the IC. USAGE: NN is a value between 00 and FF which represent the current design revision of the device. Revision_ID Address: 0x01 Access: Read Reset Value: 0xNN Bit 7 6 5 4 3 2 1 0 Field MOT Reserved FAULT OVFY OVFX Reserved Reserved RES Data Type: Bit field USAGE: Register 0x02 allows the user to determine if motion has occurred since the last time it was read. If so, then the user should read registers 0x03 and 0x04 to get the accumulated motion. It also tells if the motion buffers have overflowed and whether or not an LED fault occurred since the last reading. The current resolution is also shown. Motion Address: 0x02 Access: Read Reset Value: 0x00
MOT Motion since last report or PD 0 = No motion 1 = Motion occurred, data ready for reading in Delta_X and Delta_Y registers Reserved Reserved for future FAULT LED Fault detected – set when R_BIN is too low or too high, shorts to VDD or Ground 0 = No fault 1 = Fault detected OVFY Motion overflow Y, ΔY buffer has overflowed since last report 0 = No overflow 1 = Overflow has occurred OVFX Motion overflow X, ΔX buffer has overflowed since last report 0 = No overflow 1 = Overflow has occurred Reserved Reserved for future Reserved Reserved for future RES Resolution in counts per inch 0 = 400 1 = 800 Notes for Motion: 1. Reading this register freezes the Delta_X and Delta_Y register values. Read this register before reading the Delta_X and Delta_Y registers. If Delta_X and Delta_Y are not read before the motion register is read a second time, the data in Delta_X and Delta_Y will be lost. 2. Avago RECOMMENDS that registers 0x02, 0x03 and 0x04 be read sequentially. 3. Internal buffers can accumulate more than eight bits of motion for X or Y. If either one of the internal buffers overflows, then absolute path data is lost, and the OVFX or OVFY bit is set. These bits (OVFX and OVFY) are cleared once some motion has been read from the Delta_X and Delta_Y registers, and if the buffers are not at full scale. Since more data is present in the buffers, the cycle of reading the Motion, Delta_X and Delta_Y registers should be repeated until the motion bit (MOT) is cleared. Until MOT is cleared, either the Delta_X or Delta_Y registers will read either positive or negative full scale. If the motion register has not been read for a long time, at 400 cpi it may take up to 16 read cycles to clear the buffers, at 800 cpi, up to 32 cycles. 4. FAULT is a sticky bit that is cleared by reading the Motion register. It signifies that an LED fault has occurred since the last time the motion register was read. Once an LED fault has cleared, the hardware will drive the LED normally. 80 81 FE FF 00 01 02 7E 7F -128 -127 -2 -1 0 + 1 + 2 +126 +127MOTION DELTA_X ADNS-2051 Delta X Bit 7 6 5 4 3 2 1 0 Field X7 X6 X5 X4 X3 X2 X1 X0 Data Type: Eight bit 2‘s complement number. USAGE: X movement is counts since last report. Absolute value is determined by resolution. Reading clears the register. Delta_X Address: 0x03 Access: Read Reset Value: 0x00
squal count is dependent on focus distance. This graph is obtained by getting multiple readings over different heights. Figure 38. Typical mean squal vs. Z (white paper) Data Type: Eight bit 2‘s complement number. resolution. Reading clears the register. Data Type: Eight bit number. no surface below the sensor.
Reserved Address: 0x08 Reserved Address: 0x09 0 25 50 75 100 125 150 175 200 225 250 AVERAGE PIXEL VALUE AVERAGE PIXEL (WHITE PAPER) ADNS-2051 Average Pixel 0 25 50 75 100 125 150 175 200 225 250 MAXIMUM PIXEL VALUE MAXIMUM PIXEL (WHITE PAPER) ADNS-2051 Max. Pixel Bit 7 6 5 4 3 2 1 0 Field 0 0 AP5 AP4 AP3 AP2 AP1 AP0 Data Type: Six bit number. USAGE: Average Pixel value in current frame. Minimum value = 0, maximum = 63. The average pixel value can be adjusted every frame. Shown below is a graph of 250 sequentially acquired average pixel values, while the sensor was moved slowly over white paper. Average_Pixel Address: 0x06 Access: Read Reset Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field 0 0 MP5 MP4 MP3 MP2 MP1 MP0 Data Type: Six bit number. USAGE: Maximum Pixel value in current frame. Minimum value = 0, maximum value = 63. The maximum pixel value can be adjusted every frame. Shown below is a graph of 250 sequentially acquired maximum pixel values, while the sen- sor was moved slowly over white paper. Maximum_Pixel Address: 0x07 Access: Read Reset Value: 0x00
RESET Power up defaults (bit always reads 0) 0 = No effect 1 = Reset registers and bits to power up default settings (bold entries) LED_MODE LED Shutter Mode 0 = Shutter mode off (LED always on) (even if no motion up to 1 sec.) 1 = Shutter mode on (LED only on when the electronic shutter is open) Sys Test System Tests (bit always reads 0) 0 = No tests 1 = perform all system tests, output 16 bit CRC via Data_Out_Upper and Data_Out_Lower registers. Note: Since part of the system test is a RAM test, the RAM will be overwritten with the default values when the test is done. If any configuration changes from the default are needed for operation, make the changes AFTER the system test is run. This operation requires substantially more time to complete than other register transactions. RES Resolution in counts per inch 0 = 400 1 = 800 Pix Dump Dump the pixel array through Data_Out_Upper and Data_Out_Lower, 256 bytes 0 = disabled 1 = dump pixel array Reserved Reserved Reserved Reserved Sleep Sleep Mode 0 = Normal, fall asleep after one second of no movement (1500 frames/s) 1 = Always awake Reserved Address: 0x0b Bit 7 6 5 4 3 2 1 0 Field RESET LED_MODE Sys Test RES PixDump Reserved Reserved Sleep Data Type: Bit field USAGE: Register 0x0a allows the user to change the configuration of the sensor. Shown below are the bits, their default values, and optional values. Configuration_bits Address: 0x0a Access: Read/Write Reset Value: 0x00
Data_Out_Upper Data_Out_Lower Note System test result 1: FE D4 One of two results returned. These System test result 2: 4D 10 values are subject to change with each device design revision. Pixel Dump command Pixel Address Pixel Data (Lower 6 bits) Once the pixel dump command is given, the sensor writes the address and the value for the first pixel into the Data_Out_Upper and Data_Out_Lower registers. The MSB of Data_Out_Lower is the status bit for the data. If the bit is high, the data are NOT valid. Once the MSB is low, the data for that particular read are valid and should be saved. The pixel address and data will then be incremented on the next frame. Once the pixel dump is complete, the PixDump bit in register 0x0a should be set to zero. To obtain an accurate image, the LED needs to be turned on by changing the sleep mode of the configuration register 0x0a to always awake. Bit 7 6 5 4 3 2 1 0 Field DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Data_Out_Lower Address: 0x0c Access: Read Reset Value: undefined Bit 7 6 5 4 3 2 1 0 Field DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 Data Type: Sixteen bit word. USAGE: Data can be written to these registers from the system self test, or the pixel dump command. The data can be read out 0x0d, or 0x0d first, then 0x0c. Data_Out_Upper Address: 0x0d Access: Read Reset Value: undefined
Figure 39. Directions are for a complete mouse, with the HDNS-2100 lens
black, to 63 for complete white. An internal AGC circuit adjusts the shutter value to keep the brightest feature (max. Figure 40. Pixel dump pictures
is dependent on focus distance. Data Type: Sixteen bit word. acquired shutter values, while the sensor was moved slowly over white paper. Figure 41. Typical shutter vs. Z (white paper)
← Default Max. Shutter Max Shutter Shutter Frames/second Decimal Hex Upper Lower 2300 5010 0x1392 13 92 2000 6184 0x1828 18 28 1500 9184 0x23E0 23 E0 1000 15184 0x3B50 3B 50 500 33184 0x81A0 81 A0 *Note: To optimize tracking performance on dark surfaces, it is recommended that an adaptive frame rate based on shutter value be implemented, for frame rates greater than 1500. Changing the frame rate results in changes in the maximum speed, acceleration limits, and dark surface performance. To read from the registers, read Frame_Period_Upper first followed by Frame_Period_Lower. To write to the registers, write Frame_Period_Lower first followed by Frame_Period_Upper. The maximum value of the shutter is dependent upon the frame rate and clock frequency. The formula for the maximum shutter value is: Clock Frequency Frame RateMax. Shutter Value = –2816 For a clock frequency of 18 MHz, the following table shows the maximum shutter value. 1 clock cycle is 55.56 nsec. ← Default Frame Time Counts Frame_Period Frames/second Decimal Hex 2‘s Comp Upper Lower 2300* 7826 0x1E92 0xE16E E1 6E 2000* 9000 0x2328 0xDCD8 DC D8 1500 12000 0x2EE0 0xD120 D1 20 1000 18000 0x4650 0xB9B0 B9 B0 500 36000 0x8CA0 0x7360 73 60 ← Minimum Frame Time Bit 7 6 5 4 3 2 1 0 Field FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0 Frame_Period_Lower Address: 0x10 Access: Read/Write Reset Value: 0x20 Bit 7 6 5 4 3 2 1 0 Field FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8 Data Type: Sixteen bit 2‘s complement word. USAGE: The frame period counter counts up until it overflows. Units are clock cycles. The formula is: = Counts (decimal) Counts (hex) Counts (2‘s complement hex) For an 18 MHz clock, here are the Frame_Period values for popular frame rates. Frame_Period_Upper Address: 0x11 Access: Read/Write Reset Value: 0xd1 ←←Clock Rate Frame Rate
IC Register State after Reset (power up or setting bit 7, register 0x0a) Address Register Value Meaning 0x0 Product_ID 0x02 Product ID = 2 (Fixed value) 0x01 Revision_ID 0xNN Revision of IC (Fixed value). (For each device design revision.) 0x02 Motion 0x00 No Motion LED = No Fault No X data overflow No Y data overflow Resolution is 400 counts per inch 0x03 Delta_X 0x00 No X motion 0x04 Delta_Y 0x00 No Y motion 0x05 SQUAL 0x00 No image yet to measure 0x06 Average_Pixel 0x00 No image yet to measure 0x07 Maximum_Pixel 0x00 No image yet to measure 0x08 Reserved — 0x09 Reserved — 0x0a Configuration_bits 0x00 Part is not Reset LED Shutter Mode is off No System tests Resolution = 400 counts per inch Pixel Dump is disabled Sleep mode is enabled 0x0b Reserved — 0x0c Data_Out_Lower undefined No data to read 0x0d Data_Out_Upper undefined No data to read 0x0e Shutter_Lower 0x64 Initial shutter value 0x0f Shutter_Upper 0x00 Initial shutter value 0x10 Frame_Period_Lower 0x20 Initial frame period value (corresponds to 1500 fps) 0x11 Frame_Period_Upper 0xd1 Initial frame period value (corresponds to 1500 fps)
Optical Mouse Design References Eye Safety calculation AN1228
Ordering Information
Specify part number as follows: ADNS-2051 = Sensor IC in a 16-pin staggered DIP , 20 per tube. HDNS-2100 = Round Optical Mouse Lens HDNS-2100#001 = Trimmed Optical Mouse Lens HDNS-2200 = LED Assembly Clip (Black) HDNS-2200#001 = LED Assembly Clip (Clear) HLMP-ED80-XX000 = LED For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2008 Avago Technologies. All rights reserved. Obsoletes 5988-8477EN AV02-1364EN - September 3, 2008