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Technical content
Features
- 80C48 and 80C80/85 Bus Compatible - No Interfacing Logic Required
- Easy Interface to Most Microprocessors
- Will Operate in a “Stand Alone” Mode
- Differential Analog Voltage Inputs
- Works with Bandgap Voltage References
- TTL Compatible Inputs and Outputs
- On-Chip Clock Generator
- Analog Voltage Input Range
- No Zero-Adjust Required
- 80C48 and 80C80/85 Bus Compatible - No Interfacing Logic Required Pinout ADC0803, ADC0804 (PDIP) TOP VIEW WR RD CS DB6 DB7 INTR DB3 DB4 DB5 DB0 DB1 DB2 CLK IN CLK R VIN (-) VIN (+) DGND VREF/2 AGND ANY PROCESSOR 8-BIT RESOLUTION OVER ANY DESIRED ANALOG INPUT VOLTAGE RANGE DIFF INPUTS 10K 150pF VREF/2 P BUS +5V WR RD CS CLK IN INTR VIN (-) VIN (+) DGND VREF/2 AGND V+ OR VREF CLK R DB0 (LSB) DB1 DB2 DB3 DB4 DB5 DB6 DB7 (MSB)
Ordering Information
PART NUMBER ERROR EXTERNAL C ONDITIONS TEMP. RANGE ( oC) PACKAGE PKG. NO ADC0803LCN 1/2 LSB V REF/2 Adjusted for Correct Full Scale Reading 0 to 70 20 Ld PDIP E20.3 ADC0804LCN 1 LSB V REF/2 = 2.500VDC (No Adjustments) 0 to 70 20 Ld PDIP E20.3
ADC0803, ADC0804 FN3094 Rev 4.00 Page 2 of 17 August 2002 Functional Diagram 1211 15 1413 18 1716 WR RD CS INTR CLK OSC CLK R VIN (-) VIN (+) DGND VREF/2 AGND (VREF) DAC VOUT COMP CLK GEN CLKS CLK A RESET START F/F LADDER AND DECODER SUCCESSIVE APPROX. REGISTER AND LATCH 8-BIT SHIFT REGISTER D RESET SET CONV. COMPL. THREE-STATE OUTPUT LATCHES DIGITAL OUTPUTS THREE-STATE CONTROL “1” = OUTPUT ENABLE DFF2 CLK A XFER G2 Q
8 X 1/f
R Q INTR F/F IF RESET = “0” D DFF1 Q D Q CLK B START CONVERSION MSB LSB Q “1” = RESET SHIFT REGISTER “0” = BUSY AND RESET STATE RESET READ SET3 CLK IN MSB CLK LSB INPUT PROTECTION FOR ALL LOGIC INPUTS INPUT TO INTERNAL BV = 30V CIRCUITS
ADC0803, ADC0804 FN3094 Rev 4.00 Page 3 of 17 August 2002 Absolute Maximum Ratings Thermal Information Operating Conditions Thermal Resistance (Typical, Note 1) JA (oC/W) Maximum Junction Temperature CAUTION: Stresses above those listed in “Abs olute Maximum Ratings” may cause permanent dam age to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications (Notes 2, 8) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS CONVERTER SPECIFICATIONS V+ = 5V, TA = 25oC and fCLK = 640kHz, Unless Otherwise Specified Total Unadjusted Error ADC0803 V REF/2 Adjusted for Correct Full Scale Reading - - 1/2 LSB ADC0804 V REF/2 = 2.500V - - 1L S B VREF/2 Input Resistance Input Resistance at Pin 9 1.0 1.3 - k Analog Input Voltage Range (Note 3) GND-0.05 - (V+) + 0.05 V DC Common-Mode Rejection Over Analog Input Voltage Range - 1/16 1/8 LSB Power Supply Sensitivity V+ = 5V 10% Over Allowed Input Voltage Range - 1/16 1/8 LSB CONVERTER SPECIFICATIONS V+ = 5V, 0oC to 70oC and fCLK = 640kHz, Unless Otherwise Specified Total Unadjusted Error ADC0803 V REF/2 Adjusted for Correct Full Scale Reading - - 1/2 LSB ADC0804 V REF/2 = 2.500V - - 1L S B VREF/2 Input Resistance Input Resistance at Pin 9 1.0 1.3 - k Analog Input Voltage Range (Note 3) GND-0.05 - (V+) + 0.05 V DC Common-Mode Rejection Over Analog Input Voltage Range - 1/8 1/4 LSB Power Supply Sensitivity V+ = 5V 10% Over Allowed Input Voltage Range - 1/16 1/8 LSB AC TIMING SPECIFICATIONS V+ = 5V, and TA 25oC, Unless Otherwise Specified Clock Frequency, fCLK V+ = 6V (Note 4) 100 640 1280 kHz V+ = 5V 100 640 800 kHz Clock Periods per Conversion (Note 5), tCONV 62 - 73 Clocks/Conv Conversion Rate In Free-Running Mode, CR INTR tied to WR with CS = 0V, fCLK = 640kHz - - 8888 Conv/s Width of WR Input (Start Pulse Width), tW(WR)I CS = 0V (Note 6) 100 - - ns Access Time (Delay from Falling Edge of RD to Output Data Valid), tACC CL = 100pF (Use Bus Driver IC for Larger CL) - 135 200 ns Three-State Control (Delay from Rising Edge of RD to Hl-Z State), t1H, t0H CL = 10pF, RL= 10K (See Three-State Test Circuits) - 125 250 ns Delay from Falling Edge of WR to Reset of INTR, tWI, tRI - 300 450 ns Input Capacitance of Logic Control Inputs, CIN -5-p F Three-State Output Capacitance (Data Buffers), COUT -5-p F
ADC0803, ADC0804 FN3094 Rev 4.00 Page 4 of 17 August 2002 DC DIGITAL LEVELS AND DC SPECIFICATIONS V+ = 5V, and TMIN to TMAX, Unless Otherwise Specified CONTROL INPUTS (Note 7) Logic “1“ Input Voltage (Except Pin 4 CLK IN), VINH Logic “0“ Input Voltage (Except Pin 4 CLK IN), VINL CLK IN (Pin 4) Positive Going Threshold Voltage, V+CLK 2.7 3.1 3.5 V CLK IN (Pin 4) Negative Going Threshold Voltage, V-CLK 1.5 1.8 2.1 V CLK IN (Pin 4) Hysteresis, VH 0.6 1.3 2.0 V Logic “1” Input Current (All Inputs), IINHI VlN = 5V - 0.005 1 Logic “0” Input Current (All Inputs), IINLO VlN = 0V -1 -0.005 - A Supply Current (Includes Ladder Current), I+ fCLK = 640kHz, TA = 25oC and CS = Hl - 1.3 2.5 mA DATA OUTPUTS AND INTR Logic “0” Output Voltage, VOL lO = 1.6mA, V+ = 4.75V - - 0.4 V Logic “1” Output Voltage, VOH lO = -360A, V+ = 4.75V 2.4 - - V Three-State Disabled Output Leakage (All Data Buffers), ILO VOUT = 0V -3 - - A VOUT = 5V - - 3 A Output Short Circuit Current, ISOURCE VOUT Short to GND, TA = 25oC4 . 5 6 - m A Output Short Circuit Current, ISINK VOUT Short to V+, TA = 25oC9 . 0 1 6 - m A NOTES: 2. All voltages are measured with respect to GND, unless otherwise specified. The separate AGND point should always be wired to the DGND, being careful to avoid ground loops. 3. For V IN(-) VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the V+ supply. Be careful, during testing at low V+ levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct - especially at elevated temperatures, and cause errors for analog inputs near full scale. As long as the analog VIN does not exceed the supply voltage by more than 50mV, the output code will be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950V over temperature variations, initial tolerance and loading. 4. With V+ = 6V, the digital logic in terfaces are no longer TTL compatible. 5. With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. 6. The CS input is assumed to bracket the WR strobe input so that timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see Timing Diagrams). 7. CLK IN (pin 4) is the input of a Schmitt tr igger circuit and is therefore specified separately. 8. None of these A/Ds requires a zero-adjust. However, if an all zero code is desired for an analog input other than 0V, or if a narrow full scale span exists (for example: 0.5V to 4V full scale) the VIN(-) input can be adjusted to achieve this. See the Zero Error description in this data sheet. Electrical Specifications (Notes 2, 8) (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Timing Waveforms FIGURE 1A. t1H FIGURE 1B. t1H, CL = 10pF 10K RD CS CL DATA OUTPUT RD 2.4V tr 90% 50% 10% t1H 0.8V DATA OUTPUTS GND tr = 20ns VOH 90%
FIGURE 6. FULL SCALE ERROR vs fCLK FIGURE 7. EFFECT OF UNADJUSTED OFFSET ERROR FIGURE 8. OUTPUT CURRENT vs TEMPERATURE FIGURE 9. POWER SUPPLY CUR RENT vs TEMPERATURE
1 TO 8 x 1/fCLK INTERNAL TC
ADC0803, ADC0804 FN3094 Rev 4.00 Page 8 of 17 August 2002 Understanding A/D Error Specs A perfect A/D transfer characteristic (staircase wave-form) is shown in Figure 11A. The horizontal scale is analog input voltage and the particular points labeled are in steps of 1 LSB (19.53mV with 2.5V tied to the V REF/2 pin). The digital output codes which correspond to these inputs are shown as D-1, D, and D+1. For the perfect A/D, not only will center-value (A - 1, A, A + 1, . . .) analog inputs produce the correct output digital codes, but also each riser (the transitions between adjacent output codes) will be located 1/2 LSB away from each center- value. As shown, the risers are ideal and have no width. Correct digital output codes will be provided for a range of analog input voltages which extend 1/2 LSB from the ideal center-values. Each tread (the range of analog input voltage which provides the same digital output code) is therefore 1 LSB wide. The error curve of Figure 11B shows the worst case transfer function for the ADC080X. Here the specification guarantees that if we apply an analog input equal to the LSB analog voltage center-value, the A/D will produce the correct digital code. Next to each transfer function is shown the corresponding error plot. Notice that the error includes the quantization uncertainty of the A/D. For example, the error at point 1 of Figure 11A is 1/2 LSB because the digital code appeared 1/2 LSB in advance of the center-value of the tread. The error plots always have a constant negative slope and the abrupt upside steps are always 1 LSB in magnitude, unless the device has missing codes. Detailed Description The functional diagram of the ADC080X series of A/D converters operates on the successive approximation principle (see Application Notes AN016 and AN020 for a more detailed description of this principle). Analog switches are closed sequentially by successive-approximation logic until the analog differential input voltage [V lN(+) - VlN(-)] matches a voltage derived from a tapped resistor string across the reference voltage. The most significant bit is tested first and after 8 comparisons (64 clock cycles), an 8-bit binary code (1111 1111 = full scale) is transferred to an output latch. The normal operation proceeds as follows. On the high-to-low transition of the WR input, the internal SAR latches and the shift- register stages are reset, and the INTR output will be set high. As long as the CS input and WR input remain low, the A/D will remain in a reset state. Conversion will start from 1 to 8 clock periods after at least one of these inputs makes a low-to-high transition. After the requisite number of clock pulses to complete the conversion, the INTR pin will make a high-to-low transition. This can be used to interrupt a processor, or otherwise signal the availability of a new conversion. A RD operation (with CS low) will clear the INTR line high again. The device may be operated in the free-running mode by connecting INTR to the WR input with CS = 0. To ensure start-up under all possible conditions, an external WR pulse is required during the first power-up cycle. A conversion-in-process can be interrupted by issuing a second start command. Digital Operation The converter is started by having CS and WR simultaneously low. This sets the start flip-flop (F/F) and the resulting “1” level resets the 8-bit shift register, resets the Interrupt (INTR) F/F and inputs a “1” to the D flip-flop, DFF1, which is at the input end of the 8-bit shift register. Internal clock signals then transfer this “1” to the Q output of DFF1. The AND gate, G1, combines this “1” output with a clock signal to provide a reset signal to the start F/F. If the set signal is no longer present (either WR or CS is a “1”), the start F/F is reset and the 8-bit shift register then can have the “1” clocked in, which starts the conversion process. If the set signal were to still be present, this reset pulse would have no effect (both outputs of the start F/F would be at a “1” level) and the 8-bit shift register would continue to be held in the reset mode. This allows for asynchronous or wide CS and WR signals. After the “1” is clocked through the 8-bit shift register (which completes the SAR operation) it appears as the input to DFF2. As soon as this “1” is output from the shift register, the AND gate, G2, causes the new digital word to transfer to the Three- State output latches. When DFF2 is subsequently clocked, the Q output makes a high-to-low transition which causes the INTR F/F to set. An inverting buffer then supplies the INTR output signal. When data is to be read, the combination of both CS and RD being low will cause the INTR F/F to be reset and the three- state output latches will be enabled to provide the 8-bit digital outputs. Digital Control Inputs The digital control inputs (CS, RD, and WR) meet standard TTL logic voltage levels. These signals are essentially equivalent to the standard A/D Start and Output Enable control signals, and are active low to allow an easy interface to microprocessor control busses. For non-microprocessor based applications, the CS input (pin 1) can be grounded and the standard A/D Start function obtained by an active low pulse at the WR input (pin 3). The Output Enable function is achieved by an active low pulse at the RD input (pin 2). Analog Operation The analog comparisons are performed by a capacitive charge summing circuit. Three capacitors (with precise ratioed values) share a common node with the input to an auto-zeroed comparator. The input capacitor is switched between VlN(+) and VlN(-), while two ratioed reference capacitors are switched between taps on the reference voltage divider string. The net charge corresponds to the weighted difference between the input and the current total value set by the successive approximation register. A correction is made to offset the comparison by 1/2 LSB (see Figure 11A).
ADC0803, ADC0804 FN3094 Rev 4.00 Page 9 of 17 August 2002 Analog Differential Voltage Inputs and Common- Mode Rejection This A/D gains considerable applications flexibility from the analog differential voltage input. The VlN(-) input (pin 7) can be used to automatically subtract a fixed voltage value from the input reading (tare correction). This is also useful in 4mA - 20mA current loop conversion. In addition, common-mode noise can be reduced by use of the differential input. The time interval between sampling V IN(+) and VlN(-) is 41/2 clock periods. The maximum error voltage due to this slight time difference between the input voltage samples is given by: where: E is the error voltage due to sampling delay, VPEAK is the peak value of the common-mode voltage, fCM is the common-mode frequency. For example, with a 60Hz common-mode frequency, fCM, and a 640kHz A/D clock, fCLK, keeping this error to 1/4 LSB (~5mV) would allow a common-mode voltage, VPEAK, given by: or The allowed range of analog input voltage usually places more severe restrictions on input common-mode voltage levels than this. An analog input voltage with a reduced span and a relatively large zero offset can be easily handled by making use of the differential input (see Reference Voltage Span Adjust). Analog Input Current The internal switching action causes displacement currents to flow at the analog inputs. The voltage on the on-chip capacitance to ground is switched through the analog differential input voltage, resulting in proportional currents entering the V IN(+) input and leaving the VIN(-) input. These current transients occur at the leading edge of the internal clocks. They rapidly decay and do not inherently cause errors as the on-chip comparator is strobed at the end of the clock perIod. Input Bypass Capacitors Bypass capacitors at the inputs will average these charges and cause a DC current to flow through the output resistances of the analog signal sources. This charge pumping action is worse for continuous conversions with the V IN(+) input voltage at full scale. For a 640kHz clock frequency with the VIN(+) input at 5V, this DC current is at a maximum of approximately 5A. Therefore, bypass capacitors should not be used at the analog inputs or the VREF/2 pin for high resistance sources (>1k). If input bypass capacitors are necessary for noise filtering and high source resistance is desirable to minimize capacitor size, the effects of the voltage drop across this input resistance, due to the average value of the input current, can be compensated by a full scale adjustment while the given source resistor and input bypass capacitor are both in place. This is possible because the average value of the input current is a precise linear function of the differential input voltage at a constant conversion rate. Input Source Resistance Large values of source resistance where an input bypass capacitor is not used will not cause errors since the input currents settle out prior to the comparison time. If a low- pass filter is required in the system, use a low-value series resistor (1k) for a passive RC section or add an op amp RC active low-pass filter. For low-source-resistance applications (1k), a 0.1F bypass capacitor at the inputs will minimize EMI due to the series lead inductance of a long wire. A 100 series resistor can be used to isolate this capacitor (both the R and C are placed outside the feedback loop) from the output of an op amp, if used. Stray Pickup The leads to the analog inputs (pins 6 and 7) should be kept as short as possible to minimize stray signal pickup (EMI). Both EMI and undesired digital-clock coupling to these inputs can cause system errors. The source resistance for these inputs should, in general, be kept below 5k. Larger values of source resistance can cause undesired signal pickup. Input bypass capacitors, placed from the analog inputs to ground, will eliminate this pickup but can create analog scale errors as these capacitors will average the transient input switching currents of the A/D (see Analog Input Current). This scale error depends on both a large source resistance and the use of an input bypass capacitor. This error can be compensated by a full scale adjustment of the A/D (see Full Scale Adjustment) with the source resistance and input bypass capacitor in place, and the desired conversion rate. Reference Voltage Span Adjust For maximum application flexibility, these A/Ds have been designed to accommodate a 5V, 2.5V or an adjusted voltage reference. This has been achieved in the design of the IC as shown in Figure 12. Notice that the reference voltage for the IC is either 1/2 of the voltage which is applied to the V+ supply pin, or is equal to the voltage which is externally forced at the V REF/2 pin. This allows for a pseudo-ratiometric voltage reference using, for the V+ supply, a 5V reference voltage. Alternatively, a voltage less than 2.5V can be applied to the V REF/2 input. The internal gain to the VREF/2 input is 2 to allow this factor of 2 reduction in the reference voltage. Such an adjusted reference voltage can accommodate a reduced span or dynamic voltage range of the analog input voltage. If the analog input voltage were to range from 0.5V to 3.5V, instead of 0V to 5V, the span would be 3V. With 0.5V fCLK VPEAK VPEAK
ADC0803, ADC0804 FN3094 Rev 4.00 Page 13 of 17 August 2002 Typical Applications Interfacing 8080/85 or Z-80 Microprocessors This converter has been designed to directly interface with 8080/85 or Z-80 Microprocessors. The three-state output capability of the A/D eliminates the need for a peripheral interface device, although address decoding is still required to generate the appropriate CS for the converter. The A/D can be mapped into memory space (using standard memory-address decoding for CS and the MEMR and MEMW strobes) or it can be controlled as an I/O device by using the I/OR and I/OW strobes and decoding the address bits A0 A7 (or address bits A8 A15, since they will contain the same 8-bit address information) to obtain the CS input. Using the I/O space provides 256 additional addresses and may allow a simpler 8- bit address decoder, but the data can only be input to the accumulator. To make use of the additional memory reference instructions, the A/D should be mapped into memory space. See AN020 for more discussion of memory-mapped vs I/O- mapped interfaces. An example of an A/D in I/O space is shown in Figure 21. The standard control-bus signals of the 8080 (CS , RD and WR) can be directly wired to the digital control inputs of the A/D, since the bus timing requirements, to allow both starting the converter, and outputting the data onto the data bus, are met. A bus driver should be used for larger microprocessor systems where the data bus leaves the PC board and/or must drive capacitive loads larger than 100pF. It is useful to note that in systems where the A/D converter is 1 of 8 or fewer I/O-mapped devices, no address-decoding circuitry is necessary. Each of the 8 address bits (A0 to A7) can be directly used as CS inputs, one for each I/O device. Interfacing the Z-80 and 8085 The Z-80 and 8085 control buses are slightly different from that of the 8080. General RD and WR strobes are provided and separate memory request, MREQ, and I/O request, IORQ, signals have to be combined with the generalized strobes to provide the appropriate signals. An advantage of operating the A/D in I/O space with the Z-80 is that the CPU will automatically insert one wait state (the RD and WR strobes are extended one clock period) to allow more time for the I/O devices to respond. Logic to map the A/D in I/O space is shown in Figure 22. By using MREQ in place of IORQ, a memory-mapped configuration results. Additional I/O advantages exist as software DMA routines are available and use can be made of the output data transfer which exists on the upper 8 address lines (A8 to A15) during I/O input instructions. For example, MUX channel selection for the A/D can be accomplished with this operating mode. The 8085 also provides a generalized RD and WR strobe, with an IO/M line to distinguish I/O and memory requests. The circuit of Figure 22 can again be used, with IO/M in place of IORQ for a memory-mapped interface, and an extra inverter (or the logic equivalent) to provide IO/M for an I/O-mapped connection. Interfacing 6800 Microprocessor Derivatives (6502, etc.) The control bus for the 6800 microprocessor derivatives does not use the RD and WR strobe signals. Instead it employs a single R/W line and additional timing, if needed, can be derived from the 2 clock. All I/O devices are memory-mapped in the 6800 system, and a special signal, VMA, indicates that the current address is valid. Figure 23 shows an interface schematic where the A/D is memory-mapped in the 6800 system. For simplicity, the CS decoding is shown using 1/2 DM8092. Note that in many 6800 systems, an already decoded 4/5 line is brought out to the common bus at pin 21. This can be tied directly to the CS pin of the A/D, provided that no other devices are addressed at HEX ADDR: 4XXX or 5XXX. In Figure 24 the ADC080X series is interfaced to the MC6800 microprocessor through (the arbitrarily chosen) Port B of the MC6820 or MC6821 Peripheral Interface Adapter (PlA). Here the CS pin of the A/D is grounded since the PlA is already memory- mapped in the MC6800 system and no CS decoding is necessary. Also notice that the A/D output data lines are connected to the microprocessor bus under program control through the PlA and therefore the A/D RD pin can be grounded. Application Notes NOTE # DESCRIPTION AN016 “Selecting A/D Converters” AN018 “Do’s and Don’ts of Applying A/D Converters” AN020 “A Cookbook Approach to High Speed Data Acquisition and Microprocessor Interfacing” AN030 “The ICL7104 - A Binary Output A/D Converter for Microprocessors”
NOTE: Pin numbers for 8228 System Controller: Others are 8080A. FIGURE 21. ADC080X TO 8080A CPU INTERFACE
ADC0803, ADC0804 FN3094 Rev 4.00 Page 16 of 17 August 2002 Die Characteristics DIE DIMENSIONS 101 mils x 93 mils METALLIZATION Type: Al Thickness: 10kÅ 1kÅ PASSIVATION Type: Nitride over Silox Nitride Thickness: 8kÅ Silox Thickness: 7kÅ Metallization Mask Layout ADC0803, ADC0804 WR RD CS CLK ININTRVIN (-) V IN (+) DGND VREF/2 AGND V+ OR VREF CLK R DB0DB1DB2DB3DB4 DB5 DB6 DB7 (MSB) V+ OR VREF
FN3094 Rev 4.00 Page 17 of 17 August 2002 ADC0803, ADC0804 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2002. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpen- dicular to datum . 7. e B and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dam- bar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E20.3 (JEDEC MS-001-AD ISSUE D)
20 LEAD DUAL-IN-LINE PLASTIC PACKAGE
A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.55 1.77 8 C 0.008 0.014 0.204 0.355 - D 0.980 1.060 24.89 26.9 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - e A 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N2 0 2 0 9 Rev. 0 12/93