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Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 55
Technical content
Features
Low power architecture Surface mount technology (SMT) device Self-adjusting power-saving modes for longer battery life High speed motion detection up to 15ips Self-adjusting frame rate for optimum performance Motion detect pin output Finger detect pin output Internal oscillator – no clock input needed Selectable 250, 500, 750, 1000 and 1250 cpi resolution Dual 2.8V/1.8V or single 2.8V supply options Selectable Input/Output voltage at 2.8V or 1.8V nominal Serial peripheral interface (SPI) or Two wire interface (TWI) Integrated chip-on-board LED with wavelength of 870nm
Applications
Finger input devices Mobile devices Integrated input devices Battery-powered input device Avago customers purchasing the ADBS-A320 OFN product are eligible to receive a royalty free license to our US patents 6977645, 6621483, 6950094, 6172354 and 7289649, for use in their end products.
Pinout of ADBS-A320 Optical Sensor Pin Name Description Input/Output pin Function
1 GND Ground
2 XY_LED XY LED driver connection Must connect to LED- (see schematics fi g 7a,7b)
3 MOTION Motion Detect
(active low output) O (CMOS output) Open when not used Default active low signal, can be changed in Motion_Control register 0x1d
4 GPIO General Purpose Input /
O (CMOS output) Pin indicate Finger Presence Detection, OFN engine 0x60 must be enabled (see application note OFN A320 fi rmware design guide). Open when not used
5 VDDIO Voltage supply for I/O Sets I/O voltage but not for nDREG_EN
6 IO_MOSI_A0 TWI address set or
I (Schmitt trigger input) SPI : MOSI (Master Out Slave In) signal TWI : address select 0 Open when not used
7 IO_CLK Serial clock input I (Schmitt trigger input) Serial clock signal
8 IO_MISO_SDA TWI serial data or
In SPI – CMOS output. In TWI – open drain I/O SPI : MISO (Master Input Slave Out) signal TWI : serial data signal
9 IO_NCS_A1 TWI address set or
I (Schmitt trigger input) SPI : NCS (chip select) signal TWI : address select 1 Open when not used Active low signal
10 NRST Hardware Chip Reset I (Schmitt trigger input) Set to high when not used
11 GND Ground
12 ORIENT Sensor orientation input I (Schmitt trigger input) Set to high when not used
13 SHTDWN Shutdown (active high input) I (Schmitt trigger input) Set to low when not used
14 VDDIO Voltage supply for I/O Sets I/O voltage but not for nDREG_EN
15 IO_SELECT SPI / TWI Select I (Schmitt trigger input) TWI : GND or SPI : High
16 DVDD Digital Supply voltage or
In regulator disabled, supply 1.8V. In regulator enabled, do not supply 1.8V. 17 nDREG_EN Digital Regulator enable signal I (Schmitt trigger input) Tie to VDDA to disable internal regulator or GND to supply 1.8V to DVDD
18 NC No Connect No Connection
19 NC No Connect No Connection
20 VDDA Analog Voltage input
21 GND Ground
22 GND Ground
23 NC No Connect No connection
24 LED- LED Cathode Must connect to XY_LED
25 LED- LED Cathode Must connect to XY_LED
26 LED- LED Cathode Must connect to XY_LED
27 LED+ LED Anode Provide 2.8V supply voltage
28 GND Ground
Note when A0, A1 is in NC, the sensor will drive the pin to 0 or low.
- Dimension in millimeters/inches
- Coplanarity of pads : 0.08mm
- Non Cumulative Pad pitch tolerance : ± 0.10mm
- Dimensional tolerance (unless otherwise stated) : ± 0.10mm
- All critical dimensions are indicated by number enclosed in a circle.
Figure 2. Package outline drawing
22 GND
24 LED(-)
25 LED(-)
26 LED(-)
27 LED(+)
28 GND
1 GND
2 XY-LED
3 MOTION
4 GPIO
5 VDDIO
6 IO_MOSI_AO
7 IO_CLK
scribing the cover plate molding features. defi ned features on the cover plate. features on the package that align to the lens. well as illumination of the surface at the optimum angle. Features on the lens align it to the sensor and cover plate. Guide for more details on process fl ow.
Note :- Dome + must be connected to MCU to detect button change state and Dome – can be connected to GND Figure 7a. Schematic diagram for interface between ADBS-A320 and 3V microcontroller via SPI with internal Regulator 1.8V enabled 1u F / 16 V MPS 430F 1222IPW 0603 SW 2 SW 3 VDD 2 100 k 1 % 910 VSS 2 VSS 2 VDD 2 C 1 10 nF VSS 2 1 2 LEFT_ SW RIGHT _SW R 1 R5 100 k 1 % 0603 100 k 1 % 0603 VDD 2 VSS 2 VDD 2 2U 1 100 nF /1 6 V 0603 32 .768KHz X 2 VSS 2VSS RST/NMI P1.4 P1.5 P1.6 P1.7 TST XOUT IXIN P3.5/RXD P3.4/TXD VDD P1.0 P1.1 P1.2 P1.3 P2.5 P2.1 P2.2 P2.3 P2.4 P2.0 P3.0 P3.6 P3.7 P3.2/MISO P3.3/CLK P3.1/MOSI 12 1117 MISO_SDA MOSI_A0 CLK NCS_A 1 MOTION SHTDWN NRST ORIENT VDDIO5 ADBS-A320 VDD 2 VSS 1 D 1
1 M , 1 %
LP 2950 CD T-3.0 OUTPUT INPUT GND2 1 3 C2 2 C2 3 4.7 uF /10 V 100 nF /1 6 V 0603 0603 C2 1 100 nF /1 6 V 0603 R 10 1u F / 16 V 0805 0805 0603 220 R BQ 24200 DGN MSOP-8 IN VCC STAT VSS OUT BAT CE N /C 1u F / 16 V 0805 C 19 BAT 54 C SOT 23 3 21 R 19 R2 0 C2 5 1n F 0603 51k 1 % 0603 0603 51k 1 % VSS 2VSS 2SW 6 10 nF CN 1 DATA - DATA + V + I D GND VDD 1 1u F VDDA20 10 nF 1u F VDD 2 VDDIO LED - 24 LED - 25 LED - 26 LED + 27 GPIO4 10 nF 1u F VDD 3 XY_LE D 2 VSS 2 VSS 1 VSS 3 DVDD 16 3.3 uF VSS 1 IO _Select15 VSS 2GND 11GND 21GND 22GND 28GGND 17nDREG VSS 1 NC 23 NC 19NC NC NCNC
Note :- Dome + must be connected to MCU to detect button change state and Dome – can be connected to GND. Figure 7b. Schematic diagram for interface between ADBS-A320 and 1.8V microcontroller via SPI with internal Regulator 1.8V enabled 1u F / 16 V 1.8V micro controller 0603 SW 2 SW 3 VDD 1.8 100 k 1 % 910 VSS 2 VSS 2 VDD 1.8 C 1 10 nF VSS 2 1 2 LEFT_ SW RIGHT_SW R 1 R5 100 k 1 % 0603 100 k 1 % 0603 VDD 1.8 VSS 2 VDD 1.8 2U 1 100nF /1 6 V 0603 32 .768KHz X 2 VSS 4VSS RST/NMI P1.4 P1.5 P1.6 P1.7 TST XOUT IXIN P3.5/RXD P3.4/TXD VDD P1.0 P1.1 P1.2 P1.3 P2.5 P2.1 P2.2 P2.3 P2.4 P2.0 P3.0 P3.6 P3.7 P3.2/MISO P3.3/CLK P3.1/MOSI 12 1117 MISO _SDA MOSI_ A0 CLK NCS _A 1 MOTION SHTDWN NRST ORIENT VDDIO5 ADBS-A320 VDD 2 VSS 1 D 1
1 M, 1 %
LP 2950 CD T-3.0 OUTPUT INPUT GN D2 1 3 C2 2 C2 3 4.7 uF/10 V 100 nF/16 V 0603 0603 C2 1 100 nF/16 V 0603 R10 1u F / 16 V 0805 0805 0603 220 R BQ24200 DGN MSOP-8 IN VCC STAT VSS OUT BAT CE N /C 1u F / 16 V 0805 C 19 BAT 54C SOT 23 3 21 R 19 R2 0 C2 5 1n F 0603 51k 1 % 0603 0603 51k 1 % VSS 2VSS 2SW 6 10 nF CN 1 DATA - DATA + V + I D GND VDD 1.8 1u F VDDA20 10 nF 1u F VDD 2 VDDIO LED - 24 LED - 25 LED - 26 LED + 27 GPIO4 10 nF 1u F VDD 3 XY_LE D 2 VSS 2 VSS 1 VSS 3 DVDD 16 3.3 uF VSS 1 IO_Select15 1u F C2 0 0805 VDD 1.8 VSS 4 LP 2989 LV-1.8 OUTPUTI NPUT GND2 1 3 C2 2 C2 3 4.7 uF/10 V 100 nF 0603 0603 C2 1 100 nF 0603 VSS 2GND 11GND 21GND 22GND 28GGND 17nDREG VSS 1 NC 23 NC 19NC NC NCNC
Figure 7c. Schematic diagram for interface between ADBS-A320 and 3V microcontroller via SPI with internal Regulator 1.8V disabled 1u F / 16 V Micro controller 0603 SW 2 SW 3 VDD 1.8 100 k 1 % 910 VSS 2 VSS 2 VDD 2 C 1 10 nF VSS 2 1 2 LEFT_ SW RIGHT_SW R 1 R5 100 k 1 % 0603 100 k 1 % 0603 VDD2 VSS 2 VDD 2 2U 1 100 nF /1 6 V 0603 32 .768KHz X 2 VSS 2VSS RST/NMI P1.4 P1.5 P1.6 P1.7 TST XOUT IXIN P3.5/RXD P3.4/TXD VDD P1.0 P1.1 P1.2 P1.3 P2.5 P2.1 P2.2 P2.3 P2.4 P2.0 P3.0 P3.6 P3.7 P3.2/MISO P3.3/CLK P3.1/MOSI 12 1117 MISO_SDA MOSI_A0 CLK NCS_A 1 MOTION SHTDWN NRST ORIENT VDDIO5 ADBS-A320 VDD 2 VSS 1 D 1 LP 2950 CD T-3.0 OUTPUT INPUT GND2 1 3 C2 2 C2 3 4.7 uF /10 V 100 nF /1 6 V 0603 0603 C2 1 100 nF /1 6 V 0603 R 10 1u F / 16 V 0805 0805 0603 220 R BQ 24200 DGN MSOP-8 IN VCC STAT VSS OUT BAT CE N /C 1u F / 16 V 0805 C 19 BAT 54 C SOT 23 3 21 R 19 R2 0 C2 5 1n F 0603 51k 1 % 0603 0603 51k 1 % VSS 2VSS 2SW 6 10 nF CN 1 DATA- DATA+ V + I D GND VDD 1 1u F VDDA20 10 nF 1u F VDD 2 VDDIO LED- 24 LED- 25 LED- 26 LED+ 27 GPIO4 10 nF 1u F VDD 3 XY_LE D 2 VSS 2 VSS 1 VSS 3 IO_Select15 1u F C2 0 0805 VDD 1.8 VSS 4 LP 2989 LV-1.8 OUTPUTI NPUT GND2 1 3 C2 2 C2 3 4.7 uF /10 V 100 nF 0603 0603 C2 1 100 nF 0603 DVDD 16 0.0 1u F VSS 4 VDD 1.8 C3 0 1uF VSS 2GND 11GND 21GND 22GND 28GGND 17nDREG VDD2 NC 23 NC 19NC NC NCNC
Note :- Dome + must be connected to MCU to detect button change state and Dome – can be connected to GND. Figure 7d. Schematic diagram for interface between ADBS-A320 and 1.8V microcontroller via SPI with internal Regulator 1.8V disabled 1u F / 16 V 1.8V micro controller 0603 SW 2 SW 3 VDD 1.8 100 k 1 % 910 VSS 2 VSS 2 VDD 1.8 C 1 10 nF VSS 2 1 2 LEFT_ SW RIGHT_SW R 1 R5 100 k 1 % 0603 100 k 1 % 0603 VDD 1.8 VSS 2 VDD 1.8 2U 1 100 nF /1 6 V 0603 32 .768KHz X 2 VSS 4VSS RST/NMI P1.4 P1.5 P1.6 P1.7 TST XOUT IXIN P3.5/RXD P3.4/TXD VDD P1.0 P1.1 P1.2 P1.3 P2.5 P2.1 P2.2 P2.3 P2.4 P2.0 P3.0 P3.6 P3.7 P3.2/MISO P3.3/CLK P3.1/MOSI 12 1117 MISO_SDA MOSI_A0 CLK NCS_A 1 MOTION SHTDWN NRST ORIENT VDDIO5 ADBS-A320 VDD 2 VSS 1 D 1 LP 2950 CD T-3.0 OUTPUT INPUT GND2 1 3 C2 2 C2 3 4.7 uF /10 V 100 nF /1 6 V 0603 0603 C2 1 100 nF /1 6 V 0603 R 10 1u F / 16 V 0805 0805 0603 220 R BQ 24200 DGN MSOP-8 IN VCC STAT VSS OUT BAT CE N /C 1u F / 16 V 0805 C 19 BAT 54 C SOT 23 3 21 R 19 R2 0 C2 5 1n F 0603 51k 1 % 0603 0603 51k 1 % VSS 2VSS 2SW 6 10 nF CN 1 DATA- DATA+ I D GND VDD 1.8 1u F VDDA20 10 nF 1u F VDD 2 VDDIO LED- 24 LED- 25 LED- 26 LED+ 27 GPIO4 10 nF 1u F VDD 3 XY_LE D 2 VSS 2 VSS 4 VSS 3 IO_Select15 1u F C2 0 0805 VDD 1.8 VSS 4 LP 2989 LV-1.8 OUTPUTI NPUT GND2 1 3 C2 2 C2 3 4.7 uF /10 V 100 nF 0603 0603 C2 1 100 nF 0603 DVDD 16 0.0 1u F VSS 4 VDD 1.8 C3 0 1uF VSS 2GND 11GND 21GND 22GND 28GGND 17nDREG VDD2 NC 23 NC 19NC NC NCNC
I/O Voltage options (values listed are typical) Internal regulator status nDREG pin V DDA DVDD VDDIO I/O pin interface voltage Notes for DV DD Notes for pin18 & 19 connection Enabled GND (Fig 7a) 2.8V Output 1.8V with bypass capacitor 3.3uF External 1.8V or V DDA 1.8V or 2.8V Do not use internal regulator output voltage as supply to other circuits. MUST be No Connect (NC) Disabled V DDA (Fig 7b) 2.8V Input of 1.8V with 0.01uF and 1uF External 1.8V or V DDA 1.8V or 2.8V Require external voltage supply. Prefer if No Connect. Optional connection to GND allowed Regulatory Requirements Passes FCC B and worldwide analogous emission limits when assembled following Avago Technologies recommendations. Passes IEC-55024 or CISPR 24 radiated susceptibility level when assembled following Avago Technologies recommendations. Absolute Maximum Ratings Parameter Symbol Minimum Maximum Units Notes Storage Temperature T S -40 85 °C Lead Solder Temp 260 °C For 1.4 seconds Moisture Sensitivity Level MSL 1 Referring to JEDEC-J-STD-020. Analog Supply Voltage V DDA -0.5 3.6 V I/O Supply Voltage V DDIO -0.5 3.6 V Digital Supply Voltage DV DD -0.5 2 V LED supply voltage V LED+ -0.5 3.6 V ESD (sensor only) 2 kV All pins, human body model JESD22-A114-E Input Voltage V IN -0.5 V DDA+0.5 VDDIO+0.5 V nDREG_EN pin All pins except nDREG_EN pin Latchup Current Iout 20 mA All Pins Note - Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are the stress ratings only and functional operation of the device at these or any other condition beyond those indicated may aff ect device reliability. At power up, if DV DD is powered up before V DDA, DV DD should never exceed V DDA by more than 0.7V to avoid high inrush current. If DV DD is powered up before V DDA, then V DDA must ramp up to stable voltage in less than 1.5seconds. In this case high inrush current of up to 180mA can be observed at DV DD. At power down, if V DDA is powered down before DV DD and VDDIO, then DVDD must ramp down to 0V in less than 1.5seconds. In this case high inrush current of up to 180mA can be observed at DV DD.
Recommended Operating Conditions Parameter Symbol Minimum Typical Maximum Units Notes Operating Temperature T A -20 60 °C Analog supply voltage V DDA 2.6 2.8 3.3 Volts Including V NA noise. voltages but not for nDREG_EN. See fi g 7a, 7b. Digital supply voltage DV DD 1.65 1.8 1.95 Volts Input voltage supply when nDREG pin is high. Input voltage supply not required when nDREG is GND LED supply voltage V LED+ 2.6 2.8 3.3 Volts Including V NA noise. Power supply rise time t VRT 0.001 100 ms 0 to 2.8V Supply noise (Sinusoidal) V NA 100 mV p-p 10kHz-50MHz Speed S 15 in/sec Using prosthetic fi nger as surface Electrical Characteristics at 25°C, VDDA=2.8V, DVDD=1.8V. Parameter Symbol Minimum Typical Maximum Units Notes Motion delay after reset t MOT-RST 3.5 23 ms From Hard or Soft_RESET register write to valid register write/read and motion, assuming motion is present Shutdown t SHTDWN 50 ms From SHTDWN pin active to low current Wake from shutdown t WAKEUP 100 ms From SHTDWN pin inactive to valid motion. Refer to section “Notes on Shutdown” , also note t MOT-RST MOTION rise time t r-MOTION 150 300 ns C L = 100pF MOTION fall time t f-MOTION 150 300 ns C L = 100pF SHTDWN pulse width t P-SHTDWN 150 ms NRST pulse width t NRST 20 us From edge of valid NRST pulse Reset wait time after stable supply voltage tVRT-NRST 100 ms Transient Supply Current I DDT 75 mA Max supply current for 500 usec for each supply voltages ramp from 0 to 3.3V
Electrical Characteristics at 25°C, VDDA=3.3V, DVDD=1.95V at default LED setting 13mA. Parameter Internal regulator Enabled Internal regulator Disabled Typical Max Typical Max Units Notes DC average supply current in Run mode I V DDA 1.80 2.50 0.90 1.10 mA GPIO=SHTDWN=pull low, IO_MISO=NRST=ORIENT=pull high. IDD_LED+ 1.30 1.80 1.30 1.80 mA GPIO=SHTDWN=pull low, IO_MISO=NRST=ORIENT=pull high. I DVDD 0 0 0.90 1.40 mA GPIO=SHTDWN=pull low, IO_MISO=NRST=ORIENT=pull high. Total 3.10 4.30 3.10 4.30 mA DC average supply current in Rest1 mode I V DDA 0.20 0.30 0.10 0.15 mA GPIO=SHTDWN=pull low, IO_MISO=NRST=ORIENT=pull high. IDD_LED+ 0.20 0.40 0.20 0.40 mA GPIO=SHTDWN=pull low, IO_MISO=NRST=ORIENT=pull high. I DVDD 0 0 0.10 0.15 mA GPIO=SHTDWN=pull low, IO_MISO=NRST=ORIENT=pull high. Total 0.40 0.70 0.40 0.70 mA DC average supply current in Rest2 mode I V DDA 0.06 0.12 0.03 0.07 mA GPIO=SHTDWN=pull low, IO_MISO=NRST=ORIENT=pull high. IDD_LED+ 0.04 0.08 0.04 0.08 mA GPIO=SHTDWN=pull low, IO_MISO=NRST=ORIENT=pull high. I DVDD 0 0 0.03 0.05 mA GPIO=SHTDWN=pull low, IO_MISO=NRST=ORIENT=pull high. Total 0.10 0.20 0.10 0.20 mA DC average supply current in Rest3 mode I V DDA 0.03 0.12 0.02 0.06 mA GPIO=SHTDWN=pull low, IO_MISO=NRST=ORIENT=pull high. IDD_LED+ 0.01 0.03 0.01 0.03 mA GPIO=SHTDWN=pull low, IO_MISO=NRST=ORIENT=pull high. I DVDD 0 0 0.01 0.06 mA GPIO=SHTDWN=pull low, IO_MISO=NRST=ORIENT=pull high. Total 0.04 0.15 0.04 0.15 mA Analog shutdown supply current I DDSHTDWN VDDA 17 44.3 0 2 Α GPIO=pull low, SHTDWN= IO_MISO=NRST=ORIENT=pull high. Analog shutdown supply current I DDSHTDWN VLED+ 0 0.7 0 0.7 Α GPIO=pull low, SHTDWN= IO_MISO=NRST=ORIENT=pull high. Digital shutdown supply current I DDSHTDWN DVDD 0031 5 Α GPIO=pull low, SHTDWN= IO_MISO=NRST=ORIENT=pull high.
Electrical Characteristics at 25°C, VDDA=3.3V, DVDD=1.95V at default LED setting 13mA. Parameter Symbol Minimum Typical Maximum Units Notes VDDIO DC Supply Current I V DDIO 10 uA Average current V DDIO. Analog peak supply current I PEAK VDDA 2.5 mA At LED register setting of 40mA. LED+ peak supply current I PEAK LED+ 49.5 mA At LED register setting of 40mA. Digital Peak supply current I PEAK DVDD 1.5 mA At LED register setting of 40mA. Input Low Voltage V IL -0.05 0 V DDIO*0.35 V IO_MOSI_A0, IO_CLK, IO_MISO_SDA, IO_NCS_A1, NRST, ORIENT, SHTDWN, IO_SELECT Input High Voltage V IH VDDIO * 0.7 V DDIO VDDIO+0.05 V IO_MOSI_A0, IO_CLK, IO_MISO_SDA, IO_NCS_A1, NRST, ORIENT, SHTDWN, IO_SELECT Input hysteresis V HYS 100 mV Input leakage current I leak ±1 ±10 A IO_MOSI_A0, IO_CLK, IO_MISO_SDA, IO_NCS_A1, NRST, ORIENT, SHTDWN, IO_SELECT Output Low Voltage V OL 0.2 V I out=1.2mA Output High Voltage V OH VDDIO-0.2 V DDIO-0.1 V I out=600uA Input Capacitance C in 10 pF MOSI, NCS, SCLK, SHTDWN Notes on Power-up The ADBS-A320 does not perform an internal power up self-reset; the NRST pin must be toggled every time power is applied. The appropriate sequence is as follows: 9. Check registers 0x64 with 0x08, 0x65 with 0x06, 0x66 with 0x40, 0x67 with 0x08, 0x68 with 0x48, 0x69 with 0x0a, 0x6a with 0x50, 0x6b with 0x48. 10. Check Assert/De-assert registers, 0x6d with 0xc4, 0x6e with 0x34, 0x6f with 0x3c, 0x70 with 0x18, 0x71 with 0x20. 11. Check Finger Presence Detect register, 0x75 with 0x50. 12. IF XY Quantization is used, check 0x73 with 0x99 and 0x74 with 0x02. 13. Write 0x10 to register 0x1C. This will activate burst mode. If burst mode not used then skip this step. 14. Read from registers 0x02, 0x03 and 0x04 (or read these same 3 bytes from burst motion) one time regardless the state of the motion pin. 15. Check 0x1a with 0x00 to set LED drive current to 13mA. 16. At power down, see Notes on Power Down sequence below. 1. Apply power. See Notes on Power Up sequence below. 2. Set NCS pin high if using SPI. If TWI, then NCS_A1 will follow TWI address. Set Shutdown pin low and Orient. Set IO_Select pin to low (for TWI) or high (for SPI). 3. If in TWI mode, set A0 and A1 according to the Table TWI slave address in datasheet. This step is skipped if SPI mode is used. 4. In TWI, drive NRST low then high. This is optional for SPI. TWI slave address will only be selected after a NRST toggle is applied when A0 and A1 is set. 5. If in SPI mode, wait until sensor valid power up by reading Product ID register. If in TWI mode, skip this step. 6. If in SPI mode, perform soft reset by writing 0x5A to address 0x3a. In TWI mode, this is not required. 7. Write 0xE4 to address 0x60. 8. Set Speed Switching, write 0x62 with 0x12, 0x63 with 0x0E.
Presence Detect and XY Quantisation register settings. DVDD. VDDIO can be applied in any order. See Absolute Maximum Rating for other condition. power supply is high but before any clocks are available. Figure 8. Power up and down sequence
As in step 4, in TWI mode, the sensor must be toggle with hard reset. The hard reset via toggling NRST pin high to low then high again must observe t VRT-NRST and tNRST. Then a time of t MOT-RST must be observed before accessing the sensor registers via SPI or TWI ports. See two graphs for Hard reset condition. If SPI mode is used, then hard reset is not required. Instead a soft reset can be employed. Note that time t VRT-NRST and tMOT-RST must be observed before accessing SPI ports. The Shutdown, Orient, IO_Select and TWI ports are stable after proper power up procedures. The table below shows the state of the various pins during power-up and reset. State of Signal Pins After VDDA is Valid Pin NCS high before reset NCS Low before reset After Reset NCS High Low Functional MISO Undefi ned Functional Depends on NCS SCLK Ignored Functional Depends on NCS MOSI Ignored Functional Depends on NCS XY_LED Undefi ned Undefi ned Functional MOTION Undefi ned Undefi ned Functional SHTDWN Must be low Must be low Functional NRST High High High IO_Select SPI: High, TWI:Low SPI: High, TWI:Low SPI: High, TWI:Low ORIENT Top view High High High ORIENT Top view Low Low Low GPIO Undefi ned Undefi ned Undefi ned
Notes on Shutdown and Reset The ADBS-A320 can be set in Shutdown mode by asserting or setting SHTDWN pin high. During the shutdown state, supply voltages V DDIO and DV DD must be maintained above the minimum level. If these conditions are not met, then the sensor must be restarted by powering down then powering up again for proper operation. Any register settings must then be reloaded. During the shutdown state, supply voltages V DDIO and DVDD must be maintained above the minimum level. For proper operation, SHTDWN pulse width must be at least t P-SHTDWN. Shorter pulse widths may cause the chip to enter an undefi ned state. In addition, the SPI or TWI port should not be accessed when SHTDWN is asserted. (Other ICs on the same SPI bus can be accessed, as long as the sensor’s NCS pin is not asserted.) The table below shows the state of various pins during shutdown. After deassert- ing SHTDWN, wait t WAKEUP before accessing the SPI port. Reinitializing the sensor from shutdown state will retain all register data that were written to the sensor prior to shutdown (see register table page 34 for list of registers). If the internal regulator is disabled and V DDA is removed but DVDD is retained, reinitializing the sensor from shutdown state will retain all register data that were written to the sensor prior to shutdown. See register table page 34 for list of registers. The reset of the sensor via Soft_RESET register or through the NRST pin would reset all registers to the default value. Any register settings must then be reloaded. Power management modes The ADBS-A320 has three power-saving modes. Each mode has a diff erent motion detection period, aff ecting response time to sensor motion (Response Time). The sensor automatically changes to the appropriate mode, depending on the time since the last reported motion (Downshift Time). The parameters of each mode are shown in the following table. Mode Response Time (nominal) Downshift Time (nominal) Rest 1 19.5 ms 250 ms Rest 2 96 ms 9.5 s Rest 3 482 ms 582 s Motion Pin Timing The motion pin is a level-sensitive output that signals the micro-controller when motion has occurred. The motion pin is lowered whenever the motion bit is set; in other words, whenever there is data in the Delta_X or Delta_Y registers. Clearing the motion bit (by reading Delta_Y and Delta_X, or writing to the Motion register) will put the motion pin high. LED Mode For power savings, the LED will not be continuously on. ADBS-A320 will fl ash the LED only when needed. Pin SHTDWN active NCS Functional* MISO Undefi ned SCLK Undefi ned MOSI Undefi ned XY_LED Low current MOTION Undefi ned NRST High IO_Select SPI:High, TWI:Low ORIENT Top view High ORIENT Top view Low GPIO Undefi ned *In Regulator disabled mode, NCS pin must be held to 1 (high) if SPI bus is shared with other devices. Note: There are long wakeup times from shutdown. These features should not be used for power management during normal sensor motion.
Serial Peripheral Interface (SPI) Electrical Characteristics at 25°C, VDDA=2.8V, DVDD=1.8V. Parameter Symbol Minimum Typical Maximum Units Notes Serial Port Clock Frequency f sclk 1 MHz Active drive, 50% duty cycle MISO rise time tr-MISO 150 300 ns CL = 100pF MISO fall time tf-MISO 150 300 ns CL = 100pF MISO delay after SCLK tDLY-MISO 120 ns From SCLK falling edge to MISO data valid, no load conditions MISO hold time thold-MISO 0.5 1/fSCLK s Data held until next falling SCLK edge MOSI hold time thold-MOSI 200 ns Amount of time data is valid after SCLK rising edge MOSI setup time tsetup-MOSI 120 ns From data valid to SCLK rising edge SPI time between write commands tSWW 30 s From rising SCLK for last bit of the fi rst data byte, to rising SCLK for last bit of the second data byte. SPI time between write and read commands tSWR 20 s From rising SCLK for last bit of the fi rst data byte, to rising SCLK for last bit of the second address byte. SPI time between read and subsequent commands tSRW tSRR 500 ns From rising SCLK for last bit of the fi rst data byte, to falling SCLK for the fi rst bit of the address byte of the next command. SPI read address-data delay tSRAD 4 s From rising SCLK for last bit of the address byte, to falling SCLK for fi rst bit of data being read. NCS inactive after motion burst tBEXIT 500 ns Minimum NCS inactive time after motion burst before next SPI usage NCS to SCLK active tNCS-SCLK 120 ns From NCS falling edge to fi rst SCLK falling edge SCLK to NCS inactive (for read operation) tSCLK-NCS 120 ns From last SCLK rising edge to NCS rising edge, for valid MISO data transfer SCLK to NCS inactive (for write operation) tSCLK-NCS 20 us From last SCLK rising edge to NCS rising edge, for valid MOSI data transfer NCS to MISO high-Z tNCS-MISO 500 ns From NCS rising edge to MISO high-Z state
ADBS-A320 uses a two-wire serial control interface compatible with I2C. The parameters are listed below. Electrical Characteristics at 25°C, VDDA=2.8V, DVDD=1.8V.
- All values referred to V IHMIN and VILMAX levels.
- A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V IHMIN of the SCL signal) to bridge the undefi ned
region of the falling edge of SCL.
- The maximum has t HD;DAT only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
- C B = total capacitance of one bus line in pF.
Table 1. TWI slave address transfer clock (SCL) signal and a serial data (SDA) signal. greater than the minimum timing. host at the host’s request. Data is sent in Eight-bit packets. driving SDA from low to high while SCL is held high.
Figure 17. TWI Start and Stop operation acknowledge (NAK) is defi ned as 1. Command packets contain a 7-bit ADBS-A320 device address and an active low read/write bit (R/W).
Contains 8 data bits and may be sent by the host or the ADBS-A320. with the most signifi cant bit fi rst. Figure 18. Host packets A320’s ACK if it wants to start a new data transfer. data transfer with the same ADBS-A320.
Figure 21. TWI single byte read
Figure 22. TWI polling registers using the ai bit example below.
DATA_RDY interrupt pin and/or update bit in the STATUS register bit are set. In the example below, 3 bytes are read successively from registers 0x03, 0x04, and 0x05. Figure 23. TWI ai bit
1010111 STOP
There are several I2C timing sequences which must be observed for OFN sensors. They are listed below. continue on the I2C bus. See fi gure26 for timing diagram. Figure 26. I2C quiet time during NRST most applications as it is not necessary to initiate hard reset after recovery from shutdown.
The ADBS-A320 registers are accessible via the serial port. The registers are used to read motion data and status as well as to set the device confi guration. Address Register Read/ Write Default Value Address Register Read/ Write Default Value 0x00 Product_ID* R 0x83 0x40-0x5f Reserved 0x01 Revision_ID* R 0x01 0x60 OFN_Engine* R/W 0x00 0x02 Motion R/W Any 0x61 Reserved 0x03 Delta_X R Any 0x62 OFN_Resolution* R/W 0x1a 0x04 Delta_Y R Any 0x63 OFN_Speed_Control* R/W 0x04 0x05 SQUAL R Any 0x64 OFN_Speed_ST12* R/W 0x08 0x06 Shutter_Upper R Any 0x65 OFN_Speed_ST21* R/W 0x06 0x07 Shutter_Lower R Any 0x66 OFN_Speed_ST23* R/W 0x40 0x08 Maximum_Pixel R Any 0x67 OFN_Speed_ST32* R/W 0x08 0x09 Pixel_Sum R Any 0x68 OFN_Speed_ST34* R/W 0x48 0x0a Minimum_Pixel R Any 0x69 OFN_Speed_ST43* R/W 0x0a 0x0b Pixel_Grab R/W Any 0x6a OFN_Speed_ST45* R/W 0x50 0x0c CRC0* R 0x00 0x6b OFN_Speed_ST54* R/W 0x48 0x0d CRC1* R 0x00 0x6c Reserved 0x0e CRC2* R 0x00 0x6d OFN_AD_CTRL* R/W 0xc4 0x0f CRC3* R 0x00 0x6e OFN_AD_ATH_HIGH* R/W 0x34 0x10 Self_Test W 0x00 0x6f OFN_AD_DTH_HIGH* R/W 0x3c 0x11 Confi guration_Bits* R/W 0x00 0x70 OFN_AD_ATH_LOW* R/W 0x18 0x12-0x19 Reserved 0x71 OFN_AD_DTH_LOW* R/W 0x20 0x1a LED_Control* R/W 0x00 0x72 Reserved 0x1b Reserved 0x73 OFN_Quantize_CTRL* R/W 0x99 0x1c IO_Mode* R/W 0x00 0x74 OFN_XYQ_THRESH* R/W 0x02 0x1d Motion_Control W 0x00 0x75 OFN_FPD_CTRL* R/W 0x50 0x1e-0x2d Reserved 0x76 Reserved 0x2e Observation R/W Any 0x77 OFN_Orientation_CTRL* R/W 0x01 0x2f-0x39 Reserved 0x3a Soft_RESET W 0x00 0x3b Shutter_Max_Hi* R/W 0x0b 0x3c Shutter_Max_Lo* R/W 0x71 0x3d Reserved 0x3e Inverse_Revision_ID* R 0xFE 0x3f Inverse_Product_ID* R 0x7C * Note - Registers with * will retain the same register values before and after shutdown if the supply voltages remain above th eir minimum values. In any case where there is a need to disable VDDA during shutdown, it is advisable that the register values are reloaded after VDDA is enabled to prevent any loss in register settings during VDDA cycling.
Product_ID Address: 0x00 Access: Read Reset Value: 0x83 Bit 7 6 5 4 3 2 1 0 Field PID7 PID 6 PID5 PID 4 PID 3 PID2 PID1 PID0 Data Type: 8-Bit unsigned integer. USAGE: This register contains a unique identifi cation assigned to the ADBS-A320. The value in this register does not change; it can be used to verify that the serial communications link is functional. Revision_ID Address: 0x01 Access: Read Reset Value: 0x01 Bit 7 6 5 4 3 2 1 0 Field RID7 RID 6 RID5 RID 4 RID 3 RID2 RID1 RID0 Data Type: 8-Bit unsigned integer. USAGE: This register contains the IC revision. It is subject to change when new IC versions are released.
Motion Address: 0x02 Access: Read/Write Reset Value: Any Bit 7 6 5 4 3 2 1 0 Field MOT PIXRDY PIXFIRST OVF Reserved Reserved Reserved GPIO Data Type: Bit fi eld. USAGE: Register 0x02 allows the user to determine if motion has occurred since the last time it was read. If the MOT bit is set, then the user should read registers 0x03 and 0x04 to get the accumulated motion. Read this register before reading the Delta_Y and Delta_X registers. Writing anything to this register clears the MOT and OVF bits, Delta_Y and Delta_X registers. The written data byte is not saved. Internal buff ers can accumulate more than eight bits of motion for X or Y. If either one of the internal buff ers overfl ows, then absolute path data is lost and the OVF bit is set. This bit is cleared once some motion has been read from the Delta_X and Delta_Y registers, and if the buff ers are not at full scale. Since more data is present in the buff ers, the cycle of reading the Motion, Delta_X and Delta_Y registers should be repeated until the motion bit (MOT) is cleared. Until MOT is cleared, either the Delta_X or Delta_Y registers will read either positive or negative full scale. If the motion register has not been read for long time, at 500 cpi it may take up to 16 read cycles to clear the buff ers, at 1000 cpi, up to 32 cycles. To clear an overfl ow, write anything to this register. The PIXRDY bit will be set whenever a valid pixel data byte is available in the Pixel_Dump register. Check that this bit is set before reading from Pixel_Dump. To ensure that the Pixel_Grab pointer has been reset to pixel 0,0 on the initial write to Pixel_Grab, check to see if PIXFIRST is set to high. Field Name Description MOT Motion since last report 0 = No motion 1 = Motion occurred, data ready for reading in Delta_X and Delta_Y registers PIXRDY Pixel Dump data byte is available in Pixel_Dump register 0 = data not available 1 = data available PIXFIRST This bit is set when the Pixel_Grab register is written to or when the complete pixel array has been read, initiating an increment to pixel 0,0. 0 = Pixel_Grab data not from pixel 0,0 1 = Pixel_Grab data is from pixel 0,0 OVF Motion overfl ow, Y and/or X buff er has overfl owed since last report 0 = no overfl ow 1 = Overfl ow has occurred GPIO Reports GPIO status (read only) 0 = low 1 = high
Delta_X Address: 0x03 Access: Read Reset Value: Any Bit 7 6 5 4 3 2 1 0 Field Y7 Y 6 Y5 Y 4 Y 3 Y2 Y1 Y0 Data Type: Eight bit 2’s complement number. USAGE: X movement is counts since last report. Absolute value is determined by resolution. Reading clears the register. Delta_Y Address: 0x04 Access: Read Reset Value: Any Bit 7 6 5 4 3 2 1 0 Field X7 X 6 X5 X 4 X 3 X2 X1 X0 Data Type: Eight bit 2’s complement number. USAGE: Y movement is counts since last report. Absolute value is determined by resolution. Reading clears the register. 00 01 02 7E 7FFFFE81Delta_X +127+126-1-2-127Motion +1 +20 Delta X ORIENT PIN HIGH Maximum +127 Minimum -127 ORIENT PIN LOW Maximum +127 Minimum -127 NOTES: Avago RECOMMENDS that registers 0x03 and 0x04 be read sequentially. 00 01 02 7E 7FFFFE81Delta_X +127+126-1-2-127Motion +1 +20 Delta Y ORIENT PIN HIGH Maximum +127 Minimum -127 ORIENT PIN LOW Maximum +127 Minimum -128 NOTES: Avago RECOMMENDS that registers 0x03 and 0x04 be read sequentially.
SQUAL Address: 0x05 Access: Read Reset Value: Any Bit 7 6 5 4 3 2 1 0 Field SQ7 SQ 6 SQ5 SQ 4 SQ 3 SQ2 SQ1 SQ0 Data Type: Upper 8 bits of a 9-bit unsigned integer. USAGE: SQUAL (Surface Quality) is a measure of the number of valid features visible by the sensor in the current frame. The maximum SQUAL register value is 167. Since small changes in the current frame can result in changes in SQUAL, variations in SQUAL when looking at a surface are expected. Shutter_Upper Address: 0x06 Access: Read Reset Value: Any Bit 7 6 5 4 3 2 1 0 Field S15 S14 S13 S12 S 11 S10 S9 S8 Shutter_Lower Address: 0x07 Access: Read Reset Value: Undefi ned Bit 7 6 5 4 3 2 1 0 Field S7 S 6 S5 S 4 S 3 S2 S1 S0 Data Type: Sixteen bit unsigned integer. USAGE: Units are clock cycles. Read Shutter_Upper fi rst, then Shutter_Lower. They should be read consecutively. The shutter is adjusted to keep the average and maximum pixel values within normal operating ranges. The shutter value is automatically adjusted. Maximum_Pixel Address: 0x08 Access: Read Reset Value: Any Bit 7 6 5 4 3 2 1 0 Field MP7 MP 6 MP5 MP 4 MP 3 MP2 MP1 MP0 Data Type: Eight-bit number. USAGE: Maximum Pixel value in current frame. Minimum value = 0, maximum value = 254. The maximum pixel value can vary with every frame.
Pixel_Sum Address: 0x09 Access: Read Reset Value: Any Bit 7 6 5 4 3 2 1 0 Field AP7 AP 6 AP5 AP 4 AP 3 AP2 AP1 AP0 Data Type: High 8 bits of an unsigned 17-bit integer. USAGE: This register is used to fi nd the average pixel value. It reports the seven bits of a 16-bit counter, which sums all pixels in the current frame. It may be described as the full sum divided by 512. To fi nd the average pixel value, use the following formula: Average Pixel = Register Value * 128/121 = Register Value * 1.06 The maximum register value is 240. The minimum is 0. The pixel sum value can change every frame. Minimum_Pixel Address: 0x0a Access: Read Reset Value: Any Bit 7 6 5 4 3 2 1 0 Field MP7 MP 6 MP5 MP 4 MP 3 MP2 MP1 MP0 Data Type: Eight-bit number. USAGE: Minimum Pixel value in current frame. Minimum value = 0, maximum value = 254. The minimum pixel value can vary with every frame. Pixel_Grab Address: 0x0b Access: Read/Write Reset Value: Any Bit 7 6 5 4 3 2 1 0 Field PD7 PD 6 PD5 PD 4 PD 3 PD2 PD1 PD0 Data Type: Eight-bit word. USAGE: For test purposes, the sensor will read out the contents of the pixel array, one pixel per frame. To start a pixel grab, write anything to this register to reset the pointer to pixel 0,0. Then read the PIXRDY bit in the Motion register. When the PIXRDY bit is set, there is valid data in this register to read out. After the data in this register is read, the pointer will automatically increment to the next pixel. Reading may continue indefi nitely; once a complete frame’s worth of pixels has been read, PIXFIRST will be set to high to indicate the start of the fi rst pixel and the address pointer will start at the beginning location again. The pixel map address and corresponding sensor orientation is shown below.
Figure 29. Top view of pixel map address without lens
Figure 30. Top view of pixel map address with lens
CRC2 Address: 0x0e Access: Read Reset Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field CRC27 CRC2 6 CRC25 CRC2 4 CRC2 3 CRC22 CRC21 CRC20 Data Type: Eight-bit number USAGE: Register 0x0e reports the third byte of the system self test results. See Self Test register 0x10. CRC3 Address: 0x0f Access: Read Reset Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field CRC37 CRC3 6 CRC35 CRC3 4 CRC3 3 CRC32 CRC31 CRC30 Data Type: Eight-bit number USAGE: Register 0x0f reports the fourth byte of the system self test results. See Self Test register 0x10. CRC0 Address: 0x0c Access: Read Reset Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field CRC07 CRC0 6 CRC05 CRC0 4 CRC0 3 CRC02 CRC01 CRC00 Data Type: Eight-bit number USAGE: Register 0x0c reports the fi rst byte of the system self test results. See Self Test register 0x10. CRC1 Address: 0x0d Access: Read Reset Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field CRC17 CRC1 6 CRC15 CRC1 4 CRC1 3 CRC12 CRC11 CRC10 Data Type: Eight-bit number USAGE: Register 0x0d reports the second byte of the system self test results. See Self Test register 0x10.
Self_Test Address: 0x10 Access: Write Reset Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field Reserved Reserved Reserved Reserved Reserved Reserved Reserved TESTEN Data Type: Bit fi eld USAGE: Set the TESTEN bit in register 0x10 to start the system self-test. The test takes 250ms. During this time, do not write or read through the SPI port. Results are available in the CRC0-3 registers. After self-test, reset the chip to start normal operation. The procedure to start self test is as follows:- 1. Write 0x5a to register 0x3a to initiate soft reset. Do not load OFN registers. 2. Write data 0xF6 to register 0x60. 3. Write data 0xAA to register 0x73. 4. Write data 0xC4 to register 0x63. 5. Write 0x01 to register 0x10 to initiate self test. 6. Wait 250ms. 7. Read from CRC0 from address 0x0c, CRC1 from address 0x0d, CRC2 from address 0x0e, CRC3 from address 0x0f. The results are as follows. CRC# Orient = 1 Orient = 0 CRC0 0x36 0x33 CRC1 0x72 0x8E CRC2 0x7F 0x24 CRC3 0xD6 0x6C Field Name Description TESTEN Enable System Self Test 0 = Disable 1 = Enable Confi guration_bits Address: 0x11 Access: Read/Write Reset Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field RES Reserved Reserved Reserved Reserved Reserved Reserved Reserved Data Type: Bit fi eld USAGE: Register 0x11 allows the user to change the confi guration of the sensor. The RES bit allows selection between 500 and 1000 cpi resolution. Field Name Description RES Sets resolution 0 = 500 1 = 1000
Reserved Address: 0x12-0x19 LED_Control Address: 0x1a Access: Read/Write Reset Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field Reserved Reserved Reserved Reserved Reserved LED2 LED1 LED0 Data Type: Bit fi eld USAGE: Register 0x1a allows the user to change the LED drive current of the sensor. Field Name Description LED2:0 0x00 = 13mA 0x03 = 40mA 0x05 = 9.6mA Reserved Address: 0x1b IO_Mode Address: 0x1c Access: Read/Write Reset Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field Reserved Reserved Reserved Burst Reserved SPI Reserved TWI Data Type: Bit fi eld USAGE: Register 0x1c allows the user to read the Input or Output mode of the sensor. Field Name Description Burst Burst mode 0 = not in burst mode 1 = In Burst mode SPI SPI mode 0 = not in SPI mode 1 = In SPI mode TWI TWI mode 0 = not in TWI mode 1 = In TWI mode
Motion_Control Address: 0x1d Access: Write Reset Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field Control Reserved Reserved Reserved Reserved Reserved Reserved Reserved Data Type: Bit fi eld USAGE: Register 0x1d allows the user to control and read the Motion pin state. Field Name Description Control Motion control pin 0 = set Motion pin active low. Motion pin will go low when motion is present. 1 = set Motion pin active high Reserved Address: 0x1e-0x2d Observation Address: 0x2e Access: Read/Write Reset Value: Any Bit 7 6 5 4 3 2 1 0 Field MODE1 MODE0 Reserved Reserved Reserved Reserved Reserved Reserved Data Type: Bit fi eld USAGE: Register 0x2e provides bits that are set every fr ame. It can be used during ESD testing to check that the chip is running correctly. Writing anything to this register will clear the bits. Field Name Description MODE1-0 Mode Status: Reports which mode the sensor is in. 00 = Run 01 = Rest1 10 = Rest2 11 = Rest3 Reserved Address: 0x2f-0x39 Soft_RESET Address: 0x3a Access: Write Reset Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field RST7 RST6 RST5 RST4 RST3 RST2 RST1 RST0 Data Type: 8-bit integer USAGE: Write 0x5A to this register to reset the chip. All settings will revert to default values.
Shutter_Max_Hi Address: 0x3b Access: Read/Write Reset Value: 0x0b Bit 7 6 5 4 3 2 1 0 Field SMH7 SMH6 SMH5 SMH4 SMH3 SMH2 SMH1 SMH0 Data Type: 8-Bit integer USAGE: This value is the upper 8-bit of shutter maximum open time. Shutter value represents pixel array exposure time in multiples of internal clock cycles with maximum value at 2929decimal. Shutter_Max_Lo Address: 0x3c Access: Read/Write Reset Value: 0x71 Bit 7 6 5 4 3 2 1 0 Field SML7 SML6 SML5 SML4 SML3 SML2 SML1 SML0 Data Type: 8-Bit integer USAGE: This value is the lower 8-bit of shutter maximum open time. Shutter value represents pixel array exposure time in multiples of internal clock cycles. Reserved Address: 0x3d Inverse_Revision_ID Address: 0x3e Access: Read Reset Value: 0xFE Bit 7 6 5 4 3 2 1 0 Field NRID7 NRID6 NRID5 NRID4 NRID3 NRID2 NRID1 NRID0 Data Type: Inverse 8-Bit unsigned integer USAGE: This value is the inverse of the Revision_ID. It can be used to test the SPI port. Inverse_Product_ID Address: 0x3f Access: Read Reset Value: 0x7C Bit 7 6 5 4 3 2 1 0 Field NPID7 NPID6 NPID5 NPID4 NPID3 NPID2 NPID1 NPID0 Data Type: Inverse 8-Bit unsigned integer USAGE: This value is the inverse of the Product_ID. It can be used to test the SPI port.
Reserved Address: 0x40-0x5f OFN_Engine Address: 0x60 Access: Read/Write Reset Value: 0x00 Bit 7 6 5 4 3 2 1 0 Field Engine Speed Assert/ Deassert XYQ Reserved Finger XY_Scale Reserved Data Type: Bit fi eld USAGE: This register is used to set several properties of the sensor. Field Name Description Engine Sets optical fi nger navigation properties. 0 = Disable properties 1 = Enable properties Speed Sets speed switching 0 = Disable speed switching 1 = Enable speed switching Assert/Deassert Sets Assert/Deassert mode 0 = Disable Assert/Deassert 1 = Enable Assert/Deassert XY Q Sets XY quantization 0 = Disable quantization 1 = Enable quantization Finger Sets fi nger presence detection 0 = Disable fi nger presence detection 1 = Enable fi nger presence detection XY_Scale Sets scaling factor for XY 0 = Disable scaling 1 = Enable scaling
Reserved Address: 0x61 OFN_Resolution Address: 0x62 Access: Read/Write Reset Value: 0x1a Bit 7 6 5 4 3 2 1 0 Field Reserved Reserved WakeRES 2 WakeRES1 WakeRES0 RES2 RES1 RES0 Data Type: Bit fi eld USAGE: This register is used to set several properties of the sensor. Field Name Description WakeRES2:0 Sets resolution when sensor wakes up from rest modes. Eff ective is speed switching is enabled. 0x01 : 250cpi 0x02 : 500cpi 0x03 : 750cpi 0x04 : 1000cpi 0x05 : 1250cpi RES2:0 Reads resolution of sensor 0x01 : 250cpi 0x02 : 500cpi 0x03 : 750cpi 0x04 : 1000cpi 0x05 : 1250cpi
OFN_Speed_Control Address: 0x63 Access: Read/Write Reset Value: 0x04 Bit 7 6 5 4 3 2 1 0 Field Y_scale X_scale Reserved Reserved SP_IntVal1 SP_IntVal0 Low_cpi Hi_cpi Data Type: Bit fi eld USAGE: This register is used to set several properties of the sensor. Field Name Description Y_scale Sets scaling factor for Y axis 0 = Disable 1 = Enable scale of Y * 2 X_scale Sets scaling factor for X axis 0 = Disable 1 = Enable scale of X * 2 SPIntVal 1:0 Speed switching checking interval 0x00: 4ms 0x01: 8ms (default) 0x02: 12ms 0x03: 16ms Low_cpi Sets low cpi when in speed switching mode 0 = Disable 1 = Enable 250cpi Hi_cpi Sets high cpi when in speed switching mode 0 = Disable 1 = Enable 1250cpi OFN_Speed_ST12 Address: 0x64 Access: Read/Write Reset Value: 0x08 Bit 7 6 5 4 3 2 1 0 Field ST ST ST ST ST ST ST ST Data Type: Bit fi eld USAGE: This register is used to set several speed switching properties of the sensor. Field Name Description ST 7:0 Sets resolution switching from step 1 to 2. Write in hexadecimal value. Formula (in decimal) = Velocity (inch per second) * 8
OFN_Speed_ST21 Address: 0x65 Access: Read/Write Reset Value: 0x06 Bit 7 6 5 4 3 2 1 0 Field ST ST ST ST ST ST ST ST Data Type: Bit fi eld USAGE: This register is used to set several speed switching properties of the sensor. Field Name Description ST 7:0 Sets resolution switching from step 2 to 1. Write in hexadecimal value. Formula (in decimal) = Velocity (inch per second) * 8 OFN_Speed_ST23 Address: 0x66 Access: Read/Write Reset Value: 0x40 Bit 7 6 5 4 3 2 1 0 Field ST ST ST ST ST ST ST ST Data Type: Bit fi eld USAGE: This register is used to set several speed switching properties of the sensor. Field Name Description ST 7:0 Sets resolution switching from step 2 to 3. Write in hexadecimal value. Formula (in decimal) = Velocity (inch per second) * 8 OFN_Speed_ST32 Address: 0x67 Access: Read/Write Reset Value: 0x08 Bit 7 6 5 4 3 2 1 0 Field ST ST ST ST ST ST ST ST Data Type: Bit fi eld USAGE: This register is used to set several speed switching properties of the sensor. Field Name Description ST 7:0 Sets resolution switching from step 3 to 2. Write in hexadecimal value. Formula (in decimal) = Velocity (inch per second) * 8
OFN_Speed_ST34 Address: 0x68 Access: Read/Write Reset Value: 0x48 Bit 7 6 5 4 3 2 1 0 Field ST ST ST ST ST ST ST ST Data Type: Bit fi eld USAGE: This register is used to set several speed switching properties of the sensor. Field Name Description ST 7:0 Sets resolution switching from step 3 to 4. Write in hexadecimal value. Formula (in decimal) = Velocity (inch per second) * 8 OFN_Speed_ST43 Address: 0x69 Access: Read/Write Reset Value: 0x0a Bit 7 6 5 4 3 2 1 0 Field ST ST ST ST ST ST ST ST Data Type: Bit fi eld USAGE: This register is used to set several speed switching properties of the sensor. Field Name Description ST 7:0 Sets resolution switching from step 4 to 3. Write in hexadecimal value. Formula (in decimal) = Velocity (inch per second) * 8 OFN_Speed_ST45 Address: 0x6a Access: Read/Write Reset Value: 0x50 Bit 7 6 5 4 3 2 1 0 Field ST ST ST ST ST ST ST ST Data Type: Bit fi eld USAGE: This register is used to set several speed switching properties of the sensor. Field Name Description ST 7:0 Sets resolution switching from step 4 to 5. Write in hexadecimal value. Formula (in decimal) = Velocity (inch per second) * 8
OFN_Speed_ST54 Address: 0x6b Access: Read/Write Reset Value: 0x48 Bit 7 6 5 4 3 2 1 0 Field ST ST ST ST ST ST ST ST Data Type: Bit fi eld USAGE: This register is used to set several speed switching properties of the sensor. Field Name Description ST 7:0 Sets resolution switching from step 5 to 4. Write in hexadecimal value. Formula (in decimal) = Velocity (inch per second) * 8 Reserved Address: 0x6c OFN_AD_CTRL Address: 0x6d Access: Read/Write Reset Value: 0xc4 Bit 7 6 5 4 3 2 1 0 Field 1 1 Reserved Reserved Reserved ST_HIGH 2 ST_HIGH1 ST_HIGH0 Data Type: Bit fi eld USAGE: This register is used to set Assert De-assert control. Must write 1 to bit 7 and 6. Field Name Description ST_HIGH2:0 0x01 = lowest cpi setting (if lowest resolution is on then is 250cpi or else 500cpi) 0x02 = low cpi setting 0x03 = middle cpi setting 0x04 = higher cpi setting (default) 0x05 = highest cpi seting (if highest resolution is on then is 1250cpi or else 1000cpi) OFN_AD_ATH_HIGH Address: 0x6e Access: Read/Write Reset Value: 0x34 Bit 7 6 5 4 3 2 1 0 Field ATH_H ATH_H ATH_H ATH_H ATH_H ATH_H ATH_H ATH_H Data Type: Bit fi eld USAGE: This register is used to set HIGH speed Assert shutter threshold. Field Name Description ATH_H 7:0 Sets HIGH speed assert threshold. Write in hexadecimal value. Formula (in decimal) = Shutter value / 8. It is recommended to have hysteresis of 60 to 100 between assert and de-assert threshold.
OFN_AD_DTH_HIGH Address: 0x6f Access: Read/Write Reset Value: 0x3c Bit 7 6 5 4 3 2 1 0 Field DTH_H DTH_H DTH_H DTH_H DTH_H DTH_H DTH_H DTH_H Data Type: Bit fi eld USAGE: This register is used to set HIGH speed De-assert shutter threshold. Field Name Description DTH_H 7:0 Sets HIGH speed de-assert threshold. Write in hexadecimal value. Formula (in decimal) = Shutter value / 8. It is recommended to have hysteresis of 60 to 100 between assert and de-assert threshold. OFN_AD_ATH_LOW Address: 0x70 Access: Read/Write Reset Value: 0x18 Bit 7 6 5 4 3 2 1 0 Field ATH_L ATH_L ATH_L ATH_L ATH_L ATH_L ATH_L ATH_L Data Type: Bit fi eld USAGE: This register is used to set LOW speed Assert shutter threshold. Field Name Description ATH_L 7:0 Sets LOW speed assert threshold. Write in hexadecimal value. Formula (in decimal) = Shutter value / 8. It is recommended to have hysteresis of 60 to 100 between assert and de-assert threshold. OFN_AD_DTH_LOW Address: 0x71 Access: Read/Write Reset Value: 0x20 Bit 7 6 5 4 3 2 1 0 Field DTH_L DTH_L DTH_L DTH_L DTH_L DTH_L DTH_L DTH_L Data Type: Bit fi eld USAGE: This register is used to set LOW speed De-assert shutter threshold. Field Name Description DTH_L 7:0 Sets LOW speed de-assert threshold. Write in hexadecimal value. Formula (in decimal) = Shutter value / 8. It is recommended to have hysteresis of 60 to 100 between assert and de-assert threshold.
Reserved Address: 0x72 OFN_QUANTIZE_CTRL Address: 0x73 Access: Read/Write Reset Value: 0x99 Bit 7 6 5 4 3 2 1 0 Field YQ_ON YQ_DIV 6 YQ_DIV5 YQ_DIV4 XQ_ON XQ_DIV 2 XQ_DIV1 XQ_DIV0 Data Type: Bit fi eld USAGE: This register is used to set quatization for D eltaX and DeltaY. If both X and Y quantization modes are on, then only largest quantized X or Y will be reported. Field Name Description YQ_ON 0 = Y quantization off 1 = Y quantization On YQ_DIV6:4 Quantization factor 2YQ_DIV . Reported YQ = DY / 2YQ_DIV . XQ_ON 0 = X quantization off 1 = X quantization On XQ_DIV2:0 Quantization factor 2XQ_DIV . Reported XQ = DX / 2XQ_DIV . OFN_XYQ_THRESH Address: 0x74 Access: Read/Write Reset Value: 0x02 Bit 7 6 5 4 3 2 1 0 Field Reserved Reserved Reserved Reserved Reserved XYQ_M XYQ_C 1 XYQ_C0 Data Type: Bit fi eld USAGE: This register is used to set quatization gradient for DeltaX and DeltaY. Field Name Description XYQ_M Gradient of linear region 0 = Gradient 1 1 = Gradient 2 XYQ_C 1:0 Indicates the off set of linear region (max of C = 3 or 0x03)
OFN_FPD_CTRL Address: 0x75 Access: Read/Write Reset Value: 0x50 Bit 7 6 5 4 3 2 1 0 Field Reserved FPD_POL FPD_TH FPD_TH FPD_TH FPD_TH FPD_TH FPD_TH Data Type: Bit fi eld USAGE: This register is used to set fi nger presence detection control. Field Name Description FPD_POL 0 = GPIO is active LOW 1 = GPIO is active HIGH (default) FPD_TH5:0 Sets FPD threshold based on shutter value. Write in hexadecimal value. Formula (in decimal):- Shutter value / 32. Reserved Address: 0x76 OFN_ORIENTATION_CTRL Address: 0x77 Access: Read/Write Reset Value: 0x01 Bit 7 6 5 4 3 2 1 0 Field XY_SWAP Y_INV X_INV Reserved Reserved Reserved ORIENT 1 ORIENT0 Data Type: Bit fi eld USAGE: This register is used to set sensor orientation control after ORIENT pin is set. Field Name Description XY_SWAP 0 = Normal sensor reporting of DX, DY. (default) 1 = Swap data of DX to DY and DY to DX. Y_INV 0 = Normal sensor reporting of DY. (default) 1 = Invert data of DY only. X_INV 0 = Normal sensor reporting of DX. (default) 1 = Invert data of DX only. ORIENT1:0 Read only bits of Orient pin state 0x00 = mounted 90deg clockwise (Orient pin is low) 0x01 = mounted 0deg (default, Orient pin is high, Figure 27)
Packaging tape, reel and packing information. PS 21121110987 203546 6PS PS6 CPN 16MM MPN Detail "X" RECYCLE LOGO SEE DETAIL "X" R20.0±0.5 Ø13.0±0.5(3x) Ø100.0±0.5 Ø329.0±1.0 15.9-19.4** 22.4 MAX.* SLOT 7.0±0.5(3x) 16.4 +2.0* 0.0 16.0mm HEIGHT x MIN. 0.4mm THICK. EMBOSSED LETTERING EMBOSSED LINE (2x) 89.0mm LENGTH LINES 147.0mm AWAY FROM CENTER POINT 7.5mm HEIGHT EMBOSSED LETTERING DATE CODE ESD LOGO Ø16.0 7.5mm HEIGHT EMBOSSED LETTERING HUB Ø100.0±0.5 Ø329.0±1.0 20.2(MIN.) 1.5(MIN.) Ø13.0 0.2 +0.5 BACK VIEW FRONT VIEW 8 7 6 5 Notes:- 1. * – Measured at hub area. 2. ** – Measured at outer edge. 3. Flange and hub ultrasonic welded. Internal Control ø13.0±0.2 for ON Semi only. NO. COLOUR SURFACE RESISTIVITY 1. PANTONE 285U DARK BLUE ANTISTATIC COATED 106 – 1011 PER OHMS SQUARE 2. BLACK CONDUCTIVE <10 6 PER OHMS SQUARE 3. WHITE ANTISTATIC COATED 106 – 1011 PER OHMS SQUARE 4. PANTONE 3295C DARK GREEN ANTISTATIC COATED 106 – 1011 PER OHMS SQUARE 5. BLACK ANTISTATIC COATED 106 – 1011 PER OHMS SQUARE 6. PANTONE 278c LIGHT BLUE ANTISTATIC COATED 106 – 1011 PER OHMS SQUARE 7. WHITE ANTISTATIC COATED 106 – 1011 PER OHMS SQUARE 8. NATURAL ANTISTATIC COATED 106 – 1011 PER OHMS SQUARE 9. PANTONE 186C DARK RED ANTISTATIC COATED 106 – 1011 PER OHMS SQUARE Note: X in Part Numbering denotes colour code.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved. AV02-1859EN - November 16, 2011 Reel information Notes:- 1. Ao & Bo measured at 0.3mm above base of pocket. 2. 10 pitches cumulative tol. ±0.2mm. 3. ( ) Reference dimensions only. Ao: 6.4 Bo: 6.40 Ko: 2.25 Pitch: 8.00 Width: 16.00