AD7322

AD7322 ATMEL | Alldatasheet

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Software Selectable True Bipolar Input, 2-Channel, 12-Bit Plus Sign ADC Preliminary Technical Data AD7322*

FEATURES

• 12-Bit Plus Sign SAR ADC
• True Bipolar Analog Inputs
• Software Selectable Input Ranges ± 10V, ± 5V, ± 2.5V, 0 to 10V
• Two Analog Inputs with Channel Sequencer
• Single Ended, True Differential and Pseudo Differential Capability.
• High Analog Input Impedance
• Low Power:- 6 mW
• Full Power Signal Bandwidth: >13 MHz
• Internal 2.5 V Reference
• High Speed Serial Interface
• Power Down Modes
• 14-Lead TSSOP
• For 8 and 4 channel equivalent devices see AD7328 and AD7324 respectively. GENERAL DESCRIPTION The AD7322 is a 2-Channel, 12-Bit Plus Sign, 1 MSPS Successive Approximation ADC. The ADC has a high speed serial interface that can operate at throughput rates up to 1 MSPS. The AD7322 can handle True Bipolar Analog input signals. The Bipolar ranges are software selectable by programming the on board Range Register. Bipolar input ranges include ± 10V, ± 5V, ± 2.5V. The AD7322 can also handle a 0 to 10 V uniploar input range, which is also software selectable. Each analog input channel can be independently programmed to one of the input ranges by setting the appropriate bits in the Range Register. The Analog Input Channels can be configured as Single-Ended, Fully Differential or Pseudo Differential. Dedicated Control Register bits are used to configure the Analog inputs. The AD7322 contains a Channel Sequencer, allowing automatic conversions between each analog input channel. The ADC contains a 2.5V Internal reference. The AD7322 also allows for external Reference operation. If a 3V external reference is applied to the REFIN/OUT pin, the ADC can handle a True Bipolar ± 12 V Analog input range. Minimum VDD and VSS supplies of ± 12V are required for this ± 12 V input range. * Patent Pending FUNCTIONAL BLOCK DIAGRAM Figure 1. The Serial clock frequency, SCLK, applied to the ADC will determine the maximum throughput rate the ADC can operate at. The SCLK signal is used as the conversion clock and also to transfer data to and from the ADC. The Serial interface is SPITM, QSPITM, MICROWIRETM and DSP compatible. The AD7322 offers power down modes to reduce the power consumption of the ADC at lower throughput rates. PRODUCT HIGHLIGHTS 1. The AD7322 can accept True Bipolar Analog Input signals, ±10V, ±5V, ±2.5V and 0 to 10V unipolar signals. 2. The Two Analog Inputs can be configured as Two Single- Ended inputs, One True Differential or One Pseudo Differential Input. The AD7322 has high Impedance Analog Inputs. 3. The AD7322 features a High Speed Serial Interface. Throughput Rates up to 1 MSPS can be achieved on the AD7322. 4. Low Power, 12 mW at maximum throughput rate of 1 MSPS. Information furn ished by An alog D evices is believed to be accurate and reliable. However, n o resp onsibility is assume d b y A nalog De vices fo r its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or p atent rights of Analog De vices. Trademarks an d registered trademarks are the property of their respective companies. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. Rev. PrE

AD7322 Preliminary Technical Data TABLE OF CONTENTS

REVISION HISTORY

Revision PrE: Preliminary Version Rev. PrE | Page 2 of 18

AD7322 Preliminary Technical Data Parameter Specification Units Test Conditions/Comments Reference Output Impedance 25 Ω typ LOGIC INPUTS Input High Voltage, VINH 0.7*VDRIVE V min Input High Voltage, VINL 0.3*VDRIVE V max Input Current, IIN ± 1 µA max VIN = 0V or VCC Input Capacitance, CIN3 10 pF max LOGIC OUTPUTS Output High Voltage, VOH VDRIVE- 0.2V V min ISOURCE = 200 µA Output Low Voltage, VOL 0.4 V max ISINK = 200 µA Floating State Leakage Current ±1 µA max Floating State Output Capacitance3 10 pF max Output Coding Straight Natural Binary Coding bit set to 1 in Control Register Two’s Complement Coding bit set to 0 in Control Register CONVERSION RATE Conversion Time 800 ns max 16 SCLK Cycles with SCLK = 20 MHz Track-and-Hold Acquisition Time 150 ns max Sine Wave Input 150 ns max Full Scale Step input Throughput Rate 1 MSPS max See Serial Interface section POWER REQUIREMENTS Digital Inputs = 0V or VCC VDD 4.75V/+16.5V V min/max See VSS -4.75V/16.5V V min/max See VCC 2.7V / 5.25V V min/max See Normal Mode IDD 200 µA max ISS 200 µA max ICC 2 mA max Auto-Standby Mode FSAMPLE = TBD IDD TBD µA max ISS TBD µA max ICC 1.6 mA typ Auto-Standby Mode FSAMPLE = TBD IDD TBD µA max ISS TBD µA max ICC 1 mA typ Full Shutdown Mode IDD TBD µA max ISS TBD µA max ICC 1 µA max SCLK On or Off POWER DISSIPATION Normal Mode 12 mW max VDD = +5V, VSS = -5V, VCC = 5V, Table 5 Table 5 Table 5 NOTES

1 Temperature ranges as follows: -40°C to +85°C

2 See Terminology

3 Guaranteed by Characterization

Specifications subject to change without notice. Rev. PrE | Page 4 of 18

20 MHz max

t4 TBD ns max Data Access Time after SCLK Falling Edge. Figure 2. Serial Interface timing Diagram

Table 3. TA = 25°C, unless otherwise noted

AD7322 Preliminary Technical Data Pin Functional Descriptions TOP VIEW (Not to Scale) 8 AD7322 /X43/X53 DIN SCLK REFIN/OUT VSS DGND DOUT VIN1 VDRIVE VIN0 AGND DGND VDD /X56/X43/X43 Figure 3. AD7322 Pin Configuration TSSOP Table 4. AD7324 Pin Function Descriptions

Description

SCLK 14 Serial Clock. Logic Input. A serial clock input provides the SCLK used for accessing the data from the AD7322. This clock is also used as the clock source for the conversion process. DOUT 12 Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input and 16 SCLKs are required to access the data. The data stream consists of two leading zeros, one channel identification bit, a Sign bit followed by 12 bits of conversion data. The data is provided MSB first. See the Serial Interface section. CS 1 Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7322 and frames the serial data transfer. DIN 2 Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the register on the falling edge of SCLK. See Register section. AGND 4 Analog Ground. Ground reference point for all analog circuitry on the AD7322. All analog input signals and any external reference signal should be referred to this AGND voltage. REF IN/REFOUT 5 Reference Input/ Reference Output pin. When enabled the on-chip reference is available on this pin for use external to the AD7322. Alternativley, the internal reference can be disabled and an external reference applied to this input. When using the AD7322 with an external reference, the internal reference must be disabled via the control register. The nominal reference voltage is 2.5 V, which appears at the pin. The default on power up is for external Reference operation. See . VCC 10 Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7322. This supply should be decoupled to AGND. VDD 9 Positive power supply voltage. This is the positive supply voltage for the Analog Input section. VSS 6 Negative power supply voltage. This is the negavtive supply voltage for the Analog Input section. DGND 3,13 This is the Digital Ground pin. VDRIVE 11 Logic Power Supply input. The voltage applied to this pin determines the operating voltge of the sertial inteface. Vin0-Vin1 7,8 Analog input 0 through Analog Input 1. The analog inputs are multiplexed into the on-chip track-and-hold. The analog input channel for conversion is selected by programming the channel address bit ADD0, in the control register. The inputs can be configured as 2 Single- Ended Inputs, 1 True Differential Input pair, 1 Pseudo Differential inputs. The configuration of the Analog inputs is selected by programming the Mode bits, Mode1 and Mode0, in the Control Register. The input range on each input channel is controlled by programming the range register. Inputs ranges of ±10V, ±5V, ±2.5V and 0 to 10V can be selected on each analog input channel. See Register section. Table 8 Rev. PrE | Page 7 of 18

AD7322 Preliminary Technical Data TERMINOLOGY Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition. Offset Code Error This applies to Straight Binary output coding. It is the deviation ideal, i.e., AGND + 1 LSB. Offset Error Match This is the difference in Offset Error between any two input channels. Gain Error This applies to Straight Binary output coding. It is the deviation ideal (i.e., 4 x VRef – 1 LSB, 2 x VREF –1 LSB, VREF –1 LSB) after the offset error has been adjusted out. Gain Error Match This is the difference in Gain Error between any two input channels channels. Bipolar Zero Code Error This applies when using twos complement output coding and a bipolar Analog Input. It is the deviation of the midscale transition (all 1s to all 0s) from the ideal VIN voltage, i.e., AGND - 1 LSB. Bipolar Zero Code Error Match This refers to the difference in Bipolar Zero Code Error between any two input channels. Positive Full Scale Error This applies when using twos complement output coding and any of the bipolar Analog Input ranges. It is the deviation of the last code transition (011…110) to (011…111) from the ideal ( +4 x VREF - 1 LSB, + 2 x VREF – 1 LSB, + VREF – 1 LSB) after the bipolar Zero Code Error has been adjusted out. Positive Full Scale Error Match This is the difference in Positive Full Scale error between any two input channels. Negative Full Scale Error This applies when using twos complement output coding and any of the bipolar Analog Input ranges. This is the deviation of the first code transition (10…000) to (10…001) from the ideal (i.e., - 4 x VREF + 1 LSB, - 2 x VREF + 1 LSB, - VREF + 1 LSB) after the Bipolar Zero Code Error has been adjusted out. Negative Full Scale Error Match This is the difference in Negative Full Scale error between any two input channels. Track-and-Hold Acquisition Time The track-and-hold amplifier returns into track mode after the fifteenth SCLK falling edge. Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1/2 LSB, after the end of conversion. Signal to (Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all non-fundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02N + 1.76) dB Thus for a 13-bit converter, this is 80.02 dB. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7322 it is defined as: 2log20)( V VVVVVdBTHD ++++= where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak. Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between any two channels. It is measured by applying a full-scale, 400 kHz sine wave signal to all unselected input channels and determining how much that signal is attenuated in Rev. PrE | Page 8 of 18

The AD7322 has two-programmable registers, the Control Register and the Range Register. These registers are write only registers. Table 7. Decoding Register Select bit and Write bit. Table 8. Control Register Single Ended Inputs, 1 Fully Differential Input, 1 Pseudo Differential input. See . written to the coding bit during the last write to the Control Register.

14,12,11,1 ZERO A zero must be written to this bit to ensure correct operation of the AD7322. Table 9. Analog Input Configuration Selection

1 Pseudo Differential I/p 1Fully Differential i/p Not Allowed Two-Single Ended i/ps

0 Vin0 Vin1 Vin0 Vin1 Vin0 AGND

1 Vin0 Vin1 Vin0 Vin1 Vin1 AGND

Table 10. Power Mode Selection retained when the AD7322 is in Full Shutdown Mode. the control register is updated. 0 0 Normal Mode, All internal Circuitry is powered up at all times. Table 11. Sequencer Selection Control Register selects the next channel for conversion. sequence until the Seq bits are changed in the Control Register. Control Register selects the next channel for conversion.

each time any one of these analog input channels is selected. The ±10V input Range is selected by default on each analog input channel. Table 12. Range Register Input Range on Analog Input X. Input Range on Analog Input X. Input Range on Analog Input X.

AD7322 Preliminary Technical Data REFERENCE The AD7322 can operate with either the internal 2.5V on-chip reference or an externally applied reference. The internal reference is selected by setting the REF bit in the Control Register to 1. On power up the REF bit will be 0, selecting the external Reference for the AD7322 conversion. For external reference operation the REFIN/REFOUT pin should be decoupled to AGND with a 470 nF capacitor. The internal Reference circuitry consists of a 2.5V band gap reference and a reference buffer. When operating the AD7322 in internal Reference mode the 2.5V internal reference is available at the REFIN/REFOUT pin. When using the AD7322 with the internal reference the REFIN/REFOUT pin should be decoupled to AGND using a 0.47 µF cap. It is recommended that the Internal Reference be buffered before applying it else where in the system. The AD7322 is specified for a 2.5V to 3V reference range. When a 3V reference is selected the ranges will be, ±12V, ±6V, ±3V and 0 to 12V. For these ranges the VDD and VSS supply must be equal to or greater than the max Analog Input Range selected. On power up if the internal reference operation is required for the ADC conversion, a write to the control register is necessary to set the REF bit to 1. During the Control Register write the conversion result from the first initial conversion will be invalid. The reference buffer will require TBD us to power up and charge the 0.47 µF decoupling cap, during the power up time the conversion result from the ADC will be invalid. Rev. PrE | Page 15 of 18

Figure 14. Serial Interface timing Diagram (Control register write) information to and from the AD7322 during a conversion. it will require 16 SCLK cycles to complete.

16 SCLK cycles have elapsed, the conversion will be terminated,

addressed register on the 11th SCLK falling edge. which channel the conversion result corresponds to.

AD7322 Preliminary Technical Data OUTLINE DIMENSIONS 14-Lead Thin Shrink Small Outline (TSSOP) (RU-14) Ordering Guide AD7322 Products Temperature Package Package Description Package Outline AD7322BRU –40°C to +85°C TSSOP RU-14 EVAL-AD7322CB1 Evaluation Board EVAL-CONTROL BRD22 Controller Board NOTES 1 This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL Board for evaluation/demonstration purposes. 2 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete evaluation kit, the particular ADC evaluation board, e.g., EVAL-AD7322CB, the EVAL-CONTROL BRD2, and a 12V transformer must be ordered. See relevant Evaluation Board Technical note for more information. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrE | Page 18 of 18