ACX306

ACX306AK SONY | Alldatasheet

Document overview

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• PDF pages: 23

Technical content

Features

• Number of active dots: 118,000, 3.86cm (1.5 Type) in diagonal
• Horizontal resolution: 240 TV lines
• Optical transmittance: 6.5% (typ.)
• High contrast ratio with normally white mode: 200 (typ.)
• Built-in H and V driving circuitry (built-in input level conversion circuit, 3V drive possible)
• Low voltage, low power consumption: 12V drive: 43mW (panel block, typ.)
• Smooth pictures with a RGB delta arrangement
• Supports NTSC/PAL
• Built-in picture quality improvement circuit
• Up/down and/or right/left inverse display function
• LR (low reflectance) surface treatment provides an easy-to-see display even outdoors
• Dirt-resistant surface treatment
• Narrow frame Element Structure
• Active matrix TFT-LCD panel with built-in peripheral driving circuitry using low temperature polycrystalline silicon transistors
• Number of pixels Total number of dots: 494 (H) Number of active dots: 490 (H) · 240 (V) = 117,600
• Module dimensions Package dimensions: 38 (W) · 32.6 (D) · 2.2 (H) (mm) Effective display dimensions: 31.115 (H) · 30.360 (V) (mm)

Applications

LCD monitors, etc. – 1 – E00143-PS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 2 – ACX306AK Block Diagram The panel block diagram is shown below. TESTL TESTR COM VST VCK EN DW N V DD V SS VDDG VSSG TEST2 W IDE HST REF TEST Cext/Rext HCK2 HCK1 PSIG GREEN RED BLUE RGT Level Shifter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 V Shift Register H Level Shifter & Shift R egister LCC S C O M C om m on Voltage Boost, N egative Voltage G eneration C ircuit

– 3 – ACX306AK Absolute Maximum Ratings(Vss = 0V)

• H driver supply voltage VDD , Cext/Rext –1.0 to +17 V
• V driver boost supply voltageVDDG VDD – 1.0 to +18V
• V driver negative supply voltageVSSG –3.0 to +1.0 V
• Common voltage of panel COM –1.0 to +17 V
• H driver input pin voltage HST, HCK1, HCK2, RGT, WIDE –1.0 to +17 V
• V driver input pin voltage VST, VCK, EN, DWN, REF –1.0 to +15 V
• Video signal, uniformity improvement signal input pin voltage GREEN, RED, BLUE, PSIG –1.0 to +13 V
• Operating temperature Topr –10 to +60 °C
• Storage temperature Tstg –30 to +85 °C Operating Conditions of Panel Block 1. Input/output supply voltage conditions*1 (VSS = 0V) Item Supply voltage VDD Cext/Rext*2 VDDG VSSG Rext 11.4 V DD – 3.4 14.0 –2.3 12.0 12.0 15.0 –1.8 12.6 16.3 –1.5 160 V V V V kΩ VDDG output voltage setting VSSG output voltage setting* Resistor connected to Cext/Rext pin*2 Symbol Min. Typ. Max. Unit *1 The VDD typical voltage setting is noted as 12.0V in these specifications. *2 Connect the resistor and capacitor to the Cext/Rext pin as shown in the figure below. *3 For the VDDG, VSSG output setting, connect an external smoothing capacitor and a voltage stabilizing Zener diode as shown in the figure below. VD D – C ext/R ext C ext/R extVD D VD D 7Voltage Tim e text Set a C ext value that satisfies text > 1m s. The C ext/R ext value differs according to the rising tim e of the panel supply voltage. R ext AC X306AK VD D VSSG VSS C ext/R ext 1µF C ext 1µF VD D G R ecom m ended voltage applied exam ple Zener diode. (R D 4.3U M is recom m ended) R ecom m ended voltage applied exam ple Zener diode. (R D 2.7U M is recom m ended)

– 4 – ACX306AK Pin No. TESTL COM VST VCK EN DWN V DD VSS VDDG VSSG TEST2 WIDE HST REF TEST Cext/ Rext HCK2 HCK1 PSIG GREEN RED BLUE RGT TESTR Start pulse input for H shift register drive Level shifter circuit REF voltage input Panel test output; no connection Time constant power supply input for H shift register drive Clock input for H shift register drive Clock input for H shift register drive Uniformity improvement signal input Video signal (G) input to panel Video signal (R) input to panel Video signal (B) input to panel H shift register drive direction signal input Panel test output; no connection Symbol Description Pin No. Symbol Description Panel test output; no connection Common voltage input of panel Start pulse input for V shift register drive Clock input for V shift register drive Gate selection pulse enable input V shift register drive direction signal input Power supply input for V driver H and V driver GND Boost power supply setting for V driver Negative power supply setting for V driver No connection inside the panel. (with 1MΩ terminating resistor) Uniformity improvement signal control pulse input Pin Description of Panel Block 4 Input video and uniformity improvement signals should be input the voltage amplitude symmetrical to VVC as shown in Fig. 1. PSIG w aveform VVC Vpsig Fig. 1 Item H/V driver input voltage (Low) (High) VIL VIH VREF VVC Vsig Vpsig Vcom –0.3 2.6 VIH/2 – 0.3 5.8 1.0 VVC ± 2.3 VVC – 0.6 0.0 3.0 VIH/2 6.0 VVC ± 4.0 VVC ± 2.5 VVC – 0.5 0.3 5.5 VIH/2 + 0.3 6.2 VDDG – 4.0 (10.5V or less) VVC ± 2.7 VVC – 0.4 V V V V V V V REF input voltage Video signal center voltage* Video signal input range*4 Uniformity improvement signal*4 Common voltage of panel (Ta = 25°C) Symbol Min. Typ. Max. Unit 2. Panel input signal voltage conditions (VSS = 0V)

– 5 – ACX306AK Input Equivalent Circuits of Panel Block To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition, protective resistors are added to all pins except the video signal input pins. All pins are connected to V SS with a high resistance of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (Resistor value: typ.) (1) RED, GREEN, BLUE, PSIG VD D 1M Ω Input Signal line (2) HCK1, HCK2 1M Ω 1M Ω VD D VD D H C K1 H C K2 H level shifter and shift register circuit (3) WIDE, REF 1M Ω 350Ω 1M Ω 350Ω VD D VD D Input R EF Level conversion circuit (5) RGT, REF 1M Ω 2kΩ 1M Ω 2kΩ VD D VD D Input R EF Level conversion circuit (4) HST 1M Ω 175Ω 1M Ω 175Ω VD D VD D Input R EF Level conversion circuit

– 6 – ACX306AK (11) TEST, TEST2 VD D TEST 350Ω 1M Ω 350Ω TEST2 1M Ω (12) TESTL, TESTR TESTL TESTR 4M Ω VD D (7) DWN, REF 1M Ω 1M Ω VD D VD D 2kΩ2kΩ Input R EF Level conversion circuit (8) VDDG, VSSG VD D VD D G , VSSG Boost, N egative voltage generation circuit (9) COM 1M Ω Input LC (10) Cext/Rext VD D C ext/R ext H driver 1M Ω (6) VST, VCK, EN, REF 1M Ω 800Ω 1M Ω 800Ω VD D VD D Input R EF Level conversion circuit

– 7 – ACX306AK Clock Timing Conditions of Panel Block (VIH = 3.0V, VDD = 12V, Ta = 25°C) HST rise time HST fall time HST data setup time HST data hold time HCKn * 5 rise time HCKn *5 fall time HCK1 fall to HCK2 rise time HCK1 rise to HCK2 fall time VST rise time VST fall time VST data setup time VST data hold time VCK rise time VCK fall time EN rise time EN fall time EN fall to VCK rise/fall time EN pulse width WIDE rise time WIDE fall time WIDE (H) rise to VCK rise/fall time WIDE (H) pulse width trHst tfHst tdHst thHst trHckn tfHckn to1Hck to2Hck trVst tfVst tdVst thVst trVckn tfVckn trEn tfEn tdEn twEn trWide tfWide tdhWide twhWide 300 –30 –15 –15 –30 500 2900 –0.4 1.4 333 –32 600 3000 –0.5 1.5 363 100 100 –34 100 100 100 100 700 3100 100 100 –0.6 1.6 ns µs ns µs Item Symbol Min. Typ. Max. Unit HST HCK VST VCK EN WIDE 5 HCKn means HCK1 and HCK2. (fHCKn = 1.5MHz)

– 8 – ACX306AK Horizontal Standard Timing FR P VC K EN W ID E H C K2 H C K1 H ST 3.1µs 0.6µs 3.0µs 1.5µs 1.1µs 0.4µs

– 9 – ACX306AK *6 Definitions: The right-pointing arrow ( ) means +. The left-pointing arrow ( ) means –. The black dot at an arrow ( ) indicates the start of measurement 7 WIDE represents every 1H pulse as shown in Horizontal Timing. <Horizontal Shift Register Driving Waveforms> HST rise time HST HCK HST fall time HST data setup time HST data hold time HCKn *5 rise time HCKn *5 fall time HCK1 fall to HCK2 rise time HCK1 rise to HCK2 fall time

• HCKn *5 duty cycle 50% to1Hck = 0ns to2Hck = 0ns
• HCKn * 5 duty cycle 50% to1Hck = 0ns to2Hck = 0ns
• HCKn * 5 duty cycle 50% to1Hck = 0ns to2Hck = 0ns tdHst = 333ns thHst = 0ns
• tdHst = 333ns thHst = 0ns trHst tfHst tdHst thHst trHckn tfHckn to1Hck to2Hck Item Symbol Waveform Conditions 90% 90% 10% 10% H ST trH st tfH st 50% 50% 50% tdH st thH st H ST H C K1 50% H C Kn 90% 90% 10%10% trH ckn tfH ckn 50% 50% 50%50% H C K1 H C K2 to2H ck to1H ck WIDE WIDE rise time WIDE fall time trWide tfWide W ID E 90% 90% 10% 10% trW ide tfW ide WIDE rise to VCK rise/ fall time WIDE pulse width tdhWide twhWide VC K 50% W ID E 50% 50% tdhW ide tw hW ide

– 10 – ACX306AK Vertical Standard Timing FR P EN W ID E H ST VC K VST N TSC 4:3 (in case of EVEN field)

– 11 – ACX306AK EN rise time EN EN fall time EN fall to VCK rise/fall time EN pulse width trEn tfEn tdEn twEn 90% tfEn 10% EN 90% 10% trEn VC K 50% EN 50% 50% tdEn tw En

• VCK duty cycle 50% to1Vck = 0ns to2Vck = 0ns <Vertical Shift Register Driving Waveforms> VST rise time VST VCK VST fall time VST data setup time VST data hold time VCK rise time trVst tfVst tdVst thVst trVck VCK fall time tfVck Item Symbol Waveform Conditions 90%90% VST trVst tfVst 10%10% 50% 50% VST 50% VC K tdVst thVst 50% VC K 90% 90% 10%10% trVck tfVck
• VCK duty cycle 50% to1Vck = 0ns to2Vck = 0ns
• VCK duty cycle 50% to1Vck = 0ns to2Vck = 0ns
• VCK duty cycle 50% to1Vck = 0ns to2Vck = 0ns tdVst = 32µs thVst = –32µs

– 12 – ACX306AK Electrical Characteristics of Panel Block (Ta = 25°C, VDD = 12.0V, VIH = 3.0V, VREF = 1.5V) 1. Horizontal drivers Item HCKn input pin capacitance HST input pin capacitance Video signal input pin capacitance Psig input pin capacitance (4:3 display) Input pin currentHCK1 HCK2 HST RGT REF CHckn CHst Csig Cpsig I Hck1 I Hck2 I Hst I RGT I REF HCK1: actual driving HCK2: actual driving HST = GND RGT = GND REF = VIH/2 –600 –600 –200 –150 –900 120 5.2 –300 –300 –100 –50 –300 150 8.0 pF pF pF nF µA µA µA µA µA Symbol Min. Typ. Max. Unit Conditions 2. Vertical drivers Item VCK input pin capacitance VST input pin capacitance Input pin currentVCK VST EN DWN WIDE CVck CVst I Vck I Vst I En I DWN I WIDE –150 –150 –150 –150 –150 –50 –50 –50 –50 –50 pF pF µA µA µA µA µA Symbol Min. Typ. Max. Unit Conditions 3. Total power consumption of the panel Item Total power consumption of the panel (NTSC) (Ta = 25°C) (Ta = 60°C) PWR25 PWR60 mW mW Symbol Min. Typ. Max. Unit 4. Pin input resistance Item Pin – VSS input resistance 1 Rin1 0.5 1 — M Ω Symbol Min. Typ. Max. Unit VCK = GND VST = GND EN = GND DWN = GND WIDE = GND HCKn: HCK1, HCK2 (1.5MHz)

– 13 – ACX306AK Electro-optical Characteristics (Ta = 25°C, NTSC mode) *1 Conforms to the measurement results for the discrete panel. Item 25°C 60°C X Y X Y X Y 25°C 60°C 25°C 60°C 25°C 60°C R – G B – G 0°C 25°C 0°C 25°C 60°C 60°C CR ‡ 10 q = 0° 25°C R G B V V50 V10 ON time OFF time CR 25 CR 60 T Rx Ry Gx Gy Bx By V 90-25 V90-60 V50-25 V50-60 V10-25 V10-60 V50RG V50BG ton0 ton25 toff0 toff25 F YT1 qT qB qL qR Rf CTK 100 100 6.0 0.595 0.310 0.240 0.580 0.120 0.08 1.30 1.30 1.70 1.70 2.30 2.30 –0.115 200 180 6.5 0.625 0.340 0.270 0.610 0.150 0.110 1.50 1.50 1.90 1.90 2.50 2.50 –0.080 0.03 120 –60 0.9 0.9 0.655 0.370 0.300 0.640 0.180 0.140 1.70 1.70 2.10 2.10 2.70 2.70 –0.045 0.05 180 –30 rank C 1.5 1.5 CIE standards V V ms dB s Degree (°) Contrast ratio Panel transmittance*1 Chromaticity V-T characteristics*1 Half tone color reproduction range*1 Response time*1 Flicker*1 Image retention time*1 Viewing angle range Surface reflection ratio Cross talk*1 Symbol Measurement method Min. Typ. Max. Unit

– 14 – ACX306AK <Electro-optical Characteristics Measurement> Basic m easurem ent conditions (1) D riving voltage VD D = 12.0V, VIH = 3.0V, VR EF = 1.5V VVC = 6.0V, VC O M = 5.5V, Vpsig = 6.0 – 2.5V (2) M easurem ent tem perature 25°C unless otherw ise specified. (3) M easurem ent point O ne point in the center of the screen unless otherw ise specified. (4) M easurem ent system s Three types of m easurem ent system s are used as show n below . (5) R , G and B input signal voltage Vsig Vsig = 6.0 – VAC [V] (VAC : signal am plitude)

• M easurem ent system I
• M easurem ent system II
• M easurem ent system III Lum inance M eter M easurem ent Equipm entLight D etector M easure using the discrete LC D panel.D rive C irucuit Light Source O ptical fiber Light Source Spectroscope Surface A∗ Surface A∗ Surface A∗ LC D panel O ptical fiber Light receptor lens ∗ Surface A: See the Package O utline. E13585A U sing the Stanley E13585A inverter. U sing the TO PC O N BM -5A lum inance m eter. D C 6.0V Backlight 1. Contrast Ratio Contrast ratio (CR) is given by the following formula. CR = L (White)/L (Black) L (White): Surface luminance of the TFT-LCD panel at the input signal amplitude VAC = 0.5V. L (Black): Surface luminance of the panel at VAC = 4.0V. Both luminosities are measured by System I.

– 15 – ACX306AK 2. Optical Transmittance of Panel Optical transmittance (T) is given by the following formula. T = L (White)/Luminance of Backlight · 100 [%] 3. Chromaticity Chromaticity of the panels is measured by System I. Raster modes of each color are defined by the representations at the input signal amplitude conditions shown in the table below. System Iuses x and y of the CIE standards as the chromaticity here. 4. V-T Characteristics V-T characteristics, or the relationship between signal amplitude and the transmittance of the panel, are measured by System IIby inputting the same signal amplitude V AC to each input pin. V90, V50, and V10 correspond to the voltages which define 90%, 50%, and 10% of transmittance respectively. V10V50V90 VAC – Signal am plitude [V] Transm ittance [% 5. Half Tone Color Reproduction Range The half tone color reproduction range of LCD panels is characterized by the differences between the V-T characteristics of R, G and B. The differences of these V-T characteristics are measured by System II. System IIdefines signal voltages of each R, G and B raster mode which correspond to 50% of transmittance, V 50R , V50G and V50B, respectively. V50RG and V50BG , that is to say the differences between V50R and V50G and between V50B and V50G , are given by the following formulas respectively. V50RG = V50R – V50G V50BG = V50B – V50G Transm ittance [% V50R VAC – Signal am plitude [V] 100 V50B V50G V50R G V50BG G raster B rasterR raster R input G input B input Raster R G B 0.5 4.0 4.0 4.0 0.5 4.0 4.0 4.0 0.5 W 0.0 0.0 0.0 Signal amplitudes (VAC ) supplied to each input (Unit: V)

– 16 – ACX306AK 6. Response Time Response times ton and toff are measured by System II by applying the input signal voltages in the figure to the right to each input pin. These times are defined by the following formulas. ton = t1 – tON toff = t2 – tOFF t1: time which gives 10% transmittance of the panel. t2: time which gives 90% transmittance of the panel. The relationships between t1, t2, tON and tOFF are shown in the figure to the right. 4.0V 6.0V 0.5V O ptical transm ittance output w aveform 100% 90% 10% tO N t1 tO FF t2 ton toff Input signal voltage (W aveform applied to m easured pixels) 7. Flicker Flicker (F) is given by the following formula. DC and AC components (NTSC: 30Hz, rms; PAL: 25Hz, rms) of the panel output signal for gray raster* mode are measured by a DC voltmeter and a spectrum analyzer in System II. F [dB] = 20 log {AC component/DC component} * R, G, B input signal voltage for gray raster mode is given by Vsig = 6.0 ± V 50 [V] where: V50 is the signal amplitude which gives 50% of transmittance in V-T curve. 8. Image Retention Time Image retention time is given by the following procedures. Apply the monoscope pattern* to the LCD panel for 1 minute and then change to a gray scale signal (Vsig = 6.0 ± V AC [V]; VAC = 3 to 4V). Judging by sight at the VAC that holds the maximum image retention, measure the time for the residual image to disappear. * Monoscope pattern input conditions (shown in the figure to the right) Vcom = 5.5V 6.0V 4.0V 2.0V 4.0V 2.0V Black level W hite level Vsig w aveform

– 17 – ACX306AK 11. Cross Talk Cross talk is determined by the luminance differences between adjacent areas represented by Wi' and Wi (i = 1 to 4) around the black window (Vsig = 4.0V/1V). Cross talk value CTK = · 100 [%] W2' W4' W1 W1' W3 W3' 9. Definition of Viewing Angle Range Viewing angle range is measured by System I. The contrast ratio (CR) is measured at the angles defined in the figure to the right and the range where CR ‡ 10 is taken as the viewing angle range. Measure with surface A* facing upwards. * Surface A: See the Package Outline. θT θR θB θL N orm al (θ = 0°) R ight Left Bottom Top Surface A 10. Surface Reflection Ratio Surface reflection ratio (Rf) is given by the following formula. Rf = Reflected optical luminance of the panel surface A*/Reflected optical luminance of Al (wafer) · 100 [%] The incident and reflected angles of light are both 0°. Both luminosities are measured by System III. * Surface A: See the Package Outline. Wi Wi' – Wi

– 18 – ACX306AK 2 490 494 1 240 242 G ate SW G ate SW G ate SWG ate SWG ate SWG ate SW G R G B R G B R G B R G B R G B B G B R G B R B R G B R G B R GR R G R G B R G B R G B R G B R G B B G B R G B R B R G B R G B R GR R G R G B R G B R G B R G B R G B B G B R G B R B R G B R G B R GR R G R G B R G B R G B R G B R G B B G B R G B R B R G B R G B R GR R Active area Description of Panel Block Operation 1. Color Coding The color filters are coded in a delta arrangement. The shaded area is used for the dark border around the display.

– 19 – ACX306AK 2. Description of LCD Panel Operations

• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to each of 240 line electrodes sequentially one line electrode at a time in a single horizontal scanning period.
• The selected pulse is output when the enable pin goes to high level. PAL signal pulse elimination display is possible by using the enable pin and simultaneously controlling VCK.
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuitry, applies selected pulses to each of 490 signal electrodes sequentially in a single horizontal scanning period. These pulses are used to supply the sampled video signal to the row signal lines.
• The scanning direction of the horizontal shift registers can be switched with the RGT pin. The scanning direction is left to right (right scan) for RGT pin at high level (2.6 to 5.5V), and right to left (left scan) for RGT pin at low level (0V). In addition, the scanning direction of the vertical shift registers can be switched with the DWN pin. The scanning direction is top to bottom for DWN pin at high level (2.6 to 5.5V), and bottom to top for DWN pin at low level (0V). (These scanning directions are from a front view.)
• The vertical and horizontal drivers address one pixel, and then thin film transistors (TFTs; two TFTs for one pixel) turn on to apply a video signal to the pixel. The same procedures lead to the entire 240 · 490 pixels to display a picture in a single vertical scanning period.
• Pixel dots are arranged in a delta pattern, where sets of RGB pixels are positioned shifted by 1.5 dots against adjacent horizontal lines. The horizontal driver output pulse must be shifted by 1.5 dots for each horizontal line against the horizontal sync signal to apply a video signal to each pixel properly.
• The video signal should be input with the polarity-inverted every horizontal cycle.
• The relationships between the vertical shift register start pulse VST and the vertical display period, and between the horizontal shift register start pulse HST and the horizontal display period are shown below for top to bottom and left to right scan. (1) Vertical display period (DWN: high level) BLK H ST H C K1 H C K2 1 2 3 164 165 166 H orizontal display period (54.6µs) VD VST VC K 1 2 Vertical display period 240H (14.5m s) 239 240 VD VST VC K 1 2 Vertical display period 240H (14.5m s) 239 240 (3) Horizontal display period (RGT: high level) (2) Vertical display period (DWN: low level)

– 20 – ACX306AK 3. RGB Simultaneous Sampling The horizontal driver samples R, G and B video signal simultaneously, which requires phase matching between the R, G and B signals to prevent the horizontal resolution from deteriorating. Thus phase matching by an external signal delay circuit is needed before applying the video signal to the LCD panel. Two methods are applied for the delaying procedure: Sample-and-hold and Delay circuit. These two block diagrams are as follows. The ACX306AK has a right/left inversion function. The following phase relationship diagram indicates the phase setting for right scan (RGT = high level). For left scan (RGT = low level), the phase setting should be inverted for the B and G signals. (1) Sample-and-hold (right scan) AC Am p AC Am p AC Am p S/H S/H S/H S/H C KB C KG C KG C KG C KR B R G BLU E R ED G R EEN ACX306AK S/H H C Kn C KB C KR C KG AC Am p AC Am p AC Am p D elayD elayB R G BLU E R ED G R EEN ACX306AK D elay <Phase relationship of delaying sample-and-hold pulses> (right scan) (2) Delay element (right scan)

– 21 – ACX306AK System Configuration PSIG G R EEN BLU E C O M H C K2 VC K R ED H C K1 H ST VST EN R G T R EF W ID E Y/color difference R /G /B Serial data D W N 1µF R ext ∗ See page 3 for the value setting. C ext C XA3522R LC D Panel AC X306AK C ext/R ext VSSG 1µF Zener diode R D 4.3U M VD D G +12.0V Zener diode R D 2.7U M

– 22 – ACX306AK Notes on Handling (1) Static charge prevention Be sure to take the following protective measures. TFT-LCD panels are easily damaged by static charges. a) Use non-chargeable gloves, or simply use bare hands. b) Use an earth-band when handling. c) Do not touch any electrodes of a panel. d) Wear non-chargeable clothes and conductive shoes. e) Install grounded conductive mats on the working floor and working table. f) Keep panels away from any charged materials. g) Use ionized air to discharge the panels. (2) Protection from dust and dirt a) Operate in a clean environment. b) When delivered, the panel surface (Polarizer) is not covered by a protective sheet. Take care of handling it so as not to damage the polarizer. c) Do not touch the polarizer surface. The surface is easily scratched. When cleaning, use a clean-room wiper with isopropyl alcohol. Be careful not to leave stains on the surface. d) Use ionized air to blow dust off the panel. (3) Others a) Do not twist or bend the flexible PC board especially at the connecting region because the board is easily deformed. b) Do not drop the panel. c) Do not twist or bend the panel or panel frame. d) Keep the panel away from heat sources. e) Do not dampen the panel with water or other solvents. f) Avoid storage or use the panel at high temperatures or high humidity, as this may result in damage.

– 23 – ACX306AK Package Outline Unit: mm 4 5 B B B B 4±0.1 1.4 ±0.1 LC D panel A (3 : 1) 0.35 ±0.03 Pin1Pin24 0.5±0.15 25.4(Window)3.42 (3.78) 24.4±0.4(Polarizer) 16.95 16.85 32.7 ±0.4 (Polarizer) 7.5 φ 0.85 ±0.05 3±0.3 25±0.4(Polarizer) 33.3 ±0.4 (Polarizer) 34.3(W indow ) (16.48)16.12 32.6 22.86(Active area) 26(Window) (3.48)3.12 1.85 (1.85) N ote2 30.48(Effective area) 12.5 ±0.05 34.9±0.5 21.5±0.5 7.81±0.5 3.25 ±0.5 6.6 ±0.5 10.94 ±0.5 10.53 ±0.5 28.9±0.5 4±0.5 31.115(Active area) 12.5 ±0.05 2.06 1.03 0.3 1.4 9.82 10.18 (20) C enter (reference) C enter (reference) Erectrode enlarged(back) R ear View Front view N ote1. Tolerance w ith no indication(±0.2) 2. SO N Y logotype 3. D esign the guaranteed area of polarizer w ithin the outer circum ference of 0.7m m of the active area. 4. M ass:approxim ately 7g FPC R einforcing board Polarizer Shield case(front) Shield case(rear) label Sony Corporation