ACX301AKM

ACX301AKM SONY | Alldatasheet

Document overview

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PDF pages: 26

Technical content

Features

Number of active dots: 200,000, 5.1cm (2.0 Type) in diagonal
Horizontal resolution: 440 TV lines
Center luminance: 250cd/m 2 (typ.)
High contrast ratio with normally white mode: 200 (typ.)
Built-in H and V driving circuitry (built-in input level conversion circuit, 3V drive possible)
Low voltage, low power consumption: 12V drive: 50mW (panel block, typ.) 0.48W (CCFL∗ power consumption, typ.) ∗ Cold cathode fluorecene lamp
Smooth pictures with a RGB delta arrangement
Supports NTSC/PAL
Built-in picture quality improvement circuit
Up/down and/or right/left inverse display function
16:9 screen display function
LR (low reflectance) surface treatment provides an easy-to-see display even outdoors
Dirt-resistant surface treatment
Thin package using a dedicated backlight (5.8mm thick)
High color reproductivity using a backlight optimum for LCD panels Element Structure
Active matrix TFT-LCD panel with built-in peripheral driving circuitry using low temperature polycrystalline silicon transistors
Edge-light type backlight using cold cathode tubes
Number of pixels Total number of dots: 896 (H) × 230 (V) = 206,080 Number of active dots: 880 (H) × 228 (V) = 200,640
Module dimensions Package dimensions: 50.5 (W) × 45.6 (D) × 5.8 (H) (mm) Effective display dimensions: 40.5 (H) × 30.6 (V) (mm)

Applications

LCD monitors, etc. – 1 – E99633A01-PS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 2 – ACX301AKM Block Diagram The panel block diagram is shown below. LCC S TESTL TESTR COM VST VCK EN DWN VV DD V SS HV DD VSSG TEST2WIDEHST REF TEST Cext/Rext HCK2HCK1PSIG GREEN RED BLUERGT COM 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 231 2417 V Shift Register H, V Level Shifter Negative Voltage Generation Circuit Common Voltage H Shift Register LCD panel ACX301AK Backlight block harness Integrated type dedicated backlight Module Configuration This module is comprised of a 2.0 Type 200,000- dot color TFT-LCD panel (ACX301AK) combined with an integrated type dedicated backlight as shown in the figure on the right.

– 3– ACX301AKM Absolute Maximum Ratings(Vss = 0V)

H driver supply voltage HV DD , Cext/Rext –1.0 to +17 V
V driver supply voltage VV DD –1.0 to +15 V
V driver negative supply voltage VSSG –3.0 to +1.0 V
Common voltage of panel COM –1.0 to +17 V
H driver input pin voltage HST, HCK1, HCK2, RGT, WIDE –1.0 to +17 V
V driver input pin voltage VST, VCK, EN, DWN, REF –1.0 to +15 V
Video signal, uniformity improvement signal input pin voltage GREEN, RED, BLUE, PSIG –1.0 to +13 V
Operating temperature Topr –10 to +60 °C
Storage temperature Tstg –30 to +85 °C
Storage humidity Hstg 40 °C 95% RH
CCFL voltage Vcfl 2.0 kVp-p
CCFL current Icfl 4 mArms Operating Conditions of Panel Block 1. Input/output supply voltage conditions∗1 (VSS = 0V) Item Supply voltage HV DD VV DD Cext/Rext∗2 VSSG Rext 11.4 11.4 HV DD – 3.4 –2.3 12.0 12.0 12.0 –1.8 14.0 14.0 –1.5 160 V V V V kΩ VSSG output voltage setting∗ Resistor connected to Cext/Rext pin∗2 Symbol Min. Typ. Max. Unit ∗1 The HVDD /VVDD typical voltage setting is noted as 12.0V in these specifications. ∗2 Connect the resistor and capacitor to the Cext/Rext pin as shown in the figure below. ∗3 For the VSSG output setting, connect an external smoothing capacitor and a voltage stabilizing Zener diode as shown in the figure below. HV DD – Cext/Rext Cext/RextHV DD HV DD Voltage Time text Set a Cext and a Rext value that satisfies text > 1ms for the period HV DD – Cext/Rext > 7V. Cext/Rext constant setting condition Rext ACX301AKM HV DD VSSG VSS Cext/Rext 1µF Use a Zener voltage of 2.7V. (RD2.7UM is recommended) Cext

– 4– ACX301AKM ∗4 Input video and uniformity improvement signals should be symmetrical to VVC. The input conditions for the uniformity improvement signal Vpsig differ for 4:3 display and 16:9 display. 1) During 4:3 display, input the voltage amplitude symmetrical to VVC as shown in Fig. 1. 2) During 16:9 display, input the same signal amplitude as in 1) above during the effective display portion, and input the black signal level VpsigBK during the top/bottom black input portion as shown in Fig. 2. During 4:3 display PSIG waveform VVC Vpsig During 16:9 display PSIG waveform VVC Vpsig VpsigBK VVC ± 4.0V VVC ± 2.5V Top/bottom black display portion (letterbox portion) Effective display portion Fig. 1 Fig. 2 Item Lighting start voltage (Ta = –10°C) Driving frequency CCFL voltage (Ta = 25°C) CCFL current (Ta = 25°C) Wire harness applied voltage Vstart Fcfl VLcfl ILcfl Vlmax 180 1.0 200 2.4 640 100 220 4.0 2.0 Vrms kHz Vrms mArms kVp-p Symbol Min. Typ. Max. Unit Operating Conditions of Backlight Block Input supply voltage conditions Item H/V driver input voltage (Low) (High) VIL VIH VREF VVC Vsig Vpsig VpsigBK Vcom –0.3 2.6 VIH/2 – 0.3 5.3 1.0 VVC ± 2.3 VVC – 0.55 0.0 3.0 VIH/2 5.5 VVC ± 4.0 VVC ± 2.5 VVC ± 4.0 VVC – 0.4 0.3 5.5 VIH/2 + 0.3 5.7 VV DD – 2.0 (however, 10V or less) VVC ± 2.7 VVC ± 4.5 VVC – 0.25 V V V V V V V V REF input voltage Video signal center voltage Video signal input range Uniformity improvement signal 16:9 display top/bottom black signal∗ Common voltage of panel (Ta = 25°C) Symbol Min. Typ. Max. Unit 2. Panel input signal voltage conditions (VSS = 0V)

– 5– ACX301AKM Pin No. TESTL COM VST VCK EN DWN VV DD VSS HV DD VSSG TEST2 WIDE HST REF TEST Cext/ Rext HCK2 HCK1 PSIG GREEN RED BLUE RGT TESTR Start pulse input for H shift register drive Level shifter circuit REF voltage input Panel test output; no connection Time constant power supply input for H shift register drive Clock input for H shift register drive Clock input for H shift register drive Uniformity improvement signal input Video signal (G) input to panel Video signal (R) input to panel Video signal (B) input to panel H shift register drive direction signal input Panel test output; no connection Symbol Description Pin No. Symbol Description Panel test output; no connection Common voltage input of panel Start pulse input for V shift register drive Clock input for V shift register drive Gate selection pulse enable input V shift register drive direction signal input Power supply input for V driver H and V driver GND Power supply input for H driver Negative power supply setting for V driver No connection inside the panel. (with 1MΩ terminating resistor) Pulse input for 16:9 mode Pin Description of Panel Block Pin No.

1 CH 4 CL CCFL low voltage side connection

No. Symbol Description CCFL high voltage side connection Pin Description of Backlight Block

– 6– ACX301AKM Input Equivalent Circuits of Panel Block To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition, protective resistors are added to all pins except the video signal input pins. All pins are connected to V SS with a high resistance of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (Resistor value: typ.) (1) RED, GREEN, BLUE, PSIG HV DD 1M Ω Input Signal line (2) HCK1, HCK2 1M Ω 1M Ω HV DD HV DD HCK1 HCK2 H level shifter and shift register circuit (3) HST, WIDE, REF 1M Ω 350Ω 1M Ω 350Ω HV DD HV DD Input REF Level conversion circuit (4) RGT, REF 1M Ω 2kΩ 1M Ω 2kΩ HV DD HV DD Input REF Level conversion circuit (5) VST, VCK, EN, REF 1M Ω 800Ω 1M Ω 800Ω VV DD VV DD Input REF Level conversion circuit

– 7– ACX301AKM (10) TEST/TEST2 HV DD TEST 350Ω 1M Ω 350Ω TEST2 1M Ω (11) TESTL, TESTR TESTL TESTR VV DD 1.5MΩ (6) DWN, REF 1M Ω 1M Ω VV DD VV DD Input REF 2kΩ2kΩ Level conversion circuit (7) VSSG HV DD VSSG Negative voltage generation circuit (8) COM 1M Ω Input LC (9) Cext/Rext HV DD Cext/Rext H driver 1M Ω

– 8– ACX301AKM Clock Timing Conditions of Panel Block (VIH = 3.0V, HVDD = VVDD = 12V, Ta = 25°C) HST rise time HST fall time HST data setup time HST data hold time HCKn ∗ 5 rise time HCKn ∗5 fall time HCK1 fall to HCK2 rise time HCK1 rise to HCK2 fall time VST rise time VST fall time VST data setup time VST data hold time VCK rise time VCK fall time EN rise time EN fall time EN fall to VCK rise/fall time EN pulse width WIDE rise time WIDE fall time WIDE (H) rise to VCK rise/fall time WIDE (H) pulse width WIDE (V) pulse width WIDE (V) fall to EN rise time EN rise to WIDE (V) fall time trHst tfHst tdHst thHst trHckn tfHckn to1Hck to2Hck trVst tfVst tdVst thVst trVckn tfVckn trEn tfEn tdEn twEn trWide tfWide tdhWide twhWide twvWide tov1Wide tov2Wide 137 –30 –15 –15 –30 2400 5400 0.9 2.8 1928 167 –32 2500 5500 1.1 3.0 1933 197 100 100 –34 100 100 100 100 2600 5600 100 100 1.3 3.3 1938 ns µs µs ns Item Symbol Min. Typ. Max. Unit HST HCK VST VCK EN WIDE 5 HCKn means HCK1 and HCK2. (fHCKn = 3.0MHz)

– 9– ACX301AKM Horizontal Standard Timing 5.0µs 1.3µs 2.5µs 3µs 1.1µs 1.9µs HST Hck1 Hck2 FRP Vck EN WIDE 1∗7 (CXA3268AR) WIDE 2 (CXA3268R) WIDE signal has two timing of CXA3268R and CXA3268AR, and panel characteristics guarantee both timing.

– 10– ACX301AKM ∗6 Definitions: The right-pointing arrow ( ) means +. The left-pointing arrow ( ) means –. The black dot at an arrow ( ) indicates the start of measurement. 7 WIDE represents every 1H pulse as shown in the Horizontal Timing. <Horizontal Shift Register Driving Waveforms> HST rise time HST HCK HST fall time HST data setup time HST data hold time HCKn ∗5 rise time HCKn ∗5 fall time HCK1 fall to HCK2 rise time HCK1 rise to HCK2 fall time

HCKn ∗5 duty cycle 50% to1Hck = 0ns to2Hck = 0ns
HCKn ∗ 5 duty cycle 50% to1Hck = 0ns to2Hck = 0ns
HCKn ∗ 5 duty cycle 50% to1Hck = 0ns to2Hck = 0ns tdHst = 167ns thHst = 0ns
tdHst = 167ns thHst = 0ns trHst tfHst tdHst thHst trHckn tfHckn to1Hck to2Hck Item Symbol Waveform Conditions 90% 90% 10% 10% HST trHst tfHst 50% 50% 50% tdHst thHst HST HCK1 50% HCKn 90% 90% 10%10% trHckn tfHckn 50% 50% 50%50% HCK1 HCK2 to2Hck to1Hck WIDE WIDE rise time WIDE fall time WIDE rise to Vck rise/ fall time WIDE pulse width trWide tfWide tdhWide twhWide WIDE 90% 90% 10% 10% trWide tfWide VCK 50% WIDE 50% 50% tdhWide twhWide

– 11– ACX301AKM Vertical Standard Timing VST Vck FRP HST EN WIDE NTSC 4:3 (in case of EVEN field) VST Vck FRP HST EN WIDE NTSC WIDE (in case of EVEN field)

– 12– ACX301AKM EN rise time EN WIDE EN fall time EN fall to VCK rise/fall time EN pulse width WIDE rise time WIDE pulse width trEn tfEn tdEn twEn trWide WIDE fall time tfWide twvWide WIDE fall to EN rise timetov1Wide EN fall to WIDE fall timetov2Wide 90% tfEn 10% EN 90% 10% trEn VCK 50% EN 50% 50% tdEn twEn WIDE 90% 90% 10% 10% trWide tfWide 50%50%WIDE twvWide 50% WIDE 50%50%EN tov2Wide tov1Wide

VCK duty cycle 50% to1Vck = 0ns to2Vck = 0ns <Vertical Shift Register Driving Waveforms> VST rise time VST VCK VST fall time VST data setup time VST data hold time VCK rise time trVst tfVst tdVst thVst trVck VCK fall time tfVck Item Symbol Waveform Conditions 90%90% VST trVst tfVst 10%10% 50% 50% VST 50% 50% VCK tdVst thVst VCK 90% 90% 10%10% trVck tfVck
VCK duty cycle 50% to1Vck = 0ns to2Vck = 0ns
VCK duty cycle 50% to1Vck = 0ns to2Vck = 0ns
VCK duty cycle 50% to1Vck = 0ns to2Vck = 0ns tdVst = 32µs thVst = –32µs 8 WIDE represents 1F cycle as shown in the Vertical Timing.

– 13– ACX301AKM Electrical Characteristics of Panel Block(Ta = 25°C, HVDD = 12.0V, VVDD = 12.0V, VIH = 3.0V, VREF = 1.5V) 1. Horizontal drivers Item HCKn input pin capacitance HST input pin capacitance Video signal input pin capacitance Psig input pin capacitance (4:3 display) Psig input pin capacitance (16:9 display) Input pin current HCK1 HCK2 HST RGT REF Current consumption (Ta = 25°C) (Ta = 60°C) CHckn CHst Csig Cpsig Cpsig I Hck1 I Hck2 I Hst I RGT I REF I H25 I H60 HCK1: actual driving HCK2: actual driving HST = GND RGT = GND REF = VIH/2 –900 –900 –300 –150 –1200 170 –300 –300 –100 –50 –300 3.3 210 4.0 5.0 pF pF pF nF nF µA µA µA µA µA mA mA Symbol Min. Typ. Max. Unit Conditions 2. Vertical drivers Item VCK input pin capacitance VST input pin capacitance Input pin current VCK VST EN DWN WIDE Current consumption (Ta = 25°C) (Ta = 60°C) CVck CVst I Vck I Vst I En I DWN I WIDE I V25 I V60 –150 –150 –150 –150 –150 –50 –50 –50 –50 –50 0.7 1.0 1.3 pF pF µA µA µA µA µA mA mA Symbol Min. Typ. Max. Unit Conditions 3. Total power consumption of the panel Item Total power consumption of the panel (NTSC) (Ta = 25°C) (Ta = 60°C) PWR25 PWR60 mW mW Symbol Min. Typ. Max. Unit 4. Pin input resistance Item Pin – VSS input resistance 1 Test pin – VVDD input resistance 2 Rin1 Rin2 0.5 0.75 1.5 M Ω M Ω Symbol Min. Typ. Max. Unit VCK = GND VST = GND EN = GND DWN = GND WIDE = GND HCKn: HCK1, HCK2 (3.0MHz)

– 14– ACX301AKM Electro-optical Characteristics of Module/Panel Block (Ta = 25°C, NTSC mode) Item X Y X Y X Y X Y 25°C 60°C 25°C 60°C 25°C 60°C R – G B – G 0°C 25°C 0°C 25°C 60°C 60°C CR ≥ 10 θ = 0° 25°C R G B V V50 V10 ON time OFF time CR 25 T Lm Tcm Rx Ry Rx Ry Gx Gy Bx By V 90-25 V90-60 V50-25 V50-60 V10-25 V10-60 V50RG V50BG ton0 ton25 toff0 toff25 F YT1 θT θB θL θR Rf CTK 100 5.2 200 5700 0.61 0.32 0.26 0.59 0.13 0.09 1.3 1.3 1.7 1.7 2.2 2.2 –0.11 200 5.6 250 6600 0.31 0.34 0.63 0.34 0.28 0.61 0.15 0.11 1.5 1.5 1.9 1.9 2.4 2.4 –0.08 0.03 120 –60 0.8 0.7 0.33 0.36 0.65 0.36 0.30 0.63 0.17 0.13 1.7 1.7 2.1 2.1 2.6 2.6 –0.05 0.05 180 –30 1.5 1.5 cd/m K CIE standards V V ms dB s Degree (°) Contrast ratio Panel transmittance∗1 Center luminance Center color temperature Center chromaticity Chromaticity V-T characteristics∗1 Half tone color reproduction range∗1 Response time∗1 Flicker∗1 Image retention time∗1 Viewing angle range Surface reflection ratio Cross talk∗1 Symbol Measurement method Min. Typ. Max. Unit ∗1 Conforms to the measurement results for the discrete panel.

– 15– ACX301AKM Electro-optical Characteristics of Backlight Block Item Lcbl Tcbl xbl ybl BLunif BLlife Tbl25 Tbl-5 3740 7100 0.275 0.289 10000 4400 8400 0.290 0.304 10700 0.305 0.319 cd/m K CIE standards hr s s Backlight center luminance∗2 Backlight color temperature∗2 Backlight chromaticity∗2 Backlight luminance uniformity∗2 Backlight life∗2 Lighting time after dark storage∗2 (lighting performance after dark storage for 70 hours or more) Symbol Measurement method Min. Typ. Max. Unit ∗2 Conforms to the measurement results for the discrete backlight. 25°C –10°C

– 16– ACX301AKM <Panel/Module/Backlight Electro-optical Characteristics Measurement> Basic measurement conditions (1) Driving voltage HV DD = 12.0V, VVDD = 12.0V, VIH = 3.0V, VREF = 1.5V VVC = 5.5V, VCOM = 5.1V, Vpsig = 5.5 ± 2.5V (2) Measurement temperature 25°C unless otherwise specified. (3) Measurement point One point in the center of the screen unless otherwise specified. (4) Measurement systems Three types of measurement systems are used as shown below. (5) R, G and B input signal voltage Vsig Vsig = 5.5 ± VAC [V] (VAC : signal amplitude)

Measurement system I
Measurement system II Luminance Meter Measurement EquipmentLight DetectorLight receptor lens Measure using the discrete LCD panel.
Measurement system III Drive Circuit Light Source Optical fiber Light Source Spectroscope Surface A∗ Surface A∗ Surface A∗ ∗ Surface A: See the Package Outline. Backlight LCD panel Optical fiber 13585A DC Using the Stanley 13585A inverter. Using the TOPCON BM-5A luminance meter. 2.4mA ALow voltage side 1. Contrast Ratio Contrast ratio (CR) is given by the following formula. CR = L (White)/L (Black) L (White): Surface luminance of the TFT-LCD panel at the input signal amplitude VAC = 0.5V. L (Black): Surface luminance of the panel at VAC = 4.0V. Both luminosities are measured by System I.

– 17– ACX301AKM 2. Optical Transmittance of Panel Block, Module Center Luminance, Color Temperature Optical transmittance (T) is given by the following formula. T = L (White)/Luminance of Backlight × 100 [%] L (White) is the same expression as defined in the "Contrast Ratio" section. Optical transmittance is measured by System Iusing the TOPCON BM-5A. Lm = White luminance at the center of the panel Tcm = Color temperature at the center of the panel 3. Chromaticity Chromaticity of the panels is measured by System I. Raster modes of each color are defined by the representations at the input signal amplitude conditions shown in the table below. System Iuses x and y of the CIE standards as the chromaticity here. 4. V-T Characteristics V-T characteristics, or the relationship between signal amplitude and the transmittance of the panel, are measured by System IIby inputting the same signal amplitude V AC to each input pin. V90, V50, and V10 correspond to the voltages which define 90%, 50%, and 10% of transmittance respectively. V10V50V90 VAC – Signal amplitude [V] Transmittance [%] 5. Half Tone Color Reproduction Range The half tone color reproduction range of LCD panels is characterized by the differences between the V-T characteristics of R, G and B. The differences of these V-T characteristics are measured by System II. System IIdefines signal voltages of each R, G and B raster mode which correspond to 50% of transmittance, V 50R , V50G and V50B, respectively. V50RG and V50BG , that is to say the differences between V50R and V50G and between V50B and V50G , are given by the following formulas respectively. V50RG = V50R – V50G V50BG = V50B – V50G Transmittance [%] V50R VAC – Signal amplitude [V] 100 V50B V50G V50RG V50BG G raster B rasterR raster R input G input B input Raster R G B 0.5 4.0 4.0 4.0 0.5 4.0 4.0 4.0 0.5 W 0.0 0.0 0.0 Signal amplitudes (VAC ) supplied to each input (Unit: V)

– 18– ACX301AKM 6. Response Time Response times ton and toff are measured by System II by applying the input signal voltages in the figure to the right to each input pin. These times are defined by the following formulas. ton = t1 – tON toff = t2 – tOFF t1: time which gives 10% transmittance of the panel. t2: time which gives 90% transmittance of the panel. The relationships between t1, t2, tON and tOFF are shown in the figure to the right. 4.0V 5.5V 0.5V Optical transmittance output waveform 100% 90% 10% tON t1 tOFF t2 ton toff Input signal voltage (Waveform applied to measured pixels) 7. Flicker Flicker (F) is given by the following formula. DC and AC components (NTSC: 30Hz, rms; PAL: 25Hz, rms) of the panel output signal for gray raster∗ mode are measured by a DC voltmeter and a spectrum analyzer in System II. F (dB) = 20 log {AC component/DC component} ∗ R, G, B input signal voltage for gray raster mode is given by Vsig = 5.5 ± V 50 (V) where: V50 is the signal amplitude which gives 50% of transmittance in V-T curve. 8. Image Retention Time Image retention time is given by the following procedures. Apply the monoscope pattern∗ to the LCD panel for 1 minute and then change to a gray scale signal (Vsig = 5.5 ± V AC (V); VAC = 3 to 4V). Judging by sight at the VAC that holds the maximum image retention, measure the time for the residual image to disappear. ∗ Monoscope pattern input conditions (shown in the figure to the right) Vcom = 5.1V 5.5V 4.0V 2.0V 4.0V 2.0V Black level White level Vsig waveform

– 19– ACX301AKM 11. Cross Talk Cross talk is determined by the luminance differences between adjacent areas represented by Wi' and Wi (i = 1 to 4) around the black window (Vsig = 4.0V/1V). Cross talk value CTK = | Wi' – Wi/Wi |× 100 [%] W2' W4' W1 W1' W3 W3' 9. Definition of Viewing Angle Range Viewing angle range is measured by System Ι. The contrast ratio (CR) is measured at the angles defined in the figure to the right and the range where CR ≥ 10 is taken as the viewing angle range. Measure with surface A∗ facing upwards. ∗ Surface A: See the Package Outline. θT θR θB θL Normal (θ = 0°) Right Left Bottom Top Surface A 10. Surface Reflection Ratio Surface reflection ratio (Rf) is given by the following formula. Rf = Reflected optical luminance of the panel surface A∗/Reflected optical luminance of Al (wafer) × 100 [%] The incident and reflected angles of light are both 0°. Both luminosities are measured by System III. ∗ Surface A: See the Package Outline.

– 20– ACX301AKM 12. Backlight Characteristic Measurement Conditions 1) Test inverter operating conditions (using a Stanley 13585A inverter) Driving frequency: 58.4kHz Input voltage: 6.1V Input current: 0.105mA Input power: 0.64W Tube current: 2.4mA Tube voltage: 200V Tube power: 0.48W 2) Ambient temperature and humidity Temperature: 25 ± 1°C Humidity: 30 to 85% (Start measurement after leaving the module in the above environment for one hour.) Measurement should be performed in a dark room with a luminance of 10 lx or less and which is not subject to the effects of reflective or external light. There should be no heat insulating objects around the module unit, and measurement should be performed in a draftless condition. 3) Luminance and chromaticity measurement Measurement equipment: TOPCON BM-5A, viewing angle: 0.1°, distance: 500mm Measure 10 minutes after the backlight is lit. 13. Backlight Uniformity Measurement Method Start each measurement 10 minutes after the backlight is lit. Luminance uniformity of the backlight is obtained by measuring the luminance at the 9 points shown below and calculating Min. luminance ÷ Max. luminance × 100 [%]. 13.1 13.1 10.1 10.1 14. Backlight Life Measurement Method Definition or life: When the center luminance drops to 50% of the initial value during continuous lighting, or when normal lighting becomes impossible. Lighting conditions: 25 ± 5°C, CCFL current: 2.4mArms 15. Backlight Dark Lighting Characteristics Measurement Method Shelf conditions: Leave for 70 hours or more in the dark at each temperature (25°C, –10°C) condition. Lighting conditions: 0.5 lx or less at each temperature (25°C, –10°C) condition. The used inverter should have a Vp-p or 1.81kVp-p or more. Lighting time: Time from power-on until the backlight is lit.

– 21– ACX301AKM R GB 228 230 G G G Gate SW Gate SW Gate SWGate SWGate SWGate SW RGB RGB RGB RGBRGB B GBRGB R BR GBRG BR RG BRGBRGBRGBR GB BG B R G B R G B R G B R RGB GB RGB RGBRGB BG B R G B R B R G B R G B R RGBR GBRGBRGBRGB BG B R G B RB R G B R G B R G G G G Active area 896 880 R R R R R R R R R Description of Panel Block Operation 1. Color Coding The color filters are coded in a delta arrangement. The shaded area is used for the dark border around the display.

– 22– ACX301AKM 2. Description of LCD Panel Operations

A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to each of 228 line electrodes sequentially one line electrode at a time in a single horizontal scanning period.
The selected pulse is output when the enable pin goes to high level. PAL signal pulse elimination display and 16:9 mode pulse elimination display are possible by using the enable pin and simultaneously controlling VCK.
A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuitry, applies selected pulses to each of 880 signal electrodes sequentially in a single horizontal scanning period. These pulses are used to supply the sampled video signal to the row signal lines.
The scanning direction of the horizontal shift registers can be switched with the RGT pin. The scanning direction is left to right (right scan) for RGT pin at high level (2.6 to 5.5V), and right to left (left scan) for RGT pin at low level (0V). In addition, the scanning direction of the vertical shift registers can be switched with the DWN pin. The scanning direction is top to bottom for DWN pin at high level (2.6 to 5.5V), and bottom to top for DWN pin at low level (0V). (These scanning directions are from a front view.)
The vertical and horizontal drivers address one pixel, and then thin film transistors (TFTs; two TFTs for one pixel) turn on to apply a video signal to the pixel. The same procedures lead to the entire 228 × 880 pixels to display a picture in a single vertical scanning period.
Pixel dots are arranged in a delta pattern, where sets of RGB pixels are positioned shifted by 1.5 dots against adjacent horizontal lines. The horizontal driver output pulse must be shifted by 1.5 dots for each horizontal line against the horizontal sync signal to apply a video signal to each pixel properly.
The video signal should be input with the polarity-inverted every horizontal cycle.
The relationships between the vertical shift register start pulse VST and the vertical display period, and between the horizontal shift register start pulse HST and the horizontal display period are shown below for top to bottom and left to right scan. (1) Vertical display period (DWN: high level) BLK HST HCK1 HCK2 123 293 294 295 Horizontal display period (48.9µs) VD VST VCK 12 Vertical display period 228H (14.5ms) 227 228 VD VST VCK 12 Vertical display period 228H (14.5ms) 227 228 (3) Horizontal display period (RGT: high level) (2) Vertical display period (DWN: low level)

– 23– ACX301AKM 3. RGB Simultaneous Sampling The horizontal driver samples R, G and B video signal simultaneously, which requires phase matching between the R, G and B signals to prevent the horizontal resolution from deteriorating. Thus phase matching by an external signal delay circuit is needed before applying the video signal to the LCD panel. Two methods are applied for the delaying procedure: Sample-and-hold and Delay circuit. These two block diagrams are as follows. The ACX301AK has a right/left inversion function. The following phase relationship diagram indicates the phase setting for right scan (RGT = high level). For left scan (RGT = low level), the phase setting should be inverted for the B and G signals. (1) Sample-and-hold (right scan) AC Amp AC Amp AC Amp S/H S/H S/H S/H S/H CKB CKG CKG CKG CKR B R G BLUE RED GREEN ACX301AK HCKn CKB CKR CKG AC Amp AC Amp AC Amp Delay Delay DelayB R G BLUE RED GREEN20 ACX301AK <Phase relationship of delaying sample-and-hold pulses> (right scan) (2) Delay element (right scan)

– 24– ACX301AKM System Configuration PSIG GREEN BLUE COM HCK2 VCK RED HCK1 HST VST EN RGT REF WIDE Y/color difference R/G/B Serial data Inverter LCD Panel ACX301AK DWN Cext/Rext VSSG 1µF Use a Zener diode RD2.7UM is recommended. Rext∗1 Cext∗1 Dedicated backlight ACX301AKM (module with backlight) ∗1 See page 3 for the value setting. ∗2 When the CXA3268AR is used, insert buffer circuit to PSIG output. Buffer CXA3268R CXA3268AR

– 25– ACX301AKM Notes on Handling (1) Static charge prevention Be sure to take the following protective measures. TFT-LCD panels are easily damaged by static charges. a) Use non-chargeable gloves, or simply use bare hands. b) Use an earth-band when handling. c) Do not touch any electrodes of a panel. d) Wear non-chargeable clothes and conductive shoes. e) Install grounded conductive mats on the working floor and working table. f) Keep panels away from any charged materials. g) Use ionized air to discharge the panels. (2) Protection from dust and dirt a) Operate in a clean environment. b) When delivered, the panel surface (Polarizer) is covered by a protective sheet. Peel off the protective sheet carefully so as not to damage the panel. c) Do not touch the polarizer surface. The surface is easily scratched. When cleaning, use a clean-room wiper with isopropyl alcohol. Be careful not to leave stains on the surface. d) Use ionized air to blow dust off the panel. (3) Module fixing method a) The design reference edges are the upper and left edges as viewed from the front. (See the Package Outline.) b) Positioning in the x and y directions should be based on the panel frame or the panel window frame. c) Do not set positioning guides inside the following ranges. c-1: Within 2.3mm on both sides of the four panel frame corners c-2: FPC outlet portion c-3: Back light lamp socket portion d) Set the backlight holder on the rear of the backlight outside of the effective area of the panel. In particular, use a structure that does not apply pressure near the center of the rear of the backlight. e) Connect the panel or backlight frame to GND. (static charge prevention) f) High voltage is applied around the CCFL, so avoid locating metal objects within 1mm from the side of the lamp socket (rubber) in order to prevent discharge. (See the figure below.) (4) Other handling precautions a) Do not twist or bend the flexible PC board especially at the connecting region because the board is easily deformed. b) Do not fold or pull on the backlight harness. c) Do not drop the panel. d) Do not twist or bend the panel, panel frame or backlight. e) Keep the panel and backlight away from heat sources. f) Do not dampen the panel or backlight with water or other solvents. g) Avoid storage or use the panel at high temperatures or high humidity, as this may result in damage (faulty backlight lighting). Metal object prohibited area (lamp socket side) 1.0 (High voltage side)

– 26– ACX301AKM Package Outline Unit: mm 40.48 (Active area) 42.7±0.4 (Polarizer) 45.5 (Window) 49.8 (25.27)18.93 44.2 30.55 (Active area) 32.8±0.4(Polarizer) 33.8 (Window) (8.37)2.03 2.15 (2.15) Center (reference) 2.2 Rear View Note3 Note2 Front view 7.5 4 5 4.3±0.4 24.9 30.5±0.5 0.3±0.05 12.5±0.05 12.8±0.5 75±2 40±2

2 Note4

1.1 18.63 43.6±0.3(Backlight) 5.8±0.4 9.5 50.5±0.3 Electrode Mass: Approximately 20g 0.35±0.03 Pin1Pin24 Erectrode enlarged (back) Note1. Tolerance with no indication± 0.2) 2. SONY logotype 3. Label is stuck here 4. Dimension of harness connection block rubber socket

1 FPC

2 Reinforcing board

3 Polarizer

4 Shield case(front)

5 Shield case(rear)

6 Double coated abhesive tape

7 Reflector

8 Lamp socket

9 CCFL

10 Reflection sheet

11 Light guide plate

12 Prism sheet

13 Deffusion sheet

14 Backlight frame

15 Connector(J.S.T. mfg.:ZHR-4)

16 Harness

Summary

5.1cm (2.0 Type) NTSC/PAL Color LCD Panel (Module with Backlight)

Description

The ACX301AKM is an LCD panel module with back light developed exclusively for the ACX301AK 5.1cm diagonal active matrix TFT-LCD panel addressed by low temperature polycrystalline silicon transistors with built-in peripheral driving circuitry. This module provides full-color representation for NTSC and PAL systems. In addition, RGB dots are arranged in a delta pattern that provides smooth picture quality without fixed color patterns compared to vertical stripe and mosaic patterns.

Source title ACX301AKM Datasheet(PDF) - Sony Corporation

Read ACX301AKM online.