ACSL-7210

ACSL-7210 AVAGO | Alldatasheet

Document overview

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Technical content

Features

• Dual-Channel (Opposite direction orientation)
• High Speed: DC to 25 MBd
• 3.3 V and 5 V CMOS Compatibility
• CMOS input and output
• 25 kV/μs minimum Common Mode Rejection (CMR) at VCM = 1000 V
• Guaranteed AC and DC performance over wide temperature: –40 °C to +105 °C
• Safety and Regulatory Approvals: (pending): - UL 1577 – 3750 Vrms for 1 minute - IEC/EN/DIN EN 60747-5-5 for Reinforced Insulation –

567 VPEAK

Applications

• Digital Fieldbus Isolation: PROFIBUS, CC-Link, DeviceNet, SDS
• Multiplexed Data Transmission
• General Instrument and Data Acquisition
• Computer Peripheral Interface
• Microprocessor System Interface TRUTH TABLE (POSITIVE LOGIC) Input side VDD state Output side VDD state VI LED VO Power Supplied Power Supplied HIGH OFF HIGH LOW ON LOW No Power Power Supplied X OFF HIGH

Description

The ACSL-7210 is a dual-channel bidirectional 25 MBd digital optocoupler utilizes CMOS IC technology and pat - ented packaging technologies to achieve high isolation voltage 3750 V RMS in a < 2 mm low profile narrow-body SOIC-8 package. The device optimizes for bidirectional in- dustrial communication networks such as Fieldbus (PRO - FIBUS) and Serial Peripheral Interface (SPI) applications. The main building blocks of the ACSL-7210 for each chan- nel are a CMOS LED driver IC that is controlled by a CMOS logic input signal, a high speed LED, and a CMOS detector IC. These building blocks allow fast propagation delay of 40 ns and short pulse width distortion of 10 ns maximum. The ACSL-7210 has common-mode noise immunity of typical 35 kV/ μs at 1000 V CM, with UL recognized with isolation voltage of 3750 V RMS for 1 minute, and IEC/EN/ DIN EN 60747-5-5 working insulation voltage VIORM of 567 VPEAK with reinforced insulation. Functional Diagram CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. The components featured in this datasheet are not to be used in military or aerospace applications or environments.

Ordering Information

ACSL-7210 is UL Recognized with 3750 VRMS for 1 minute per UL1577. Part number Option Package Surface Mount Tape & Reel IEC/EN/DIN EN 60747-5-5 QuantityRoHS Compliant ACSL-7210 -00RE SO-8 X 100 per tube -06RE X X 100 per tube -50RE X X 1500 per reel -56RE X X X 1500 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACSL-7210-50RE to order RoHS-compliant Surface Mount 8-pin package in Tape-and-Reel packaging. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Package Outline Drawings 8 7 6 5 4321 0.228 (5.80) 0.244 (6.20) 0.189 (4.80) 0.197 (5.00) 0.150 (3.80) 0.157 (4.00) 0.013 (0.33) 0.020 (0.51) 0.040 (1.016) 0.060 (1.524) 0.004 (0.10) 0.010 (0.25) 0.054 (1.37) 0.069 (1.75) x 45° DIMENSIONS: INCHES (MILLIMETERS) MIN MAX 0.286 (7.27) 0.085 (2.16) 0.025 (0.64 ) LAND PATTERN RECOMMENDATION 0.010 (0.25) 0.020 (0.50) 0.008 (0.19) 0.010 (0.25) 8 ° 0.016 (0.40) 0.050 (1.27) YYWW NNNN DEVICE PART NUMBER A EEE LOT ID LEAD FREE AVAGO DATE CODE

Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used. Regulatory Information The ACSL-7210 will be approved by the following organizations: UL Approval under UL 1577, component recognition program up to VISO = 3750 VRMS. CSA Approval under CSA Component Acceptance Notice #5. IEC/EN/DIN EN 60747-5-5 (Option 06RE only) Insulation and Safety Related Specifications Parameter Symbol ACSL-7210 Units Conditions Minimum External Air Gap (Clearance) L(101) 4.3 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (Creepage) L(102) 4.3 mm Measured from input terminals to output terminals, shortest distance path along body. Minimum Internal Plastic Gap (Internal Clearance) 0.08 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. Tracking Resistance (Comparative Tracking Index) CTI 175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* (Option 06RE) Description Symbol Characteristic UnitACSL-7210 Installation classification per DIN VDE 0110/39, Table 1 for rated mains voltage ≤ 150 Vrms for rated mains voltage ≤ 300 Vrms for rated mains voltage ≤ 600 Vrms I – IV I – IV I – III Climatic Classification 40/105/21 Pollution Degree (DIN VDE 0110/39) 2 Maximum Working Insulation Voltage VIORM 567 Vpeak Input to Output Test Voltage, Method b* VIORM x 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC VPR 1063 Vpeak Input to Output Test Voltage, Method a* VIORM x 1.6=VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC VPR 907 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 6000 Vpeak Safety-limiting values – maximum values allowed in the event of a failure. Case Temperature Input Current Output Power TS IS, INPUT PS, OUTPUT 175 600 mA mW Insulation Resistance at TS, VIO = 500 V RS 109 Ω * Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/ DIN EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test profiles.

Switching Specifications (AC) Over recommended temperature (TA = –40 °C to 105 °C) and supply voltage (4.5 V≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V), (3 All typical specifications are at VDD1 = VDD2 = +3.3 V, TA = 25 °C, unless otherwise specified. Parameter Symbol Min. Typ. Max. Units Test Conditions Propagation Delay Time to Logic Low Output [3] tPHL 27 40 ns CL= 15 pF, CMOS Signal Levels Figures 3,4 Propagation Delay Time to Logic High Output [3] tPLH 25 40 ns CL= 15 pF, CMOS Signal Levels Figures 3,4 Pulse Width tPW 40 ns CL= 15 pF, CMOS Signal Levels Pulse Width Distortion [4] |tPHL - tPLH| PWD 1.8 8 ns 3 V ≤ VDD ≤ 3.6 V CL= 15 pF, CMOS Signal Levels Figures 5, 6 10 ns CL= 15 pF, CMOS Signal Levels Propagation Delay Skew [5] tPSK 20 ns CL= 15 pF, CMOS Signal Levels Output Rise Time (10% – 90%) tR 5.1 ns CL= 15 pF, CMOS Signal Levels Figure 7Output Fall Time (90% - 10%) tF 3.8 ns Common Mode Transient Immunity at Logic High Output [6] |CMH| 25 35 kV/μs VCM = 1000 V, TA = 25 °C VI = VDD1, VO > 0.8 × VDD2 Common Mode Transient Immunity at Logic Low Output [6] |CML| 25 35 kV/μs VCM = 1000 V, TA = 25 °C VI = 0 V, VO < 0.8 V Package Characteristics All typical at TA = 25 °C Parameter Symbol Min. Typ. Max. Units Test Conditions Input-Output Insulation [7,8,9] VISO 3750 VRMS RH < 50% for 1 min. TA = 25 °C Input-Output Resistance [7] RI-O 1012 Ω VI-O = 500 V Input-Output Capacitance CI-O 1 pF f=1 MHz, TA = 25 °C Input Capacitance [10] CI 6 pF Notes: 1. Per channel. 2. LED is ON when VI is low and OFF when VI is high. 3. tPHL propagation delay is measured from the 50% level on the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. tPLH propagation delay is measured from the 50% level on the rising edge of the VI signal to the 50% level of the rising edge of the VO signal. 4. PWD is defined as |tPHL - tPLH|. 5. t PSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions. 6. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining V O > 0.8 V DD2. CML is the maximum common mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges. 7. Device is considered a two-terminal device: pins 1, 2, 3, and 4 are shorted together and pins 5, 6, 7, and 8 are shorted together. 8. In accordance with UL1577, ACSL-7210 is proof-tested by applying an insulation test voltage ≥ 4500 VRMS for 1 second (leakage detection current limit, II-O ≤ 5 μA). 9. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating, refer to your equipment level safety specification or Avago Technologies Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage. ” 10. CI is the capacitance measured at pin 3 or pin 7 (VI).

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2015 Avago Technologies. All rights reserved. Figure 9. Isolated SPI between master and slave devices using ACSL-7210 and ACPL-077L munication between master and slave devices using ACSL-7210 and ACPL-077L.