ACSL-6400

ACSL-6XX0 AVAGO | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 17

Technical content

Features

• Available in dual, triple and quad channel configura- tions
• Bi-directional
• Wide supply voltage range: 3.0V to 5.5V
• High-speed: 15 MBd typical, 10 MBd minimum
• 10 kV/µs minimum Common Mode Rejection (CMR) at Vcm = 1000V
• LSTTL/TTL compatible
• Safety and regulatory approvals – 2500Vrms for 1 min per UL1577 – cUL (CSA Component Acceptance Notice 5A) – IEC/EN/DIN EN 60747-5-5
• 16 Pin narrow-body SOIC package for triple and quad channel
• -40 to 100°C temperature range

Applications

• Serial Peripheral Interface (SPI)
• Inter-Integrated Interface (I2C)
• Full duplex communication
• Isolated line receiver
• Microprocessor system interfaces
• Digital isolation for A/D and D/A conversion
• Instrument input/output isolation
• Ground loop elimination CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. The components featured in this datasheet are not to be used in military or aerospace applications or environments.

Device Number Channel Configuration Package ACSL-6210 Dual, Bi-Directional\` 8-pin Small Outline ACSL-6300 Triple, All-in-One 16-pin Small Outline ACSL-6310 Triple, Bi-Directional, 2/1 16-pin Small Outline ACSL-6400 Quad, All-in-One 16-pin Small Outline ACSL-6410 Quad, Bi-Directional, 3/1 16-pin Small Outline ACSL-6420 Quad, Bi-Directional, 2/2 16-pin Small Outline Pin Description Symbol Description Symbol Description VDD1 Power Supply 1 GND1 Power Supply Ground 1 VDD2 Power Supply 2 GND2 Power Supply Ground 2 ANODEx LED Anode NC Not Connected CATHODEx LED Cathode VOX Output Signal Truth Table (Positive Logic) LED OUTPUT ON L OFF H

Ordering Information

ACSL-6xx0 is UL Recognized with 2500 Vrms for 1 minute per UL1577 and is approved under CSA Component Accep- tance Notice #5, File CA 88324. Part number RoHS Compliant [1] Package Surface Mount Tape & Reel IEC/EN/DIN EN 60747-5-5 Quantity ACSL-6210 -00RE SO-8 X 100 per tube -06RE SO-8 X X 100 per tube -50RE SO-8 X X 1500 per reel -56RE SO-8 X X X 1500 per reel ACSL-6300 ACSL-6310 ACSL-6400 ACSL-6410 ACSL-6420 -00TE SO-16 X 50 per tube -06TE SO-16 X X 50 per tube -50TE SO-16 X X 1000 per reel -56TE SO-16 X X X 1000 per reel Note 1: The ACSL-6xx0 product family is only offered in RoHS compliant option. To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACSL-6210-56RE refers to ordering a Surface Mount SO-8 package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval in RoHS compliant. Example 2: ACSL-6400-00TE refers to ordering a Surface Mount SO-16 package product in tube packaging and in RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.

ACSL-6210 - Dual-Ch, Bi-Dir ACSL-6300 - Triple-Ch, All-in-One ACSL-6310 - Triple-Ch, Bi-Dir (2/1) ACSL-6400 - Quad-Ch, All-in-One ACSL-6210 ANODE1 VDD2 V02 GND2 CATHODE1 GND1 CATHODE2 V01 VDD1 ANODE2 ACSL-6420 - Quad-Ch, Bi-Dir (2/2)ACSL-6410 - Quad-Ch, Bi-Dir (3/1) GND ACSL-6300 VDD V01 V02 V03 NC VDD GND ANODE1 CATHODE1 ANODE2 CATHODE2 ANODE3 CATHODE3 NC NC ACSL-6310 16GND1 NC V03 VDD1 ANODE1 CATHODE1 ANODE2 CATHODE2 NC NC ANODE3 CATHODE3 VDD2 V01 V02 GND2 ACSL-6410 16GND1 CATHODE1 V04 VDD1 ANODE1 CATHODE2 ANODE2 CATHODE3 ANODE3 CATHODE4 ANODE4 GND2 V01 V02 V03 VDD2 GND2 ACSL-6420 ANODE1 CATHODE1 ANODE2 CATHODE2 ANODE3 CATHODE3 ANODE4 CATHODE4 GND1 V04 V03 VDD1 VDD2 V01 V02 GND2 ACSL-6400 16ANODE1 CATHODE1 ANODE2 CATHODE2 ANODE3 CATHODE3 ANODE4 CATHODE4 GND VDD V01 V02 V03 V04 VDD GND

ACSL-6210 - Dual-Ch, Bi-Dir ACSL-6300 - Triple-Ch, All-in-One ACSL-6310 - Triple-Ch, Bi-Dir (2/1) Shield GND2 CATHODE1 VDD2 ANODE2 Vo2 Shield1 ANODE1 GND1 CATHODE2 VDD1 Vo1 Shield 14ANODE1 CATHODE1 VDD GND Vo1 Shield CATHODE2 ANODE2 Vo2 Shield CATHODE3 ANODE3 VDD GND Vo3 Shield1 ANODE3 GND1 VDD1 Vo3 CATHODE3 Shield 11ANODE1 CATHODE1 VDD2 Vo1 Shield CATHODE2 ANODE2 GND2 Vo2 The ACSL-6xx0 series optocouplers feature the GaAsP LEDs with proprietary back emission design. They offer the designer a broad range of input drive current, from 7 mA to 15 mA, thus providing greater flexibility in designing the drive circuit. The output detector integrated circuit (IC) in the opto - coupler consists of a photodiode at the input of a two- stage amplifier that provides both high gain and high bandwidth. The secondary amplifier stage of the detector IC feeds into an open collector Schottky-clamped transis- tor. The entire output circuit is electrically shielded so that any common-mode transient capacitively coupled from the LED side of the optocoupler is diverted from the photodiode to ground. With this electric shield, the optocoupler can withstand transients that slopes up to 10,000V/µs, and am- plitudes up to 1,000V.

ACSL-6410 - Quad-Ch, Bi-Dir (3/1) ACSL-6420 - Quad-Ch, Bi-Dir (2/2) Schematic Diagrams, continued Shield 1GND1 Vo4 Shield VDD1 Vo3 ANODE3 CATHODE3 ANODE4 CATHODE4 Shield 11ANODE1 CATHODE1 VDD2 Vo1 Shield CATHODE2 ANODE2 GND2 Vo2 Shield GND2 Vo1 Shield Vo2 Shield VDD2 GND2 Vo3 4ANODE1 ANODE2 CATHODE2 ANODE3 CATHODE3 Shield1 GND1 CATHODE1 VDD1 Vo4 ANODE415 CATHODE416 Shield 14ANODE1 CATHODE1 VDD GND Vo1 Shield CATHODE2 ANODE2 Vo2 Shield CATHODE3 ANODE3 Vo3 Shield CATHODE4 ANODE4 VDD GND Vo4 ACSL-6400 - Quad-Ch, All-in-One

ACSL-6210 Small Outline SO-8 Package ACSL-6300, ACSL-6310, ACSL-6400, ACSL-6410 and ACSL-6420 Small Outline SO-16 Package Package Outline Drawings 8 7 6 5 4321 0.228 (5.80) 0.244 (6.20) 0.189 (4.80) 0.197 (5.00) 0.150 (3.80) 0.157 (4.00) 0.013 (0.33) 0.020 (0.51) 0.040 (1.016) 0.060 (1.524) 0.004 (0.10) 0.010 (0.25) 0.054 (1.37) 0.069 (1.75) x 45° DIMENSIONS: INCHES (MILLIMETERS) MIN MAX 0.286 (7.27) 0.085 (2.16) 0.025 (0.64 ) LAND PATTERN RECOMMENDATION 0.010 (0.25) 0.020 (0.50) 0.008 (0.19) 0.010 (0.25) 8 ° 0.016 (0.40) 0.050 (1.27) YYWW NNNN DEVICE PART NUMBER A EEE LOT ID LEAD FREE AVAGO DATE CODE 0.228 (5.791) 0.244 (6.197) 0.386 (9.802) 0.394 (9.999) 0.152 (3.861) 0.157 (3.988) 0.013 (0.330) 0.020 (0.508) 0.040 (1.016) 0.060 (1.524) 0.050 (1.270) 0.060 (1.524) 0.054 (1.372) 0.068 (1.727) 0.004 (0.102) 0.010 (0.249) 0.016 (0.406) 0.050 (1.270) 0.010 (0.245) 0.020 (0.508) 0.008 (0.191) 0.010 (0.249) x 45° 0 - 8° TYP. DIMENSIONS: INCHES (MILLIMETERS) MIN MAX 0.286 (7.27) 0.085 (2.16) 0.025 (0.64 ) LAND PATTERN RECOMMENDATION YYWW NNNN DEVICE PART NUMBERA EEE LOT ID LEAD FREE AVAGO DATE CODE 1 8

Insulation and Safety Related Specifications Parameter Symbol Value Units Conditions Minimum External Air Gap (Clearance) L(I01) 4.9 mm Measured from input terminals to output terminals, shortest distance through air Minimum Externa l Tracking (Creepage) L(I02) 4.5 mm Measured from input terminals to output terminals, shortest distance path through body Minimum Internal Plastic Gap (Internal Clearance) 0.08 mm Insulation thickness between emitter and detector; also known as distance through insulation Tracking Resistance (Comparative Tracking Index) CTI 175 Volts DIN IEC 112/VDE0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Reflow Soldering Profile The recommended reflow soldering conditions are per JEDEC Standard J-STD-020 (latest revision). Non-halide flux should be used. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* (Option x6xx) Description Symbol Characteristic Unit Installation classification per DIN VDE 0110, Table 1 for rated mains voltage ≤ 150 Vrms for rated mains voltage ≤ 300 Vrms I – IV I – III Climatic Classification 40/100/21 Pollution Degree (DIN VDE 0110/39) 2 Maximum Working Insulation Voltage VIORM 567 Vpeak Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC VPR 1063 Vpeak Input to Output Test Voltage, Method a* VIORM x 1.6 = VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC VPR 907 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 4000 Vpeak Safety-limiting values – maximum values allowed in the event of a failure. Case Temperature Input Current Output Power TS IS, INPUT PS, OUTPUT 175 150 600 mA mW Insulation Resistance at TS, VIO = 500 V RS >109 W * Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/DIN EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test profiles. ** Refer to following figure for dependence of PS and IS on ambient temperature. Ts-Case Temperature,°C Output Power-Ps Input Power-lp 700 600 500 400 300 200 100 0 2005025 75 100 125 150 175 Is (mA) Ps (mW)

Parameter Symbol Min. Max. Units Storage Temperature Ts -55 125 °C Operating Temperature TA -40 100 °C Supply Voltage (1 Minute Maximum) VDD1 , VDD2 7 V Reverse Input Voltage (Per Channel) VR 5 V Output Voltage (Per Channel) VO 7 V Average Forward Input Current[1] (Per Channel) IF 15 mA Output Current (Per Channel) IO 50 mA Input Power Dissipation[2] (Per Channel) PI 27 mW Output Power Dissipation[2] (Per Channel) PO 65 mW Recommended Operating Conditions Parameter Symbol Min. Max. Units Operating Temperature TA -40 100 °C Input Current, Low Level[3] I FL 0 250 µA Input Current, High Level[4] I FH 7 15 mA Supply Voltage VDD1, VDD2 3.0 5.5 V Fan Out (at RL = 1kΩ) N 5 TTL Loads Output Pull-up Resistor RL 330 4k Ω Notes: 1. Peaking circuits may produce transient input currents up to 50 mA, 50 ns max. pulse width, provided average current does not exceed its max. values. 2. Derate total package power dissipation, PT linearly above +95°C free-air temperature at a rate of 1.57mW/°C for the SO8 package mounted on low conductivity board per JESD 51-3. Derate total package power dissipation, PT linearly above +80°C free-air temperature at a rate of 1.59 mW/°C for the SO16 package mounted on low conductivity board per JESD 51-3. PT= number of channels multiplied by (PI+PO). 3. The off condition can be guaranteed by ensuring that VFL ≤ 0.8V. 4. The initial switching threshold is 7 mA or less. It is recommended that minimum 8 mA be used for best performance and to permit guardband for LED degradation. 100 0 20 40 60 80 100 120 T A - Ambient Temperature - °C PT - Total Power Dissipation per channel - mW so-16 package so-8 package

All typical specifications are at TA = +25°C , VDD1 = VDD2 = +3.3V. Parameter Symbol Min. Typ. Max. Units Test Conditions Input Threshold Current ITH 2.7 7.0 mA IOL(Sinking)=13 mA, VO = 0.6V High Level Output Current IOH 4.7 100.0 µA IF = 250 µA, VO = 3.3V Low Level Output Voltage VOL 0.36 0.68 V IOL(Sinking) = 13 mA, IF = 7mA High Level Supply Current IDDH 3.2 5.0 mA IF = 0 mA (per channel) Low Level Supply Current IDDL 4.6 7.5 mA IF = 10 mA (per channel) Input Forward Voltage VF 1.25 1.52 1.80 V IF = 10 mA, TA = 25°C Input Reverse Breakdown Voltage BVR 5.0 V IR = 10 µA Input Diode Temperature Coefficient ∆VF / ∆TA -1.8 mV/°C IF = 10 mA Input Capacitance CIN 80 pF f = 1 MHz, VF = 0V Switching Specifications specified. All typical specifications are at TA = +25°C , VDD1 = VDD2 = +3.3V. Parameter Symbol Min. Typ. Max. Units Test Conditions Maximum Data Rate 10 15 MBd RL = 350Ω, CL = 15 pF Pulse Width tPW 100 ns RL = 350Ω, CL = 15 pF Propagation Delay Time tPLH 52 100 ns RL = 350Ω, CL = 15 pF to Logic High Output Level[5] Propagation Delay Time tPHL 44 100 ns RL = 350Ω, CL = 15 pF to Logic Low Output Level[6] Pulse Width Distortion |tPHL – tPLH| |PWD| 8 35 ns RL = 350Ω, CL = 15 pF Propagation Delay Skew[7] t PSK 40 ns RL = 350Ω, CL = 15 pF Output Rise Time (10 – 90%) tR 35 ns RL = 350Ω, CL = 15 pF Output Fall Time (10 – 90%) tF 12 ns RL = 350Ω, CL = 15 pF Logic High Common Mode |CMH| 10 kV/µs Vcm = 1000V, IF = 0 mA, Transient Immunity [8] VO = 2.0V, RL = 350Ω, TA = 25°C Logic Low Common Mode |CML| 10 kV/µs Vcm = 1000V, IF = 8 mA, Transient Immunity [8] VO = 0.8V, RL = 350Ω, TA = 25°C Notes: 5. t PLH is measured from the 4.0 mA level on the falling edge of the input pulse to the 1.5V level on the rising edge of the output pulse. 6. t PHL is measured from the 4.0 mA level on the rising edge of the input pulse to the 1.5V level on the falling edge of the output pulse. 7. t PSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature and specified test condi- tions. 8. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 2.0V. CML is the maximum common mode voltage slew rate that can be sustained while maintaining VO < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges.

All typical specifications are at TA = +25°C, VDD1 = VDD2 = +5.0V. Parameter Symbol Min. Typ. Max. Units Test Conditions Input Threshold Current ITH 2.7 7.0 mA I OL(Sinking)=13 mA, VO= 0.6V High Level Output Current IOH 3.8 100.0 µA IF = 250 µA, VO= 5.5V Low Level Output Voltage VOL 0.36 0.6 V IOL(Sinking)=13 mA, IF=7 mA High Level Supply Current IDDH 4.3 7.5 mA I F = 0 mA (per channel) Low Level Supply Current IDDL 5.8 10.5 mA IF = 10 mA (per channel) Input Forward Voltage VF 1.25 1.52 1.8 V IF = 10 mA, TA = 25°C Input Reverse Breakdown Voltage BVR 5.0 V IR = 10 µA Input Diode Temperature Coefficient ∆VF / ∆TA -1.8 mV/°C IF = 10 mA Input Capacitance CIN 80 pF f = 1 MHz, VF = 0V Switching Specifications specified. All typical specifications are at TA=+25°C, VDD1 = VDD2 = +5.0V. Parameter Symbol Min. Typ. Max. Units Test Conditions Maximum Data Rate 10 15 MBd RL = 350Ω, CL =15 pF Pulse Width tPW 100 ns RL = 350Ω, CL =15 pF Propagation Delay Time tPLH 46 100 ns RL = 350Ω, CL =15 pF to Logic High Output Level[5] Propagation Delay Time tPHL 43 100 ns RL = 350Ω, CL =15 pF to Logic Low Output Level[6] Pulse Width Distortion |tPHL – tPLH| |PWD| 5 35 ns RL = 350Ω, CL =15 pF Propagation Delay Skew[7] t PSK 40 ns RL = 350Ω, CL =15 pF Output Rise Time (10 – 90%) tR 30 ns RL = 350Ω, CL =15 pF Output Fall Time (10 – 90%) tF 12 ns RL = 350Ω, CL =15 pF Logic High Common Mode |CMH| 10 kV/µs Vcm= 1000V, IF=0 mA, Transient Immunity [8] VO = 2.0V, RL=350Ω, TA = 25°C Logic Low Common Mode |CML| 10 kV/µs Vcm= 1000V, IF= 8 mA, Transient Immunity [8] VO = 0.8V, RL= 350Ω, TA = 25°C Notes: 5. tPLH is measured from the 4.0 mA level on the falling edge of the input pulse to the 1.5V level on the rising edge of the output pulse. 6. t PHL is measured from the 4.0 mA level on the rising edge of the input pulse to the 1.5V level on the falling edge of the output pulse. 7. t PSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature and specified test condi- tions. 8. CM H is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 2.0V. CML is the maximum common mode voltage slew rate that can be sustained while maintaining VO < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges.

All specifications are at TA=+25°C. Parameter Symbol Min. Typ. Max. Units Test Conditions Input-Output Momentary SO8 VISO 2500 VRMS RH ≤ 50%, t = 1 min Withstand Voltage[9] SO16 V ISO 2500 RH≤50%, t = 1 min Input-Output Insulation [10] [11] SO8 II-O 5 µA 45% RH, t=5 sec, VI-O= 3kV DC SO16 I I-O 5 45% RH, t=5 sec, V I-O=3kV DC Input-Output Resistance[10] SO8 RI-O 10 9 10 11 Ω VI-O = 500V DC SO16 R I-O 10 9 10 11 VI-O = 500V DC Input-Output Capacitance[10] SO8 CI-O 0.7 pF f = 1 MHz SO16 C I-O 0.7 f = 1 MHz Input-Input Insulation SO8 II-I 0.005 µA RH ≤ 45%, t=5 sec, VI-I=500V Leakage Current[12] SO16 I I-I 0.005 RH≤45%, t=5 sec, VI-I=500V Input-Input Resistance[12] SO8 R I-I 10 11 Ω RH≤45%, t= 5 sec, VI-I=500V SO16 R I-I 10 11 RH≤45%, t=5 sec, VI-I =500V Input-Input Capacitance[12] SO8 CI-I 0.1 pF f = 1 MHz SO16 C I-I 0.12 f = 1 MHz Electrostatic Discharge Sensitivity This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Avago recommends that all integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from per- formance degradation to complete failure. Notes: 9. V ISO is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For continuous voltage rating, refer to the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table (if applicable), the equipment level safety specification or Avago Applica- tion Note 1074 entitled “Optocoupler Input-Output Endurance Voltage. ” 10. Measured between each input pair shorted together and all output connections for that channel shorted together. 11. In accordance to UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 3000 Vrms for 1 sec (leakage detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table, if applicable. 12. Measured between inputs with the LED anode and cathode shorted together.

the local temperature of the LED can rise, which in turn may affect the long-term reliability of the device. When designing the input circuit, one must also ensure that the input reverse voltage does not exceed 5 V. If the optocoupler is subjected to reverse voltage transients or accidental situations that may cause a reverse voltage to be applied, thus an anti- parallel diode across the LED is recommended. Suggested Input Circuits for Driving the LED Figures 18, 19, and 20 show some of the several techniques for driving the ACSL-6xx0 LED. Figure 18 shows the rec - ommended circuit when using any type of TTL gate. The buffer PNP transistor allows the circuit to be used with TTL or CMOS gates that have low sinking current capabil - ity. One advantage of this circuit is that there is very little variation in power supply current due to the switching of the optocoupler LED. This can be important in high- resolution analog-to-digital (A/D) systems where ground loop currents due to the switching of the LEDs can cause distortion in the A/D output. Figure 18. TTL interface circuit for the ACSL-6xx0.

Application Information

The ACSL-6xx0 series has the ON condition defined by current, and the OFF condition defined by voltage. In order to guarantee that the optocoupler is OFF, the forward voltage across the LED must be less than or equal to 0.8 volt for the entire operating temperature range. This has direct implications for the input drive circuit. If the design uses a TTL gate to drive the input LED, then one has to ensure that the gate output voltage is sufficient to cause the forward voltage to be less than 0.8 volt. The typical threshold current for the ACSL-6xx0 series optocouplers is 2.7 mA; however, this threshold could increase over time due to the aging effects of the LED. Drive circuit arrange - ments must provide for the ON state LED forward current of at least 7 mA, or more if faster operation is desired. Maximum Input Current and Reverse Voltage The average forward input current should not exceed the 15 mA Absolute Maximum Rating as stated; however, peaking circuits with transient input currents up to 50 mA are allowed provided the average current does not exceed 15 mA. If the input current maximum rating is exceeded,

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. longest propagation delay,either tPLH or tPHL. tainty in the rest of the circuit does not cause a problem. Figure 23. Propagation delay skew – tPSK. Figure 24. Parallel data transmission example. output to change from high to low (see Figure 16).