ACS37600

ACS37600 ALLEGRO | Alldatasheet

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Technical content

The Allegro ACS37600 is a linear sensor IC designed to be used in conjunction with a ferromagnetic core to provide a highly accurate current sensor suitable for industrial, commercial, and communications applications. The device consists of a precise, low-offset, chopper-stabilized Hall-effect front end. Magnetic flux orthogonal to the IC package surface is sensed by the integrated Hall and converted into a proportional voltage. A very wide sensitivity range allows current sensor module makers to use this IC for a <20 A or a >1000 A module. A selectable bandwidth from 100 kHz to >400 kHz makes the device ideal for fast switching applications and applications where low noise is required. A user-programmable, bidirectional reference voltage pin (VREF) enables constant monitoring of the zero-current voltage and easy interfacing with 3.3 V and 5 V ADCs. The device includes a user-programmable overcurrent fault pin with a 1.5 μs (typ) response time for fast short-circuit protection. ACS37600-DS, Rev. 3 MCO-0000961

• Industry-leading noise performance
• User-programmable bandwidth (100 to 400 kHz) for easy tradeoff between speed and noise
• Very fast response time (<1.25 μs typ.)
• Wide sensing range (0.8 to 18 mV/G)
• Factory-programmed sensitivity and offset over temperature
• User-programmable sensitivity and offset
• User-programmable sensitivity over temperature for ferromagnetic core drift compensation
• User-programmable overcurrent fault (OCF) pin □ 1.5 μs (typ) OCF response time
• User-programmable, bidirectional reference pin (VREF) for full control over offset levels
• Non-ratiometric output for immunity to noisy supplies
• Undervoltage and overvoltage detection
• High output drive current (15 mA)
• Low power mode for reduced ICC
• VCC pin survives exposure up to 15 V
• Monolithic Hall IC for high reliability
• Surface mount, small footprint, low-profile TSSOP8 package High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current Sensing Figure 1: Typical Application Circuit for ACS37600 ACS37600 Continued on next page... FEATURES AND BENEFITS DESCRIPTION March 28, 2023 PACKAGE: 8-pin TSSOP package (suffix LU) Not to scale GND* VOUT VREF* GND/NC OCF GND/NC GND/NC VCC* ACS376001 ROCF CBYB 0.1 µF RLOAD CLOAD RREF CREF * Required for communication. 5 V TYPICAL APPLICATIONS
• Current sensing modules
• Solar (MPPT, combiner box)
• Motor control
• Uninterruptable power supplies (UPS)
• Smart fuse
• Overcurrent detection
• Power supplies

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A. www.allegromicro.com SELECTION GUIDE Part Number Factory-Trimmed Sensitivity (mV/G) Factory-Programmed Operating Range (G) Programmable Sens Range (mV/G) TA (°C) Packing [2] Bidirectional Unidirectional [1] ACS37600KLUA-1P5B5-C 1.5 ±1333 0 to 2667 0.8 [3] to 1.7 –40 to 125 4000 pieces per 13-inch reel ACS37600KLUA-003B5-C 3 ±667 0 to 1333 1.7 to 3.5 ACS37600KLUA-006B5-C 6 ±333 0 to 667 3.5 to 7.2 ACS37600KLUA-013B5-C 13.5 ±148 0 to 296 7.2 to 18 ACS37600KLUA-1P5B5-CP –1.5 ±1333 0 to –2667 –0.8 [3] to –1.7 ACS37600KLUA-003B5-CP –3 ±667 0 to –1333 –1.7 to –3.5 ACS37600KLUA-006B5-CP –6 ±333 0 to –667 –3.5 to –7.2 ACS37600KLUA-013B5-CP –13.5 ±148 0 to –296 –7.2 to –18 [1] This range applies if the VREF pin is overdriven to 0.5 V. If this range is desired without overdriving the VREF pin, contact an Allegro representative. [2] Contact an Allegro representative for additional packing options. [3] Refer to operating range table for high gauss performance. Part Numbering Specification ACS37600KLUATR-1P5B5-CP C = Customer Programmable P = Inverted Polarity Supply Operating Level, VCC, 5 = 5 V B = Bidirectional, U = Un directional Optimized Accuracy Range, Factory-Programmed Sens, 1P5 = 1.5 mV/G, 013 = 13.5 mV/G Packing Type: TR = Tape and Reel Package Type, LUA = 8 pin TSSOP Package Operating Temperature Range, TA, K = – 40°C to 125°C Allegro Current Sensor 5-Digit Part Number i DESCRIPTION (continued) The sensitivity and offset drift over temperature are factory programmed at Allegro to provide a highly accurate solution across the full temperature range. The ACS37600 is customer programmable. The absolute value of sensitivity and offset can be programmed after manufacturing. Additionally, customers can program the sensitivity over temperature to compensate for ferromagnetic core drifts, enabling industry- leading current sensor accuracy. A non-ratiometric output immune to supply noise, the ability to survive up to 15 V on the supply pin, and a stellar ESD performance make the ACS37600 ideal for applications where reliability and robustness are required. The IC is offered in a low-profile 8-pin surface mount TSSOP package (thin-shrink small outline package, suffix LU) that is lead (Pb) free, with 100% matte tin leadframe plating.

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Table of Contents Performance Characteristics: Factory and Performance Characteristics: Reprogrammed Including Lifetime ...12 Overvoltage/Undervoltage Overvoltage and Undervoltage Gain Temperature Coefficient Step Size (STEPSENS_SLOPE) ..25

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Notes Rating Unit Supply Voltage VCC 15 V Reverse Supply Voltage VRCC –0.5 V Output Voltage VOUT (VCC + 0.5) ≤ 15 V Reverse Output Voltage VROUT –0.5 V Reference and OCF Voltage VREF, VOCF (VCC + 0.5) ≤ 6.5 V Reverse Reference and OCF Voltage VRREF, VROCF –0.5 V Output Source IOUT VOUT connected to GND 30 mA Output Sink IIN VOUT connected to VCC –30 mA Operating Ambient Temperature TA Range L –40 to 150 °C Junction Temperature TJ(MAX) 165 °C Storage Temperature Tstg –65 to 165 °C Maximum Field Range B Field of which the device will respond ±3000 G OPERATING PARAMETERS Characteristics Symbol Test Conditions Min. Typ. Max. Unit Operational Ambient Temperature Range TA L temperature range –40 – 150 °C Optimal Ambient Temperature Range TA K temperature range –40 – 125 °C Optimal Absolute Field Range BOG Performance specifications are guaranteed at or within this limit of |B| 0 – 1625 G Nominal Absolute Field Range BNG Linearity degrades within this |B| range 1650 – 2500 G Extended Absolute Field Range BEG The output may still respond but linearity degrades significantly within this |B| range 2500 – 3000 G GND VOUT VREF GND OCF GND/NC GND/NC VCC Pinout List Number Name Description 6, 7 GND/NC No connect or Ground; connect to GND for optimal ESD performance 1, 4 GND Device ground (Pin 1 is primary GND )

5 VCC Device supply

2 VOUT Device analog output

3 VREF Reference voltage for output

8 OCF Overcurrent fault (OCF) reporting pin (open drain)

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com FUNCTIONAL BLOCK DIAGRAM External Inputs External Outputs ACS37600 To All Subcircuits Fault Path Signal Path VREF Path Programming Path EEPROM Path VCC * GND * VREF * VOUT OCF Hall Plate Overvoltage/ Undervoltage Detection Regulator EEPROM/ Digital Block BWFault Fault Analog Filtering Chopping T.C. Fine Sens Fault Logic * Indicates Communication Pin

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com ELECTRICAL CHARACTERISTICS: Valid through the full operating temperature range, TA, CBYP = 0.1 µF, VCC = 5 V, eco_mode = 0, unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit Supply Voltage VCC Standard operating voltage 4.5 5 5.5 V Supply Current ICC VCC = 4.5 to 5.5 V, output open, factory default ‒ 16 23 mA VCC = 4.5 to 5.5 V, output open, eco_mode = 1 ‒ 14 23 mA Output Capacitive Load CLOAD VOUT to GND ‒ ‒ 4.7 nF Output Resistive Load RLOAD VOUT to GND or VOUT to VCC 2 ‒ ‒ kΩ Reference Resistive Load RREF VREF to GND 200 ‒ ‒ kΩ Reference Capacitive Load CREF VREF in input/output mode, VREF to GND 0.5 ‒ 47 nF VREF in output mode only, VREF to GND 0.5 ‒ 4.7 nF Overcurrent Fault Pull-Up Resistor ROCF OCF to VCC or other pull-up node 10 ‒ ‒ kΩ Power-On Reset Voltage [1] VPOR(H) Device powers on; VCC ramp rate = +1 V/ms from GND 3.6 3.8 3.9 V VPORHys VPOR(H) – VPOR(L); TA = 25°C 0.25 0.4 0.56 V VPOR(L) Device powers off; VCC ramp rate = –1 V/ms from 5 V 3.2 3.4 3.5 V Power-On Reset Release Time tPORR Time from VUVD(H)[1] until output and reference is released ‒ 95 ‒ µs Power-On Reset: Output Settle Time tPOR(OUT) Time from when tPORR until 90% VOUT – VREF stable state with 0 G applied; CLOAD = 4.7 nF, no RLOAD ‒ 8 ‒ µs Power-On Reset: Reference Settle Time tPOR(REF) VREF in output/input or output only mode; time from tPORR until 90% reference steady state with 0 G applied; no RREF, CREF = 4.7 nF ‒ 17 ‒ µs Power-On Delay tPOD TA = 25°C, VREF in input only mode, driven to 2.5 V; time from VUVD(H)[1] until 90% VOUT stable state with 0 G applied; CLOAD = 4.7 nF, no RLOAD ‒ 103 ‒ µs TA = 25°C, VREF in input/output or output only mode, driving to

2.5 V; time from VUVD(H)[1] until 90% VOUT stable state with 0 G

applied; CLOAD and& CREF = 4.7 nF, no RLOAD or RREF ‒ 112 ‒ µs Overcurrent Fault Startup Time tPOR(OCF) Time from VUVD(H)[1] until fault is functional ‒ 105 ‒ µs Temperature Compensation Update Rate tUR ‒ 8 ‒ ms Undervoltage Detection VUVD(H) VOUT = nominal operation; TA = 25°C; VCC ramp rate = + 1 V/ms from GND 4 ‒ 4.4 V VUVDHys VUVD(H) – VUVD(L); TA = 25°C ‒ 0.4 ‒ V VUVD(L) VOUT = 0 V; TA = 25°C; VCC ramp rate = –1 V/ms from 5 V 3.6 ‒ 4 V UVD Enable Delay Time tUVD(E) Time measured from falling VCC < VUVD(E) to VOUT pulled low 35 64 90 µs UVD Disable Delay Time tUVD(D) Time measured from rising VCC > VUVD(D) to VOUT is 90% VREF stable state with 0 G applied ‒ 8 ‒ µs Overvoltage Detection VOVD(H) VOUT = high Z[2]; TA = 25°C; VCC ramp rate = +1 V/ms from 5 V 7.2 7.6 8 V VOVDHys VUVD(H) – VUVD(L); TA = 25°C ‒ 1 ‒ V VOVD(L) VOUT = back to nominal operation; TA = 25°C; VCC ramp rate = –1 V/ms from 8.1 V 6.1 6.6 7 V OVD Enable Delay Time tOVD(E) Time measured from falling VCC > VOVD(E) to VOUT becoming high Z 35 64 90 µs OVD Disable Delay Time tOVD(D) Time measured from rising VCC < VOVD(D) to VOUT is 90% VREF stable state with 0 G applied ‒ 7 ‒ µs Suppy Zener Clamp Voltage VZ TA = 25°C, ICC = 30 mA ‒ 20 ‒ V [1] POR release threshold is either VPOR(H) if uvd_dis = 1 or VUVD(H) if uvd_dis = 0. Factory default setting is uvd_dis = 0. [2] Reverse output voltage maximum can be exceeded if VOUT is pulled down to –6 V.

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com ELECTRICAL CHARACTERISTICS (continued): Valid through the full operating temperature range, TA, CBYP = 0.1 µF, VCC = 5 V, eco_mode = 0, unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit VOUT OPERATING CHARACTERISTICS Output Voltage Operating Range VOOR Linear operating range 0.5 ‒ 4.5 V Output Saturation Voltage VSAT(HIGH) VCC = 5 V, RLOAD = 2 kΩ pull-down VCC – 0.3 ‒ ‒ V VSAT(LOW) VCC = 5 V, RLOAD = 2 kΩ pull-up 0 ‒ 0.4 V Output Saturation @ 10 mA Current Load (Pull-Up Config.) VSAT(HIGH) VCC = 5 V, IL = –10 mA, TA = 25°C 4.5 4.7 ‒ V VSAT(LOW) VCC = 5 V, IL = 10 mA, TA = 25°C ‒ 0.2 0.4 V DC Output Resistance ROUT ‒ 2 5 Ω Output Maximum Drive Current IOD Drive mode: Turbo ‒ ‒ 15 mA Drive mode: Economy ‒ ‒ 7.5 mA Rise Time tRISE TA = 25°C, CL = 1 nF, 1 µs input step 1 V output swing 10% to 90% VOUT BW = 100 kHz ‒ 2.4 3.5 µs BW = 250 kHz ‒ 1.65 2.5 µs BW = 400 kHz ‒ 1.2 2 µs BW = 450 kHz ‒ 1.15 ‒ µs Propagation Delay tPD TA = 25°C, CL = 1 nF, 1 µs input step 1 V output swing, 10% input to 10% output BW = 100 kHz ‒ 0.9 1.5 µs BW = 250 kHz ‒ 0.85 1.4 µs BW = 400 kHz ‒ 0.75 1.3 µs BW = 450kHz ‒ 0.7 ‒ µs Response Time tRESPONSE TA = 25°C, CL = 1 nF, 1 µs input step 1 V output swing 90% input to 90% output BW = 100 kHz ‒ 3.5 6 µs BW = 250 kHz ‒ 2.4 3.5 µs BW = 400 kHz ‒ 1.25 2.5 µs BW = 450kHz ‒ 1.2 ‒ µs Overshoot VOS TA = 25°C, CL = 4.7 nF, 1 µs input step 1 V output swing bw_sel = 0, 1, 2 ‒ 5 10 % bw_sel = 3 ‒ 5 15 % Settling Time tSETTLE VOUT within 3% VOUT Step, TA = 25°C, CL = 1 nF, 1 µs input step 1 V output swing ‒ ‒ 10 µs Input Referred Noise Density BND VCC = 5.0 V, Input Referred, @ 400 kHz TA = 25°C ‒ 1.21 1.64 mG/√Hz TA = 125°C ‒ 1.69 2.25 mG/√Hz Output Noise VN VCC = 5.0 V, CL = 1 nF, Sens = 3 mV/G, BW = 400kHz TA = 25°C ‒ 2.83 ‒ mVRMS TA = 125°C ‒ 3.61 ‒ mVRMS Sensitivity Symmetry Error ESYM –1 0.25 1 % Nonlinearity ELIN TA = –40°C to 125°C, 2500 G > |B| > 1650 G –1 – 1 % Offset Power Supply Rejection Ratio PSRRO AC VCC = 5 V ± 10%, TA = 25°C DC to 1 kHz – 40 – dB 1 to 20 kHz – 30 – dB 20 to 60 kHz – 20 – dB Sensitivity Power Supply Rejection Ratio PSRRS AC VCC = 5 V ± 10%, TA = 25°C DC to 1 kHz – 40 – dB 1 to 20 kHz – 30 – dB 20 to 60 kHz – 20 – dB Power Supply Offset Error VPS DC VCC = 5.5 V and 4.5 V –5 ±0.25 5 mV Power Supply Sensitivity Error EPS DC VCC = 5.5 V and 4.5 V –0.5 – 0.5 %

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com ELECTRICAL CHARACTERISTICS (continued): Valid through the full operating temperature range, TA, CBYP = 0.1 µF, VCC = 5 V, eco_mode = 0, unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit VREF OUTPUT CHARACTERISTICS Reference Output Noise VNR f > 100 Hz – 0.5 – µV/√Hz DC Internal Reference Output Resistance RREF_INT Output/Input Mode 150 200 300 Ω Output Mode Only ‒ 2 5 Ω Input Mode Only ‒ 200 ‒ kΩ Reference Voltage Input Range VREF(IN) TA = 25°C, VREF overdriven externally 0.5 ‒ 2.65 V Reference Source Current ISOURCE_REF VREF to GND 0.5 0.7 1 mA Reference Sink Current ISINK_REF VREF to VCC 5 10 mA OCF OPERATING CHARACTERISTICS Overcurrent Fault Leakage Current ILEAK VCC = 5 V, RFAULT = 10 kΩ to VCC, during non-fault condition ‒ 1 ‒ µA Overcurrent Fault On Internal Resistance ROCF_Int Open drain; active low 105 140 200 Ω Overcurrent Fault Output Voltage VOCF_ON OCF pin voltage during fault condition ‒ ‒ 0.3 V Overcurrent Fault Fall Time tOCF(FALL) ROCF = 10 kΩ, 90% output to 10% output final voltage ‒ 1 ‒ µs Overcurrent Fault Response Time tOCF Time from input rising above |VOCF(OP)| until OCF<VOCF_ON BW = 100 kHz ‒ 2.7 7.5 µs BW = 250 kHz ‒ 2 5 µs BW = 400 kHz ‒ 1.5 4 µs BW = 450 kHz ‒ 1.4 ‒ µs Overcurrent Fault Hysteresis VOCF_Hyst Hysteresis below trip point before fault resets ocf_hys = 0 ‒ 120 ‒ mV ocf_hys = 1 ‒ 240 ‒ mV

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com ELECTRICAL CHARACTERISTICS (continued): Valid through the full operating temperature range, TA, CBYP = 0.1 µF, VCC = 5 V, eco_mode = 0, unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit PROGRAMMABLE CHARACTERISTICS: QUIESIENT VOLTAGE AND REFERENCE VOLTAGE Reference Voltage Coarse BITSVREF_ COARSE vref_coarse ‒ 2 ‒ bit Reference Voltage Fine BITSVREF_FINE voff_fine ‒ 9 ‒ bit Factory-Programmed Reference Voltage VREF_FACT ‒ 2.5 ‒ V Average VREF Programming Step Size STEPVREF TA = 25°C ‒ 0.98 ‒ mV Reference Voltage Temperature Compensation Step Size STEPVREF_TC Step size at each of TC point ‒ STEPVREF ‒ mV Reference Voltage Output Programming Range VREF(OUT) TA = 25°C; the vref_fine programming range for a given vref_coarse vref_coarse = 11; factory default 2.35 2.5 2.65 V vref_coarse = 10 1.5 1.65 1.8 V vref_coarse = 01 1.35 1.5 1.65 V vref_coarse = 00 0.35 0.5 0.65 V Offset Voltage Programming Bits BITSVOFF_FINE voff_fine ‒ 9 ‒ bit Factory-Programmed Quiescent Voltage Output VOUT(Q) TA = 25°C; 0 G ‒ VREF ‒ V Offset Voltage Programming Step Size STEPVOFF VOFF = VOUT(Q) – VREF – 1.15 – mV Offset Voltage Temperature Compensation Step Size STEPVOFF_TC Step size at each of TC point ‒ STEPVREF ‒ mV Offset Voltage Programming Range VOFF_PR VOFF = VOUT(Q) – VREF –200 – 200 mV PROGRAMMABLE CHARACTERISTICS: SENSITIVITY Coarse Sensitivity Programming Bits BITSSENS_C sens_coarse ‒ 2 ‒ bit Sensitivity Programming Bits BITSSENS_FINE sens_fine ‒ 9 ‒ bit Factory-Programmed Sensitivity SensFACT TA = 25°C sens_coarse = 11; 013B5-C ‒ 13.5 ‒ mV/G sens_coarse = 10; 006B5-C ‒ 6 ‒ mV/G sens_coarse = 01; 003B5-C ‒ 3 ‒ mV/G sens_coarse = 00; 1P5B5-C ‒ 1.5 ‒ mV/G Average Sensitivity Step Size STEPSENS TA = 25°C; sens_fine programming step size for a given sens_coarse sens_coarse = 11 29.57 34 40 µV/G sens_coarse = 10 13.14 15.11 17.78 µV/G sens_coarse = 01 6.57 7.56 8.89 µV/G sens_coarse = 00 3.29 3.78 3.44 µV/G Sensitivity Temperature Compensation Step Size STEPSENS_TC Step size at each of TC point ‒ STEPSENS ‒ Sens

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com ELECTRICAL CHARACTERISTICS (continued): Valid through the full operating temperature range, TA, CBYP = 0.1 µF, VCC = 5 V, eco_mode = 0, unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit PROGRAMMABLE CHARACTERISTICS: SENSITIVITY (CONTINUED) Sensitivity Programming Range SensPR TA = 25°C; sens_fine programming range for a given sens_coarse sens_coarse = 11 7.2 ‒ 18 mV/G sens_coarse = 10 3.5 ‒ 7.2 mV/G sens_coarse = 01 1.7 ‒ 3.5 mV/G sens_coarse = 00 0.8 ‒ 1.7 mV/G Sensitivity Slope Over Temperature Bits BITSSENS_ SLOPE gain_tc ‒ 6 ‒ bit Sensitivity Slope Temperature Coefficient Step Size STEPSENS_ SLOPE ‒ 0.002 ‒ %/°C Sensitivity Slope Temperature Coefficient Programming Range SensSLOPE_PR ‒0.025 ‒ 0.05 %/°C PROGRAMMABLE CHARACTERISTICS: OVERCURRENT FAULT Overcurrent Fault Step Bits BITSOCF ocf_thr ‒ 9 ‒ bit Factory Overcurrent Fault Operating Point VOCF(fact) Fault threshold in |mV| of equivalent output swing from VREF ‒ 2000 ‒ mV Overcurrent Fault Step Size STEPOCF VOCF step size in mV of equivalent output swing ‒ 9 ‒ mV Overcurrent Fault Operating Point Range VOCF_R Fault operating point range in |mV| of equivalent output swing from VREF 500 ‒ 5000 mV Overcurrent Fault Mask Time Range tOCF(MASK) With RFAULT = 10 kΩ 0 ‒ 3.5 µs Overcurrent Fault Hold Time tOCF(HOLD) Minimum time after OCF flag before flag is released 0 ‒ 5 ms

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com ACS37600KLU DEVICE PERFORMANCE CHARACTERISTICS : Valid through the full operating temperature range, TA, CBYP = 0.1 µF, VCC = 5 V, eco_mode = 0, unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit QUIESCENT OUTPUT VOLTAGE AND REFERENCE OUTPUT VOLTAGE ERROR Factory QVO Error VOUT(Q)_ERR TA = 25°C ‒10 1±4 10 mV QVO Temperature Drift VOUT(Q)_TC TA = 25°C to 125°C, VOUT(Q) ‒ VOUT(Q)@25°C ‒10 2 ±6 10 mV TA = 25°C to –40°C, VOUT(Q) ‒ VOUT(Q)@25°C ‒10 –1 ±4 10 mV Factory Reference Output Voltage Error VREF_ERR TA = 25°C ‒10 ±4 10 mV Reference Voltage Temperature Drift VREF_TC TA = 25°C to 125°C , VREF ‒ VREF@25°C ‒10 ±4 10 mV TA = 25°C to –40°C, VREF ‒ VREF@25°C ‒10 –1 ±2 10 mV Factory Offset Output Voltage Error VOE_ERR TA = 25°C, VOUT(Q) ‒ VREF ‒10 –1±3 10 mV Offset Error Temperature Drift VOE_TC TA = 25°C to 125°C, VOE ‒ VOE@25°C ‒10 –4 ±3 10 mV TA = 25°C to –40°C, VOE ‒ VOE@25°C ‒10 –1 ±4 10 mV SENSITIVITY ERROR Factory Sensitivity Error ESENS_ERR TA = 25°C ‒1.75 ±1 1.75 % Sensitivity Temperature Drift ESENS_TC TA = 25°C to 125°C, ESENS ‒ ESENS@25°C ‒1.75 –0.4 ±1.1 1.75 % TA = 25°C to –40°C, ESENS ‒ ESENS@25°C ‒1.75 ±1 1.75 % FACTORY PERFORMANCE ERROR INCLUDING LIFETIME DRIFT [1] Factory QVO Error Including Lifetime Drift VOUT(Q)_ERR_LTD TA = 25°C ‒ 6 ± 6 ‒ mV QVO Temperature Drift Including Lifetime Drift VOUT(Q)_TC_LTD TA = 25°C to 125°C, VOUT(Q) ‒ VOUT(Q)@25°C ‒ 2 ± 6 ‒ mV TA = 25°C to –40°C, VOUT(Q) ‒ VOUT(Q)@25°C ‒ – 1 ± 8 ‒ mV Factory Reference Output Voltage Error Including Lifetime Drift VREF_ERR_LTD TA = 25°C ‒ – 1 ± 6 ‒ mV Reference Voltage Temperature Drift Including Lifetime Drift VREF_TC_LTD TA = 25°C to 125°C , VREF ‒ VREF@25°C ‒ 1 ± 6 ‒ mV TA = 25°C to –40°C, VREF ‒ VREF@25°C ‒ – 1 ± 6 ‒ mV Factory Offset Output Voltage Error Including Lifetime Drift VOE_ERR_LTD TA = 25°C, VOUT(Q) ‒ VREF ‒ – 5 ± 5 ‒ mV Offset Error Temperature Drift Including Lifetime Drift VOE_TC_LTD TA = 25°C to 125°C, VOE ‒ VOE@25°C ‒ 3 ± 5 ‒ mV TA = 25°C to –40°C, VOE ‒ VOE@25°C ‒ ± 5 ‒ mV Factory Sensitivity Error Including Lifetime Drift ESENS_ERR_LTD TA = 25°C ‒ ± 1.7 ‒ Sensitivity Temperature Drift Including Lifetime Drift ESENS_TC_LTD TA = 25°C to 125°C, ESENS ‒ ESENS@25°C ‒ –1 ± 1.6 ‒ % TA = 25°C to –40°C, ESENS ‒ ESENS@25°C ‒ –0.6 ± 1.7 ‒ % Overcurrent Fault Factory Error VOCF_EFAC Fault trip point error in mV of equivalent output swing ‒100 ‒ 100 mV [1] Performance including lifetime drift is based on a convolution of initial performance distributions and drift seen during commercial qualification. Typical values are the worst-case observed mean ±3 sigma drift during the commercial qualification.

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com ACS37600KLU DEVICE PERFORMANCE CHARACTERISTICS : Valid through the full operating temperature range, TA, CBYP = 0.1 µF, VCC = 5 V, eco_mode = 0, unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit PERFORMANCE ERROR INCLUDING LIFETIME DRIFT AFTER END-OF-LINE CALIBRATION [1] QVO Lifetime Drift VQVO_LTD TA = 25°C ‒ 5 ±5 ‒ mV QVO Temperature Drift Including Lifetime Drift VOUT(Q)_TC_LTD TA = 25°C to 125°C, VOUT(Q) – VOUT(Q)@25°C ‒ 2 ± 6 ‒ mV TA = 25°C to –40°C, VOUT(Q) – VOUT(Q)@25°C ‒ –1 ± 8 ‒ mV Reference Voltage Lifetime Drift VREF_LTD TA = 25°C ‒ ± 5 ‒ mV Reference Voltage Temperature Drift Including Lifetime Drift VREF_TC_LTD TA = 25°C to 125°C , VREF – VREF@25°C ‒ 1 ± 6 ‒ mV TA = 25°C to –40°C, VREF – VREF@25°C ‒ – 1 ± 6 ‒ mV Offset Error Voltage Lifetime Drift VOFF_LTD TA = 25°C ‒ –4 ± 4 ‒ mV Offset Error Temperature Drift Including Lifetime Drift VOE_TC_LTD TA = 25°C to 125°C, VOE – VOE@25°C ‒ 3 ± 5 ‒ mV TA = 25°C to –40°C, VOE – VOE@25°C ‒ ± 5 ‒ mV Sensitivity Lifetime Drift ESENS_LTD TA = 25°C ‒ ± 1.4 ‒ % Sensitivity Temperature Drift Including Lifetime Drift ESENS_TC_LTD TA = 25°C to 125°C, ESENS – ESENS@25°C ‒ –1 ±1.6 ‒ % TA = 25°C to –40°C, ESENS – ESENS@25°C ‒ –0.6 ± 1.7 ‒ % Overcurrent Fault Reprogramming Error VOCF_ERR Fault trip point error in mV of equivalent output swing ‒200 ‒ 200 mV [1] Lifetime drift characteristics are based on the commercial qualification results from zero hours reads. Performance including lifetime drift is based on a convolution of initial performance distributions and drift seen during commercial qualification. Typical values are the worst-case observed mean ±3 sigma drift during the commercial qualification.

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com FUNCTIONAL DESCRIPTION Power-On Reset Operation The POR thresholds of the ACS37600 is based on a combination of a check on the internal regulator supplied and VCC. This allows the ACS37600 to accurately report a signal, including internal stress and temperature compensation, at startup. Refer to Figure 2 and Figure 7 for power factory on/off profile of ACS37600. Power-On As VCC ramps up, the ACS37600 VOUT and VREF pins are high impedance until VCC reaches and passes VUVD(H) [2] (or VPOR(H) [1] if UVD is disabled). Once VCC passes [2], the device takes a time, tPOD, without VCC dropping below VPOR(L) [8] before the outputs enters normal operation. Power-Off As VCC drops below VPOR(L) [8], the outputs will enter a high impedance state. If UVD is enabled, before the device powers of it will force VOUT to GND if VCC < VUVD(L) [6] until VPOR(L) [8] is reached at which point VOUT and VREF will go high Z. If UVD is disabled, then VREF and VOUT will continue to report until VCC is less than VPOR(L) [8] at which point they will go high Z. Note: Since the device is entering a high Z state, and not forcing the output, the time it takes the output to settle will depend on the external circuitry used. Power-On Timing The descriptions in this section assume: temperature = 25°C, with the labeled test conditions. The provided graphs in this section show VOUT moving with VCC. VOUT during a high-impedance state will be most consistent with a known load (RLOAD, CLOAD). Power-On Reset (POR) If VCC falls below VPOR(L) [8] while in operation, the output will re-enter a high-impedance state. After VCC recovers and exceeds VUVD(H) [2] the output will begin reporting again after the delay of tPOD. This tPOD depends on tPORR, tPOR-OUT and, tPOR-REF. Power-On Reset Release Time (tPORR) When VCC rises above VUVD(H) [2], the Power-On Reset delay counter starts. If UVD is disabled, this threshold is VPOR(H) [1]. The output will only release from high impedance to nominal operation after the Power-On Reset counter has reached the inter- nal tPORR and the temperature compensation has updated. This allows for robust and stable output reporting that is temperature compensated. If VCC falls below VPOR(L) [8] before the counter finishes the counter is reset and the part remains in the reset state. Figure 2: Power States Thresholds with VOUT Behavior, RL = Pull-Up, UVD Enabled HI Z HI Z HI Z HI Z Time Voltage VUVD(H) VUVD(L) VPOR(H) VPOR(L) QVO 2.5V VOVD(L) VOVD(H) 2 3 5 6 7 8 VCC VOUT 1 1 VOVDHys VUVDHys VPORHys

Manchester, NH 03103-3353 U.S.A. tion for discussion of the implications of VREF driven internally. put to drive the pin to 90% VREF stable state from the high Z state. Figure 6. The voltage on the VREF pin is the common mode volt- age for the VOUT amplifier and will dictate the zero for VOUT. considered when selecting the RREF and CREF values. active low when a fault condition is present after this time.

2 VREFVCC VOUT

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Figure 7: Power States Thresholds with VOUT and VREF Behavior, RL = Pull Up, UVD enabled Overvoltage and Undervoltage Detection To ensure that the device’s output can be trusted, the device con- tains an overvoltage and undervoltage detection flag. This will Use VOUT and VREF to alert the system when the supply voltage is outside of the operational ranges. If one or both are not desired, the functionality can be individually toggled off. Undervoltage Detection Voltage Thresholds (VUVD(H/L)) The ACS37600 comes factory programmed with UVD enabled. It is important to note that when powering up the device for the first time after a POR event, the VOUT and VREF will remain high Z until VCC raises above VUVD(H) (seen in Figure 7 as [2]), at which point the VOUT and VREF pin will begin to operate. If UVD is disabled, VOUT and VREF will begin report after VCC raises above VPOR(H) (seen in Figure 7 as [1]) under the same conditions. If VCC drops below VUVD(L) [6] after normal operation, VOUT will go to GND regardless of RLOAD configuration. The VOUT pin will stay at GND until VCC raises above the VUVD(H) [7] or VCC falls below VPOR(L) [8]. If VCC rises above VUVD(H) [7] after a UVD event, the outputs will resume operation. If VCC drops below the VPOR(L) [8], the device will enter a POR event and reset, VOUT and VREF will switch to high Z if this occurs. During UVD flagging, VREF is high Z, but is always pulled down so will float to GND. Overvoltage Detection Voltage Thresholds (VOVD(H/L)) When VCC raises above VOVD(H) (seen in Figure 7 as [4]), the output of the VREF and VOUT pins will go high Z, VREF be pulled to GND, and VOUT will be pulled to either VCC or GND, depend- ing if RLOAD is in a pull-up or pull-down configuration. Overvoltage/Undervoltage Detection Hysteresis (VOVDHys/VUVDHys) To prevent toggling, there is hysteresis between enable and dis- able thresholds to reducing nuisance flagging and clears. There is about 1 V and 0.4 V of hysteresis for Overvoltage and Undervolt- age respectively. These can be seen represented in Figure 7 and Figure 8 between the relevant thresholds. Overvoltage and Undervoltage Enable and Disable Time (tOVD(E/D), tUVD(E/D)) The enable time for OVD, tOVD(E), is the time from VOVD(H) [4] to OVD flag [B] in Figure 8. The UVD enable time, tUVD(E), is the time from VUVD(L) [6] to the UVD flag [D] also in Figure 8. The enable flag for both OVD and UVD have a counter to reduce transients faster than 64 µs from nuisance flags. If VCC ramps from >VUVD(L) [6] to <VPOR(L) [8] (both seen in Figure 7) faster than tUVD(E) ≈ 64 µs, then the device will not have time to report a UVD event before power off occurs. The disable time for OVD, tOVD(D), is the time from VOVD(L) [5] to the OVD clear to normal operation [E] in Figure 8. The UVD disable time, tUVD(D), is the time from VUVD(H) [7] to the UVD flag clear to nominal operation [E] also seen in Figure 8. The disable time does not have a counter for either UVD or UVD to release the output and resume reporting as soon as possible. HI Z HI ZHI Z HI Z HI Z HI Z HI Z HI Z HI Z Time Voltage 5 V VUVD(H) VUVD(L) VPOR(H) VPOR(L) QVO 2.5 V VOVD(L) VOVD(H) 2 3 5 6 7 8 VCC VOUT 1 1 VOVDHys VUVDHys VPORHys VREF VREF(Ideal) 2 4 5 6 7 6 78 6 8 Time Voltage

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Figure 8: tPOD, tOVD(E/D), and tUVD(E/D) behavior with “fast” VCC ramping HI Z HI Z Time Voltage 5 V VUVD(H) VUVD(L) VPOR(H) VPOR(L) QVO 2.5 V VOVD(L) VOVD(H) VCC VOUT VOVDHys VUVDHys VPORHys tOVD(E) B tPOD A tOVD(D) C tUVD(D) E tUVD(E) D Supply Zener Clamp Voltages If the voltage applied to the device continues to increase past the overvoltage detection, to extreme levels, there is a point at which Zener diodes will turn on (VZ). These internal diodes are in place to protect the device from short high voltage or ESD events and should NOT be used as a feature to reduce the voltage on a line. Continued exposure to voltages higher than normal operating voltage VCC(typical) can weaken or even damage the Zener diodes and potentially lead to damage of the part. Operating Ranges These are the environmental operation ranges that affect device performance. Operational Ambient Temperature Range This is the temperature range that the operating and electrical characteristics tables are valid unless otherwise stated. Optimal Ambient Temperature Range This is the temperature range that the performance characteristics are valid unless otherwise stated. This is the region the accuracy performance characteristics are factory-programmed for over temperature performance. Optimal Absolute Field Range This is the input field range with the tightest linearity limits and is recommended for highest accuracy applications. Nominal Absolute Field Range This is the input field range beyond the optimal range that has wider linearity limits than the optimal range but still falls at or below 1% error. This range could be used if linearity is not a concern or is required by the physical application. Extended Absolute Field Range This is the input field range beyond the nominal field range to the absolute maximum rated field. The device can still respond in this range, but the linearity will degrade in the region. Linearity is not characterized and does not have limits associated with this field range.

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Absolute Maximum Ratings These are the maximum application or environmental condition that the device can be subjected before damage may occur. Forward and Reverse Supply Voltage This is the greatest voltage that can be supplied to VCC from GND during programming or transient switching. This voltage should not be used as a DC voltage bias for an extended time. Forward and Reverse Output Voltage Forward Output V oltage or VFOUT rating should be read as a volt- age of no greater than VCC + 0.5 V up to 15 V . This is the greatest voltage that the output can be biased with from GND during programming or transient switching. The Reverse Output V oltage or VROUT should not drop below –0.5 V during programming or transient switching. These voltages should not be used as a DC voltage bias for an extended time. Forward and Reverse Reference/Fault Voltage Forward Reference/Fault V oltage or VF-RF rating should be read as a voltage of no greater than VCC + 0.5 V up to 6.5 V . This is the greatest voltage that the output can be biased with from GND during programing or transient switching. The Reverse Output V oltage or VR-RF should not drop below –0.5 V during program- ming or transient switching. These voltages should not be used as a DC voltage bias for an extended time. Output Source and Sink Current This is the maximum current that VOUT can passively sink or source before damage may occur. Maximum Input Gauss This is the maximum field that the transducer of the device may respond. This field greater in magnitude than this limit is beyond the known performance of the device. Additional Functional Descriptions Uni/Bidirectional Functionality This device does not have an Allegro-typical unidirectional mode. VREF can be overdriven or programmed to achieve a VOUT(Q) of 0.5 V which will function unidirectionally when the device is bidirectional. Devices in this unidirectional configuration do not extend the fault sensing range, and the effective VOCF(OP) is the same absolute swing from the VREF. If unidirectional functional- ity is desired the overtemperature performance is only valid while the device is in the factory default vref_coarse configuration. This should only be changed for prototyping or applications that do not require overtemperature accuracy.

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com DEFINITIONS OF OPERATING AND PERFORMANCE CHARACTERISTICS Quiescent Voltage Output (VOUT(Q)) The quiescent voltage output is defined as the voltage on the output VOUT when zero gauss is applied. VOUT(Q) is determined by two quantities, VREF pin voltage and voff_fine register that adjusts the output channel offset error from the VREF pin. QVO Temperature Drift (VOUT(Q)_TC) QVO Temperature Drift or VOUT(Q)_TC is defined as the drift of VOUT(Q) from room to hot or room to cold (25°C to 125°C or 25°C to –40°C respectively). Temperature drift is compensated with Allegro’s factory trim to remain within the limits across temperature; because of this, only room trimming/programming is needed. This parameter is controlled by the voff_fine register. Programming too close (<32 LSB) to the minimum and maxi- mum values of the voff_fine will affect temperature performance. This compensation is done in increments of STEPVOFF overtem- perature. Reference Voltage (VREF) The voltage reference output pin (VREF) is used as the common- mode voltage reference for the output channel VOUT. VREF pin voltage determines the quiescent voltage (VOUT(Q)) of the output amplifier, allowing the pin to be driven internally, externally, and overdriven to change the outputs quiescent voltage. This pin can be programmed to operate as an input only, output only, or input/output with the io_vref_mode register. The output voltage can also be adjusted with two internal VREF DACs: vref_coarse which determines the coarse range that vref_fine can adjust, and fine tune. For further information about these registers, refer to Programming Parameters section. VREF programmable range: 0.35 to 2.65 V VREF can be overdriven to 0.5 to 2.65 V Reference Voltage Temperature Drift (VVREF_TC) Reference V oltage Temperature Drift or VVREF_TC is defined as the drift of VREF from room to hot or room to cold (25°C to 125°C or 25°C to –40°C respectively). Only room trimming/programming is needed because temperature drift is compensated with Allegro’s factory trim to remain within the limits across temperature. This parameter is controlled by the vref_fine register. Programming too close (<32 LSB) to the minimum and maximum values of the vref_fine will affect temperature performance. This compensation is done in increments of STEPVREF over temperature. VVREF_TC is dependent on the vref_coarse register, VVREF_TC may not meet datasheet parameters if vref_coarse is changed from factory default. Reference Voltage Programming Step Size (STEPVREF) Reference V oltage Programming Step Size is defined as the average change in VREF voltage per an LSB change in vref_fine register. Offset Voltage (VOFF) Offset V oltage or VOFF is defined as VOUT(Q) -VREF and can be seen in Figure 9. The voltage offset between the output and VREF can be adjusted with the voff_fine register. For best accuracy, verify the device’s actual step size and result when trimming. Offset Error Temperature Drift (VOFF_TC) Offset Error Temperature Drift or VOFF_TC is defined as the drift of VOUT(Q) – VREF from room to hot or room to cold (25°C to 125°C or 25°C to –40°C respectively). Refer to QVO Tempera- ture Drift for further information. Offset Voltage Programming Step Size (STEPVOFF) Offset V oltage Programming Step Size is defined as the average of change in VOUT(Q) -VREF voltage per an LSB change in voff_ fine register. For best accuracy, verify the devices actual step size and result when trimming. Output Saturation Voltage (VSAT(HIGH/LOW)) Output Saturation V oltage or VSAT is defined as the voltage that output no longer changes when the magnitude of the magnetic field is increased. VSAT(HIGH) is the highest voltage the output can drive to, while VSAT(LOW) is the lowest. This can be seen in Figure 21. Note that changing the sensitivity does not change the VSAT points.

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Figure 9: VOFF, VREF, VOUT(Q). Numbers are exaggera- tions and not representative of device performance Figure 10: VSAT, Sensitivity with GOCF(fact) and VOCF(fact) Sensitivity (Sens) Sensitivity or Sens is the output swing in the presence of a magnetic field, perpendicular to and out of the top surface of the package face (refer to polarity section and Figure 12). This magnetic field moves the output voltage away from its VOUT(Q) and towards the supply voltage rails. The magnitude and direc- tion of the output voltage swing is proportional by Sens to the magnitude and direction of the applied magnetic field. The Sens of the device is calculated slightly differently for “unidirectional” (positive or negative VOOR) and “bidirectional” (positive and negative VOOR) parts. Bidirectional parts have sensitivity defined as follows: ( 1) − ( 2) 1 − 2 Unidirectional parts have sensitivity defined as follows: ( ) − ( ) where BPOS and BNEG are two magnetic fields with opposite polarities, and VOUT(BPOS) and VOUT(BNEG) are the voltages recorded of the device with the applied fields. VOUT(Q) is the actual measured offset voltage, not calculated. The fine sensitiv- ity of device can be programmed and controlled by the sns_fine register. The effect of changing sns_fine can be seen in Figure 10 in the right most breakout frame. Sensitivity Programming Range (SensPR) Sensitivity Programming Range or SensPR is the sensitivity pro- gramming range of the device with sns_fine register. The sns_fine register scales with the sns_coarse register to determine the Sens range of a given device; refer to Device Performance Character- istics section for specific devices. Sens can be programmed from factory value within the sensitivity range limits: SensPR(min) and SensPR(max). Exceeding the specified SensPR can cause the device to operate outside datasheet limits and changes. For further infor- mation about these registers, refer to Programming Parameters. Sensitivity Temperature Drift (ESENS_TC) Sensitivity Temperature Drift or ESENS_TC is defined as the drift of Sens from room to hot or room to cold (25°C to 125°C or 25°C to –40°C respectively). Only room trimming/program- ming is needed because temperature drift is compensated with Allegro’s factory trim to remain within limits across temperature. This parameter is controlled by the sns_fine register. Program- ming too close (<32 LSB) to STEPSENS min and max values will affect temperature performance. This compensation is done in increments of STEPSENS over temperature and because STEP- SENS is dependent on sns_coarse, the ESENS_TC limit is only valid for factory-programmed sns_coarse.

Manchester, NH 03103-3353 U.S.A. of the top surface of the package face as seen in Figure 12. Figure 13. Consider two magnetic fields, B1(1/2 FS) and B2(FS). Assumed fields are within the part’s response range.

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Total Output Error Total Output Error is the difference between the field measure- ment from the sensor IC and the actual field (B), relative to the actual field. This is equivalent to the difference between the ideal output voltage and the actual output voltage, divided by the ideal sensitivity, relative to the field applied to the device: ETOT(±) = (1 – VOUT_Actual(B±) / VOUT_Ideal(B±)) where V OUT_Actual(B±) = ±B × SensActual + VOUT(Q)_Actual and V OUT_Ideal(B±) = ±B × SensIdeal + VOUT(Q)_Ideal Total Output Error incorporates all sources of error and is a func- tion of magnetic field B. At relatively high fields, Total Output Error will be mostly due to sensitivity error, and at relatively low fields, Total Output Error will be mostly due to Offset V oltage (VOE). In fact, at B = 0, Total Output Error approaches infinity due to the offset. An example of total error at FS can be seen in Figure 13. Note: Total Output Error goes to infinity as the amount of applied field approaches zero gauss. Symmetry Error (ESYM) Symmetry Error is the difference between the sensitivity for two applied magnetic fields with equal magnitude and opposite polar- ity. Symmetry Error, ESYM (%) is defined as: ESYM = (1 – SensB+ / SensB–) × 100% where SensB+ and SensB– are measured with magnetic field B such that B+ = |–B–|. This can be seen in Figure 14. Power Supply Offset Error (VPS) Power Supply Offset Error or VPS is defined at the offset error in mV between VCC at 5 V to 4.5 V and 5 V to 5.5 V . Offset Power Supply Rejection Ratio (PSRRO) Offset Power Supply Rejection Ratio or PSRRO is defined as 20 × log of the ratio of the change of QVO in volts over a ±100 mV variable AC VCC centered at 5 V reported as dB in a specified frequency range. This is an AC version of the VPS parameter. The equation can be seen below: PSSRO = 20 × log(ΔQVO/ΔVCC) Power Supply Sensitivity Error (EPS) Power Supply Sensitivity Error or EPS is defined as the % sensitiv- ity error measured between VCC at 5 V to 4.5 V and 5 V to 5.5 V . Sensitivity Power Supply Rejection Ratio (PSRRS) Sensitivity Power Supply Rejection Ratio or PSRRS is defined as 20log of the ratio of the % change the sensitivity over the % change in VCC (±100 mV variable AC VCC centered at 5 V) reported as dB in a specified frequency range. This is the AC ver- sion of the EPS parameter. The equation is as follows: PSSRS = 20log(Δ%Sens / Δ%VCC) Figure 13: Accuracy Error Figure 14: Symmetry Error with Absolute Outputs

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Fault Behavior OVERCURRENT FAULT (OCF) As the output swings because of a sensed field, the Overcurrent Fault or OCF pin will trigger with an active low flag if the sensed field exceeds its programmed threshold. This is internally com- pared via voltages with the flag tripping symmetrically for the positive and negative OCF operating point. This trip point, like VOUT, is centered around VREF, so if VREF changes, the trip point remains the same in terms of output swing from VREF. The implementation for the OCF circuitry is accurate over temperature and does not require further temperature compensa- tion, as it is dependent on the Sens and VOFF parameters that are already trimmed flat over temperature. OVERCURRENT FAULT OPERATING POINT (V OCF(OP)) Overcurrent Fault Operating Point has two definitions, one for input and one for output-referred thresholds related by the device’s actual sensitivity. The Output Referred OCF Operating Point or VOCF(OP) is defined as the equivalent output in mV to which the OCF flag corresponds, while the Input Referred OCF Operating Point or GOCF(OP) (seen in Figure 15 as [9]) is the field equivalent to the VOCF(OP). Both VOCF(OP) and GOCF(OP) give the same functional trip point. The OCF threshold is programmed by the ocf_thr register. The factory VOCF(OP), or VOCF(fact), is 2000 mV swing on the output. The functional range is 0.5 V to 5 V swing from VREF for the VOCF(OP). VOCF(OP) = (Field × SensACTUAL) × 1000 (mV) GOCF(OP) = VOCF(OP) / SensACTUAL The minimum and maximum codes for ocf_thr registers do not correspond to the minimum and maximum OCF functional range. Refer to the programming section for further information on ocf_thr programing. OVERCURRENT FAULT HYSTERESIS (V OCF_HYS ) Overcurrent Fault Hysteresis or VOCF_HYS is defined as both output-referred or input-referred magnitudes from the OCF flag assertion threshold (seen in Figure 16 as [9]) to the OCF clear threshold (seen in Figure 16 as [10]). The ACS37600 comes standard with an VOCF_HYS of 120 mV equivalent output swing. If a larger hysteresis is desired, this can be doubled to 240 mV by setting ocf_hys = 1. OVERCURRENT FAULT STEP SIZE (STEP OCF) The Overcurrent Fault Step Size or STEPOCF is defined as the average change in VOCF(OP) or GOCF(OP) with an LSB change to the ocf_thr register. OVERCURRENT FAULT FACTORY ERROR (V OCF_EFAC) Overcurrent Fault Factory Error or VOCF_EFAC is the error, in mV , of the actual OCF trip point and the factory target of 2 V swing on the output. OVERCURRENT FAULT REPROGRAMMED ERROR (VOCF_ERR ) Overcurrent Fault Reprogrammed Error or VOCF_ERR is the error in mV of the actual OCF trip point and the reprogrammed target. Figure 15: Fault Thresholds and Functional OCF Pin States Figure 16: General Fault Timing

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com OVERCURRENT RESPONSE TIME ( tOCF) Overcurrent Response Time or tOCF is defined as the time from when the input reaches the operating point [9] until the device’s OCF pin falls below VOCF_ON [G]. If the OCF Mask is disabled, tOCF is equal to tOCF-R seen as the time from [9] until [F]. OVERCURRENT REACTION TIME ( tOCF-R) Overcurrent Reaction Time or tOCF-R is defined as the time from the field input rising above GOCF(OP) at point [9] until the OCF pin reaches VOCF_ON at point [F] with the OCF mask disable. This is also the time required for the device to recognize and clear the fault, seen as the time between [10] until [I]. This can be seen in Figure 16. OVERCURRENT FAULT HOLD TIME ( tOCF-HOLD) Overcurrent Fault Hold Time or tOCF-HOLD is defined as the mini- mum time the OCF flag will be asserted after a sufficient OCF event. After the hold time has been reached, OCF will release if the OCF condition has ended (seen in Figure 16, [G] until [J]) or persist if the OCF condition is still present (seen in Figure 17, [F] until [K]). Factory default is 0 ms and can be changed in the ocf_mask register. OVERCURRENT FAULT MASK TIME ( tOCF-MASK) Overcurrent Fault Mask Time or tOCF-MASK is defined as the additional amount of time the OCF must be present beyond tOCF-R (seen in Figure 16, [F] until [G]). To prevent nuisance trip- ping, a programmable ocf_mask time is used. If an OCF occurs but does not persist beyond tOCF + tOCF-MASK, it is not reported by the device (seen in Figure 18). This prevents short transient spikes from causing erroneous OCF flagging. In the event where transient error reporting is desired, the ocf_mask can be disabled by setting the register to 0. Factory default setting is 1 in the ocf_mask register corresponding to tOCF-MASK = 0.5 µs. OCF PERSIST The ACS37600 has a fault persist option that will maintain the OCF flag if a flag occurred until a POR event. This is disabled as factory default but can be toggled on by setting the ocf_persist register to 1. OCF DISABLE The ACS37600 also contains an OCF disable bit ocf_dis that will disable the OCF pin functionality. When this bit is set to 1, the OCF pin will remain in high Z. Factory default is 0, enabling the OCF functionality. Figure 17: Fault Hold with Clear Fault After Hold Time Figure 18: Fault Condition Clearing Before Mask Time Is Reached

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Dynamic Response Parameters The descriptions in this section assume: temperature = 25°C, and output loads are within specifications provided. The step applied is an input step that corresponds to 1 V excursion on the output, unless otherwise stated. PROPAGATION DELAY ( tREACTION) The time interval between a) when the sensed field reaches 10% of its stable value, and b) when the sensor output reaches 10% of its stable value for a step input. See Figure 19 for visual descrip- tion of parameter. RISE TIME ( tRISE) The time interval between a) when the sensor reaches 10% of its stable value, and b) when it reaches 90% of the stable value for a step input. See Figure 19 for visual description of parameter. RESPONSE TIME ( tRESPONSE) The time interval between a) when the sensed field reaches 90% of its stable value, and b) when the sensor output reaches 90% of its stable value. See Figure 19 for visual description of parameter. OVERSHOOT ( VOS) The amount, in percent of step size, the output voltage (VOUT) rises past the steady-state output voltage. The equation used to calculate this is shown in Figure 20; also see Figure 20 for description of parameters in the equation. SETTLING TIME ( tSettle) The amount of time it takes for the output voltage (VOUT) to settle to between ±3% of the steady-state output. See Figure 20 for description of parameter. Figure 19: Dynamic Response Parameters Figure 20: Overshoot and Settling Time (3 V step is shown) Vout (%) Input Flux Density VOUT Reaction Time (tREACTION) Rise Time (tRISE) 100 Response Time (tRESPONSE) Vmax V1 = VQVO + VSTEP*0.1 t ±3% of VSTEP (90mV) VOUT VSETTLE (3.5V) VOUT(Q) (0.5V) tSETTLE VSTEP (3V)

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Temperature Compensation To remove the effects temperature has on the performance of the ACS37600, an internal temperature sensor is integrated. This sensor, along with compensation algorithms, help to standardize device performance over the full range of operating temperatures. TEMPERATURE COMPENSATION UPDATE RATE ( tUR) After Power-On Delay (tPOD) elapses, tUR is also required to maintain a valid temperature compensated output. Further infor- mation in temperature compensation section. GAIN TEMPERATURE COEFFICIENT ( SENSSLOPE) Sensitivity Temperature Coefficient or SENSSLOPE is a parameter that allows the user to increase or decrease the sensitivity linearly overtemperature. This allows for temp compensation of other ele- ments in the application system i.e. magnetic cores. GAIN TEMPERATURE COEFFICIENT STEP SIZE (STEPSENS_SLOPE) Sensitivity Temperature Coefficient Step Size or STEPSENS_SLOPE is defined as the average change in % Sens/°C per LSB change in the gain_tc register. Package Stress Compensation Sensitivity drift due to package hysteresis is internally compen- sated to reduce the effects of temperature and lifetime drift error. Package stress and relaxation can cause the device sensitivity at TA = 25°C to change during and after temperature cycling and over life stress.

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com APPLICATION AND THEORY Parameter Trim Algorithm For best results, a trim flow of Sens, VREF, and VOFF/VOUT(Q) is recommended, because sensitivity and VREF will affect VOFF/ VOUT(Q). SENS: 1. Knowing the actual sensitivity and target sensitivity, take the difference: SensSTEP = SensTarget – SensActual 2. Using the calculated SensStep, divide it by the STEPSens to de- termine the number of codes to change the sns_fine register. A. If more accuracy is required or desired, measuring the device’s actual STEPSens is required. This should be done if an iterative process is used. # sens codes = round(SensStep/STEPSens) 3. Read the sns_fine register and add the # sens codes to the register value. Write the result back into sns_fine. 4. Measure the new sensitivity. If it is not within 0.5 × STEP- Sens or within desired error, repeat 1-4; be sure to measure STEPSens for best accuracy. VREF: 5. Knowing the actual VREF and target VREF, take the difference: VREF-STEP = VREF-Target – VREF-Actual. 6. Using the calculated VREF-STEP, divide it by STEPVREF to determine the number of codes to change for the vref_fine register. A. If more accuracy is required or desired, measuring the devices actual STEPVREF is required. This should be done if an iterative process is being used. # VREF codes = round(VREF-STEP / STEPVREF) 7. Read the vref_fine register and add the # VREF codes to the register value. Write the result back into vref_fine. 8. Measure the new VREF. If it is not within 0.5 × STEPVREF or within desired error, repeat 5-8; be sure to measure STEPVREF for best accuracy. VOUT(Q): 9. Knowing the actual VOFF and target VOFF, take the difference: VOFF-STEP = VOFF-Target – VOFF-Actual. 10. Using the calculated VOFF-STEP, divide it by the STEPVOFF to determine the number of codes to change the voff_fine register. A. If more accuracy is required or desired, measuring the de- vice’s actual STEPVOFF is required. This should be done if an iterative process is used. # VOFF codes = round(VOFF-STEP / STEPVOFF) 11. Read the voff_fine register and add the # VOFF codes to the register value. Write the result back into voff_fine. 12. Measure the new VOFF. If it is not within 0.5 × STEPVOFF or within desired error, repeat 9-12; be sure to measure STEPVREF for best accuracy.

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com OCF Pulled Up to Different Power Domain The OCF pin was designed to be compatible with power domains that are not the VCC and GND networks. Because the output is not a push or pull output but an active low, this allows it to be pulled up to a different voltage. The OCF must be pulled up to a voltage no greater than the absolute maximum rating of the OCF pin and supplied from the same GND as the device. A common example of this is attaching this pin to a 3.3 V network while the device is being supplied by 5 V . Overdriving VREF: Dynamic Output and Accelerated tPOD The VREF pin can be overdriven while in the factory vref_io_mode. This can be used to dynamically change the effec- tive range of field the output is mapped to, as well as overdriving the VREF pin during startup POR to reduce the tPOD time. To increase VREF voltage, the pin must be supplied with a source that can maintain the desired higher voltage level while being capable of supplying a current greater than ISINK_REF. To decrease the voltage, the pin must be supplied with a sink that can maintain the desired lower voltage while being able to sink ISOURCE_REF. DYNAMIC OUTPUT Range changing can be done by adjusting the VREF pin by over- driving the pin voltage. For an example of this in use, consider the factory default fault at 2 V swing from VREF and during normal operation. The expected operation is going to fall reasonably within ±2 V swing, but there are expected excursions that are +3 V that are of interest. If there is an excursion of 3 V from VREF, which is beyond 2 V VOCF(fact), the OCF pin will trigger and the direction is known because VOUT > VREF. VREF can be overdriven in the opposite direction down 2 V from 2.5 V to 0.5 V , allowing for the output report a signal that is otherwise outside its capabilities. In addition, when this input starts to fall and reduces below 1.88 V from VREF, the OCF will release and the VREF pin can now be let go or driven back to 2.5 V . This effectively allows for a dynamic output operation range, allowing for better accuracy during low current needs while maintaining the ability to capture signals that would otherwise be out of range for the device with this accuracy requirements. ACCELERATED tPOD When the ACS37600 powers up, the power-on time can be limited by the low internal drive strength of the VREF pin. One way to reduce this is by overdriving the VREF pin during POR to remove the VREF limited drive strength from slowing tPOD. This allows tPOD to depend on tPOR-OUT instead of tPOR-REF which is twice as slow. Manchester Communication and Device Features USING THE ANALOG_LOCK BIT The analog_lock configuration is located in register 0x0F bit 24 and controls whether an OVD event is required for read/write communications after the initial unlock. With this bit set to the factory default of 0, OVD is not required to send a read or write command. With this bit set to 1, OVD is required for every read/ write. This bit does not change the unlock procedure, but only communication after unlock. USING THE UNLOCK_CODE BIT The unlock_code register is located in register 0x0F bit 25 and sets the requirement for and additional unlock code to unlock and communicate with the device. With this bit set to the factory default of 0, only one unlock code is required to unlock the part. With this bit set to 1, two codes must be used in succession in order to successfully unlock the part for communication. This bit does not affect communication after unlock. HOW OVD CAN BE USED WITH PROGRAMMING Using OVD during read/write removes the need for the MCU to overdrive the Vref pin for successful communication. Using the OVD flag to make Vref Hi-Z during communication can be used with analog_lock = 1 or 0, but only when ovd_dis = 0 which is the factory default.

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com PROGRAMMING PARAMETERS Fine Tuning Sensitivity, Reference and Quiescent Voltage Sensitivity and VOFF can be adjusted by programming sns_fine and voff_fine bits, as illustrated below. Customers should not program sensitivity or VOUT(Q) beyond the maximum or mini- mum programming ranges specified in the Operating Character- istics table. Exceeding the specified limits will cause sensitivity and VOUT(Q) drift through temperature range, VREF_TC, VOFF_TC, and ESENS_TC, to deteriorate beyond the specified values. Programming sensitivity might cause a small change in VOUT(Q)/ OFF; as a result, Allegro recommends programming sensitivity first, then programming VOUT(Q)/OFF. FINE SENSITIVITY ( sns_fine) Device sensitivity can be programmed by adjusting the sns_fine register. This register is a 2’s complement number, meaning that the sensitivity can be programmed up or down from its nomi- nal value at sns_fine = 0. As part of final testing, the sns_fine register is set by Allegro in the trimming process, so devices may already contain a non-zero sns_fine value. Programing too close (<32 LSB) to STEPSENS minimum and maximum values will affect temperature performance. It is recommended that the user keep the codes from 0-223 and 288-511. FINE REFERENCE VOLTAGE ( vref_fine) The reference voltage (VREF) is determined by one of two stimuli. The value can be programmed internally, in which case the vref_fine and vref_coarse (see the Coarse Reference V olt- age) settings determine which voltage the device outputs on the VREF pin. The second method of setting the reference voltage is by externally overdriving the VREF pin to the desired voltage. In this case, the internal settings do not matter, as the reference is the physical voltage on the pin, not internal settings. Program- ming too close (<32 LSB) to the STEPSENS minimum and maxi- mum values will affect temperature performance. It is recom- mended that the user keeps the codes from 0-223 and 288-511. QUIESCENT OR OFFSET VOLTAGE ( VOUT(Q), VOFF) The quiescent voltage VOUT(Q) is defined as the output voltage when zero gauss is present on the device’s sensing element. In application, this is determined by the reference voltage (VREF) and any offset voltage from the reference (VOFF). To eliminate this offset, voff_fine can be adjusted to remove any error. This 2’s complement number allows VOUT(Q) to be moved up and down without affecting VREF to remove VOFF. At final test, this value is set to trim for the chosen VREF and may need to be adjusted if VREF is changed or overdriven. Programming too close (<32 LSB) to STEPSENS minimum and maximum values will affect temperature performance. It is recommended that the user keep the codes from 0-223 and 288-511. Figure 23: VOFF Register/DAC Transfer Curve Figure 21: Sensitivity Register/DAC Transfer Curve /gid00082/gid00077/gid00082_/gid00104/gid00077/gid00068 Max Sens Code Min Sens Code 0 255/uni00A0 256 511 Valid /uni00A0Programing Range Output Sens (mV/G) 223 288 Figure 22: VREF Register/DAC Transfer Curve /gid00085/gid00081/gid00068/gid00069_/gid00104/gid00077/gid00068 Max V R E F Code Min V R E F Code 0 255/uni00A0 256 511 Valid /uni00A0Programing Range Output V REF/uni00A0(V) 223 288 /gid00085/gid00078/gid00069/gid00069_/gid00104/gid00077/gid00068 Max V OF F Code Min V OF F Code 0 255/uni00A0 256 511 Valid /uni00A0Programing Range Output V OFF/uni00A0(mV) 223 288

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Overcurrent Fault OCF OPERATING POINT THRESHOLD ( ocf_thr) The OCF(OP) threshold is controlled by the ocf_thr register. This register is programmed by the factory to a value that corresponds to 2 V excursion from VREF on the output. If programming OCF(OP) to a different threshold is desired, there are two ways to calculate the code for the desired OCF(OP). If programming the fault such that 0.5 V ≤ |VOCF(OP)| ≤ 3.5 V , the fault error should is within the VOCF_EFAC limits. If programming VOCF(OP) ≥ 3.5 V swing from VREF, the INL error of the ocf_thr DAC will intro- duce error and the fault error should perform within the VOCF_ ERR limits. For best accuracy, OCF(OP) should be validated for each device after trimming. For the first method, take the difference between the current trip point and the desired trip point. Figure 24 shows two equations that can be used to calculate the desired ocf_thr. The second method attempts to mitigate average DAC INL error. The equation in Figure 25 will give the desired average INL compensated ocf_thr code. Note that this only compensates for the average INL error measured in production. Measuring after programming and reprogramming as needed is the most accurate way to mitigate the device specific INL error. A visual representa- tion and equations of the INL compensation and impact on the OCP(OP) are shown in Figure 25. OCF MASK TIME ( ocf_mask) To avoid nuisance OCF tripping from transient signals, the OCF block contains a mask feature that requires the OCF condition to be at or beyond OCF(OP) for a programmable amount of time beyond the reaction time, tOCF-R. This device comes with a factory default ocf_mask = 1 for tOCF-MASK = 0.5 µs. If a differ- ent value is desired, refer to the table below for the appropriate ocf_mask setting. ocf_mask (code) tOCF-MASK (µs) 0 0 1 (factory default) 0.5 2 1 3 2 4 2.5 5 3 6 3.5 Figure 24: Overcurrent Fault Threshold DAC Transfer Function in Full Scale (FS) and Corresponding Output Swing from VREF Figure 25: OCF DAC Nonidealities, INL Error

Manchester, NH 03103-3353 U.S.A. ting, refer to the table below for available options. elent to 120 mV on the output.

0 Input only

1 Input only

2 Output only

Figure 26. To calculate the code needed to obtain the desired gain sensitivity at temperature T and follow the equation below.

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Note: When calculating ESENS_TC, use the expected Sens(T) that can be calculated with the equations for Sens(T). The hot and cold ranges are not symmetric and the GainTC for hot and cold will not match at the extreme temperatures. Sens(T) = Sens(25°C) × [1 + SENSSLOPE(T)] SENSSLOPE(T) = (T – 25) × gain_tc × 2.6 × 10–5 Registers Useful for Prototyping The registers that are contained in this section are useful for prototyping and room applications. Changing the values of these registers from the factory default may affect the over temperature performance. COARSE SENSITIVITY ( sns_coarse) Each ACS37600 is programmed to a different coarse sensitiv- ity setting. Devices are tested and temperature-compensated for the specific coarse sensitivity setting. If the coarse sensitivity is changed, by programming the sns_coarse bits, Allegro cannot guarantee the specified sensitivity drift through temperature and lifetime limits. COARSE REFERENCE VOLTAGE ( vref_coarse) This device has a coarse reference DAC that changes the centered voltage for the vref_fine DAC. To program vref_coarse, refer to the following table. If this register is not in the factory default set- ting, Allegro cannot guarantee the over temperature performance of the device. vref_coarse (code) Approx. Center Voltage (V) 0 0.5 1 1.5 2 1.65 3 2.5 OUTPUT POLARITY ( gc_pol) It is possible to change the direction of the output excursion for a given field by changing the gc_pol register. Refer to polarity for a more detailed explanation in the definitions section. The factory default setting is gc_pol = 0. If the gc_pol is changed from the factory default, Allegro cannot guarantee the over temperature performance of the device. MEMORY LOCKING MECHANISMS The ACS37600 is equipped with multiple memory-locking mechanisms. The purpose of these mechanisms is to allow the user to reduce the likelihood of unintended communication and programming in the future. Note: Due to the nature of locking a part, some of these settings may limit the user’s ability to debug issues in the future, and in some cases may even limit Allegro’s ability to provide assistance in any issues. Make sure that when locking a part, the settings chosen are desired, and functionality of the part is fully under- stood. CHOPPER STABILIZING TECHNIQUE When using Hall-effect technology, a limiting factor for total accuracy is the small signal voltage developed across the Hall element. This voltage is disproportionally small relative to the offset that can be produced at the output of the Hall sensor. This makes it difficult to process the signal while maintaining an accu- rate, reliable output over the specified operating temperature and voltage ranges. Chopper stabilization is a unique approach used to minimize Hall offset on the chip.

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com DEVICE PROGRAMMING Serial Communication The serial interface allows an external controller to read and write registers, including EEPROM, in the device using a point-to- point command/acknowledge protocol. The device does not initi- ate communication; it only responds to commands from the exter- nal controller. Each transaction consists of a command from the controller. If the command is a write, there is no acknowledging from the device. If the command is a read, the device responds by transmitting the requested data. Figure 27: Programming Connections The serial interface uses a Manchester-encoding-based protocol per G.E. Thomas (0 = rising edge, 1 = falling edge), with address and data transmitted MSB first. Four commands are recognized by the device: Write Access Code, Write to V olatile Memory, Write to Non-V olatile Memory (EEPROM) and Read. One frame type, Read Acknowledge, is sent by the device in response to a Read command. Figure 28: General Format for Serial Interface Communication READ (CONTROLLER TO DEVICE) The fields for the Read command are:

• Sync (2 zero bits)
• Read/Write (1 bit, must be 1 for read)
• CRC (3 bits) Figure 29 shows the sequence for a Read command. Figure 29: Read Sequence READ ACKNOWLEDGE (DEVICE TO CONTROLLER) The fields for the data return frame are:
• Sync (2 zero bits)
• Data (32 bits): □ [31:28] Don’t Care □ [27:26] ECC Pass/Fail □ [25:0] Data Figure 30 shows the sequence for a Read Acknowledge. Refer to the Detecting ECC Error section for instructions on how to detect Read/Write Synchronize Memory Address Data (32 bits) and ECC failure. Figure 30: Read Acknowledge Sequence

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com WRITE (CONTROLLER TO DEVICE) The fields for the Write command are:

• Sync (2 zero bits)
• Read/Write (1 bit, must be 0 for write)
• Address (6 bits)
• Data (32 bits): □ [31:26] Don’t Care □ [25:0] Data
• CRC (3 bits) Figure 31 shows the sequence for a Write command. Bits [31:26] are Don’t Care because the device automatically generates 6 ECC bits based on the content of bits [25:0]. These ECC bits will be stored in EEPROM at locations [31:26]. Figure 31: Write Sequence WRITE ACCESS CODE (CONTROLLER TO DEVICE) The fields for the Access Code command are:
• Sync (2 zero bits)
• Read/Write (1 bit, must be 0 for write)
• Address (6 bits)
• Data (32 bits)
• CRC (3 bits) Figure 32 shows the sequence for an Access Code command. Figure 32: Write Access Code The controller must open the serial communication with the device by sending an Access Code. It must be sent within Access Code Timeout, tACC, from power-up, or the device will be dis- abled for read and write access. Name Serial Interface Format Register Address Data (Hex) (Hex) User Access 0x26 0x2C413736 Unlock Code 0x26 0xAFCF6C27 EEPROM ERROR CHECKING AND CORRECTION (ECC) Hamming code methodology is implemented for EEPROM checking and correction. The device has ECC enabled after power-up. The device always returns 32 bits. The message received from controller is analyzed by the device EEPROM driver and ECC bits are added. The first six received bits from device to controller are dedicated to ECC. DETECTING ECC ERROR If an uncorrectable error has occurred, bits 27:26 are set to 10, the VOUT pin will go to a high-impedance state, and the device will not respond to the applied magnetic field. Bits Name Description 31:28 – No meaning 27:26 ECC 00 = No Error 01 = Error detected and message corrected 10 = Uncorrectable error 11 = No meaning 25:0 D[25:0] EEPROM data Characteristics Symbol Note Min. Typ. Max. Unit VCC Programming Enable Voltage VPROG VCC pulse required when initializing first communication 8 – – V Program Time Delay td – 74 – µs Program Write Delay tw – 20 – ms Manchester High Voltage VMAN(H) Data pulses on VREF 4 5 VCC V Manchester Low Voltage VMAN(L) Data pulses on VREF 0 – 1 V Bit Rate tBITR Communication rate 1 30 100 kbps Bit Time tBIT Data bit pulse width at 30 kbps – (33) – µs Access Code Timeout tACC – 10 – ms

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Customer Memory Map Address Register Name Parameter Name Location Description R/W Bits Factory Default Decimal Binary Effect 0x05 eeprom_5 vref_coarse 0:1 Coarse setting for VREF R/W [1] 2 3 11 VREF(OUT) = 2.35 to 2.65 V sens_coarse 2:3 Coarse for sensitivity. R/W [1] 2 DS DS Sets sens range bw_sel 4:5 Internal bandwidth selection R/W 2 2 10 400 kHz io_ref_mode 6:7 VREF input/output mode selection R/W 2 0 00 Input/Output vout_eco_mode 8 Reduces operational ICC and IOD R/W 1 0 0 Turbo ovd_dis 9 Disables OVD flag R/W 1 0 0 OVD enabled uvd_dis 10 Disables UVD flag R/W 0 0 UVD enabled spare_user 11:14 No internal function. Customer scratch. R/W 4 0 0000 N/A voff_fine 15:23 Adjusts VOUT offset from VREF R/W 9 N/A N/A Sets offset ECC 26:31 R 6 N/A N/A 0x06 eeprom_6 ocf_hys 0 Doubles OCF hysteresis R/W 1 0 0 Standard hysteresis ocf_persist 1 OCF flag can only be cleared with POR event R/W 1 0 0 OCF clears normally ocf_mask 2:4 Sets additional time fault condition needs to be present before OCF flag is asserted R/W 3 1 001 0.5 µs OCF mask ocf_hold 5:7 Sets minimum time OCF can be asserted R/W 3 0 000 OCF clears when condition is removed ocf_dis 8 Disables OCF functionality R/W 1 0 0 OCF is enabled ocf_thr 9:17 Sets OCF trip threshold R/W 9 DS DS OCF will trip at 100% FS gc_pol 18 Changes direction output will respond with field R/W [1] 1 0 0 Positive field perpendicular to top face of package will cause positive increase in output ECC 26:31 R 6 N/A N/A 0x0F eeprom_f vref_fine 0:8 Adjusts the VREF output voltage within vref_coarse dependent range R/W 9 DS DS 2.5 V sens_fine 9:17 Adjusts sensitivity of the device within sens_coarse dependent range R/W 9 DS DS Selection specific sensitivity gain_tc 18:23 Adjusts change in sensitivity over temperature up or down R/W 6 0 000000 Flat over temperature analog_lock 24 R/W 1 0 0 unlock_code 25 R/W 1 0 0 ECC 26:31 R 6 N/A N/A [1] Temperature performance is guaranteed while the gc_pol, sens_coarse, vref_coarse are in the factory default state.

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Multi-Device Communication Setup Error Checking CYCLICAL REDUNDANCY CHECK (CRC) The serial interface uses a 3-bit CRC with polynomial g(x) = x3 + x + 1. The CRC is initialized at ‘111’. Synchroniza- tion bits are ignored during calculation of CRC. If the serial inter- face receives a command with a CRC error, the error is ignored, and it is up to the host controller to resend the command. EEPROM ERROR CHECKING AND CORRECTION (ECC) The EEPROM space includes check bits for the purpose of Error Checking and Correction (ECC); these bits are called Hamming codes. ECC can be enabled or disabled via the ECC_DISABLE register. This register has the following effects. ECC_DISABLE = ‘0’ (ECC ENABLED) Read – 26 bits are returned [25:0] A single bit read error will be corrected and the ECC_SINGLE register will be set to ‘1’ A double bit read error will cause the data in EEPROM to remain unchanged, and the Dual Bit Error be set to ‘1’ and force the output to its diagnostic state (High Impedance). Write – 26 bits are accepted. Hamming check bits will be handled internally and written with each write to the EEPROM. ECC_DISABLE = ‘1’ (ECC DISABLED) Read – 32 bits are returned [31:0] Data is passed through unchecked. Check bits are passed to Serial Interface, so checks can be made by host controller. Write – 32 bits are accepted. Check bits can be written by the Serial Interface. In the event of a single or dual bit error, the respective flag is set in register. These flags are read only and will reset after a read command to the register.

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com PACKAGE OUTLINE DRAWING Figure 33: Package LU, 8-Pin TSSOP For Reference Only – Not for Tooling Use (Reference Allegro DWG-0000381, Rev. 1 and JEDEC MO-153AA) NOT TO SCALE Dimensions in millimeters Dimensions exclusive of moldfl ash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A

1.10 MAX

0.15 0.05 0.30 0.19 0.20 0.09 0.60

1.00 REF

C SEATING PLANE C0.10

0.65 BSC

0.25 BSC

+0.15 –0.10 3.00 ±0.10 4.40 ±0.106.40 BSC GAUGE PLANE SEATING PLANE A B 6.10 0.65 0.45 1.70 B D D D Branding scale and appearance at supplier discretion Branded Face E C 1.43 ±0.05 1.50 ±0.05 ±2° D E PCB Layout Reference View Terminal #1 mark area Reference land pattern layout (reference IPC7351 SOP65P640X110-8M); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Hall element, not to scale Active Area Depth 0.36 mm REF Line 1: Maximum 3 characters Line 2: Maximum 5 characters Line 1: Part Number Line 2: Logo A, 4-digit Date Code Standard Branding Reference View C Date Code XXX

High-Precision, Programmable Linear Hall-Effect Sensor IC with VREF, Overcurrent Fault, and High-Bandwidth (400 kHz) Analog Output for Core-Based Current SensingACS37600 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com For the latest version of this document, visit our website: www.allegromicro.com

Revision History

– October 13, 2020 Initial release

1 December 9, 2020

Updated Selection Guide and Part Numbering Specification (page 2), Functional Block Diagram (page 5), Characteristics table headings, Temperature Compensation Update Rate (page 6), Output Saturation Voltage, Response Time, Overshoot, Input Referred Noise Density, Output Noise, and Power Supply Sensitivity Error (page 7), Reference Output Noise, OCF Operating Characteristics (page 8), Programmable Characteristics (pages 9-10), Performance Characteristics (pages 11-12), Uni/Bidirectional Functionality (page 17), Definitions of Operating and Performance Characteristics (pages 18-25), Dynamic Output (page 27), Programming Parameters (pages 28-31), and Package Outline Drawing (page 36).

2 January 7, 2022 Updated package drawing (page 36)

3 March 28. 2023 Updated Nominal Absolute Field Range minimum value (page 4) Copyright 2023, Allegro MicroSystems. Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copies of this document are considered uncontrolled documents.