6276

6276 ALLEGRO | Alldatasheet

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26185.201B† 6276 16-BIT SERIAL-INPUT, CONSTANT- CURRENT LATCHED LED DRIVER Always order by complete part number, e.g., A6276EA . The A6276EA and A6276ELW are specifically designed for LED- display applications. Each BiCMOS device includes a 16-bit CMOS shift register, accompanying data latches, and 16 npn constant-current sink drivers. Except for package style and allowable package power dissipation, the two devices are identical. The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 5 V logic supply, typical serial data-input rates are up to 20 MHz. The LED drive current is deter- mined by the user’s selection of a single resistor. A CMOS serial data output permits cascade connections in applications requiring additional drive lines. For inter-digit blanking, all output drivers can be disabled with an ENABLE input high. Similar 8-bit devices are available as the A6275EA and A6275ELW. Two package styles are provided for through-hole DIP (suffix A) or surface-mount SOIC (suffix LW). Under normal applications, a copper lead frame and low logic-power dissipation allow the dual in-line package to sink maximum rated current through all outputs continu- ously over the operating temperature range (90 mA, 0.75 V drop, +85°C). Both devices are also available for operation over the standard temperature range of -20°C to +85°C. To order, change the suffix letter ‘E’ to ‘S’. Note that the A6276EA (DIP) and the A6276ELW (SOIC) are electrically identical and share a common terminal number assignment. A6276ELW ABSOLUTE MAXIMUM RATINGS Output Voltage Range, Input Voltage Range, Package Power Dissipation, Operating Temperature Range, Storage Temperature Range, Caution: These CMOS devices have input static protection (Class 2) but are still suscep- tible to damage if exposed to extremely high static electrical charges.

FEATURES

I To 90 mA Constant-Current Outputs I Under-Voltage Lockout I Low-Power CMOS Logic and Latches I High Data Input Rate I Functional Replacement for TB62706BN/BF GROUND REGISTER LATCHES 81 7 SERIAL DATA OUT LOGIC SUPPLY SERIAL DATA IN OUTPUT ENABLE LATCH ENABLE CLOCK CK V DD OE OUT 1 OUT 2 OUT 0 OUT 12 OUT 14 OUT 13 OUT 3 OUT 15 R EXT I REGULATOR L O OUT 5 OUT 6 OUT 4 OUT 7 13 Dwg. PP-029-11 OUT 8 OUT 10 OUT 9 OUT 11

16-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-50002 Copyright © 2000, 2003 Allegro MicroSystems, Inc. 50 75 100 125 150 2.5 0.5 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS AMBIENT TEMPERATURE IN °°°°C 2.0 1.5 1.0 Dwg. GP-022-3 24-LEAD SOIC, RθJA = 75°C/W 24-PIN DIP, RθJA = 50°C/W FUNCTIONAL BLOCK DIAGRAM MOS BIPOLAR GROUND LATCH ENABLE OUTPUT ENABLE (ACTIVE LOW) SERIAL DATA OUT CLOCK SERIAL DATA IN SERIAL-PARALLEL SHIFT REGISTER LATCHES VDD LOGIC SUPPLY R EXT OUT 0 OUT 1 Dwg. FP-013-3 OUT 2 OUT N I REGULATOR O UVLO

16-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER www.allegromicro.com 3 CLOCK and SERIAL DATA IN SERIAL DATA OUT LATCH ENABLEOUTPUT ENABLE (active low) Dwg. EP-010-11 IN VDD Dwg. EP-010-12 IN VDD Dw g. EP-010-13 IN VDD TRUTH TABLE Serial Shift Register Contents Serial Latch Latch Contents Output Output Contents Data Clock Data Enable Enable Input Input I HH R 1 R2 ... R N-2 RN-1 RN-1 LL R 1 R2 ... R N-2 RN-1 RN-1 XR 1 R2 R3 ... R N-1 RN RN L = Low Logic (Voltage) Level H = High Logic (Voltage) Level X = Irrelevant P = Present State R = Previous State VDD Dw g. EP-063-6 OUT

16-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER Worcester, Massachusetts 01615-0036 (508) 853-50004 ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V (unless otherwise noted). Limits Characteristic Symbol Test Conditions Min. Typ. Max. Unit Supply Voltage Range V DD Operating 4.5 5.0 5.5 V Under-Voltage Lockout V DD(UV) VDD = 0 ¡ 5 V 3.4 – 4.0 V Output Current I O VCE = 0.7 V, REXT = 250 Ω 64.2 75.5 86.8 mA (any single output) VCE = 0.7 V, REXT = 470 Ω 34.1 40.0 45.9 mA Output Current Matching ∆IO 0.4 V ≤ VCE(A) = VCE(B) ≤ 0.7 V: (difference between any R EXT = 250 Ω – ±1.5 ±6.0 % two outputs at same VCE) REXT = 470 Ω – ±1.5 ±6.0 % Output Leakage Current I CEX VOH = 15 V – 1.0 5.0 µA Logic Input Voltage V IH 0.7VDD –V DD V VIL GND – 0.3V DD V SERIAL DATA OUT V OL IOL = 500 µA – – 0.4 V Voltage VOH IOH = -500 µA 4.6 – – V Input Resistance R I ENABLE Input, Pull Up 150 300 600 k Ω LATCH Input, Pull Down 100 200 400 k Ω Supply Current I DD(OFF) REXT = open, VOE = 5 V – 0.8 1.4 mA REXT = 470 Ω , VOE = 5 V 3.5 6.0 8.0 mA REXT = 250 Ω , VOE = 5 V 6.5 11 15 mA IDD(ON) REXT = 470 Ω , VOE = 0 V 7.0 13 20 mA REXT = 250 Ω , VOE = 0 V 10 22 32 mA Typical Data is at VDD = 5 V and is for design information only.

16-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER www.allegromicro.com 5 SWITCHING CHARACTERISTICS at TA = 25°C, VDD = VIH = 5 V, VCE = 0.4 V, VIL = 0 V, REXT = 470 Ω , IO = 40 mA, VL = 3 V, RL = 65 Ω , CL = 10.5 pF. Limits Characteristic Symbol Test Conditions Min. Typ. Max. Unit Propagation Delay Time t pHL CLOCK-OUTn – 350 1000 ns LATCH-OUTn – 350 1000 ns ENABLE-OUTn – 350 1000 ns CLOCK-SERIAL DATA OUT – 40 – ns Propagation Delay Time t pLH CLOCK-OUTn – 300 1000 ns LATCH-OUTn – 300 1000 ns ENABLE-OUTn – 300 1000 ns CLOCK-SERIAL DATA OUT – 40 – ns Output Fall Time t f 90% to 10% voltage 150 350 1000 ns Output Rise Time t r 10% to 90% voltage 150 300 600 ns RECOMMENDED OPERATING CONDITIONS Characteristic Symbol Conditions Min. Typ. Max. Unit Supply Voltage V DD 4.5 5.0 5.5 V Output Voltage V O – 1.0 4.0 V Output Current I O Continuous, any one output – – 90 mA IOH SERIAL DATA OUT – – -1.0 mA IOL SERIAL DATA OUT – – 1.0 mA Logic Input Voltage V IH 0.7VDD –V DD + 0.3 V VIL -0.3 – 0.3V DD V Clock Frequency f CK Cascade operation – – 10 MHz

16-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER Worcester, Massachusetts 01615-0036 (508) 853-50006 TIMING REQUIREMENTS and SPECIFICATIONS (Logic Levels are VDD and Ground) A. Data Active Time Before Clock Pulse B. Data Active Time After Clock Pulse D. Time Between Clock Activation NOTE – Timing is representative of a 10 MHz clock. Significantly higher speeds are attainable. Information present at any register is transferred to the respective latch when the LATCH ENABLE is high (serial-to- parallel conversion). The latches will continue to accept new data as long as the LATCH ENABLE is held high. Applica- tions where the latches are bypassed (LATCH ENABLE tied high) will require that the OUTPUT ENABLE input be high during serial data entry. When the OUTPUT ENABLE input is high, the output source drivers are disabled (OFF). The information stored in the latches is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input low, the outputs are controlled by the state of their respective latches. CLOCK SERIAL DATA IN LATCH ENABLE OUTPUT ENABLE OUT N Dwg. WP-029-1 50%SERIAL DATA OUT DATA DATA 50% 50% 50% C A B D E LOW = ALL OUTPUTS ENABLED pt DATA 50% pt LOW = OUTPUT ON HIGH = OUTPUT OFF OUTPUT ENABLE OUT N Dwg. WP-030-1A DATA 10% 50% pHLt pLHt HIGH = ALL OUTPUTS DISABLED (BLANKED) ft rt 90% F 50%

16-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER www.allegromicro.com 7 ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE A6276EA A6276ELW 0 20 DUTY CYCLE IN PER CENT 100 Dwg. GP-062-11 ALLOWABLE OUTPUT CURRENT IN mA/BIT 6040 10080 VCE = 1 V VCE = 2 V VCE = 3 V VCE = 4 V TA = +25°C VDD = 5 V R θJA = 50°C/W 0 20 DUTY CYCLE IN PER CENT 100 Dwg. GP-062-10 ALLOWABLE OUTPUT CURRENT IN mA/BIT 6040 10080 VCE = 1 V VCE = 2 V TA = +50°C VDD = 5 V R θJA = 50°C/W VCE = 3 V VCE = 4 V 0 20 DUTY CYCLE IN PER CENT 100 Dwg. GP-062-6 ALLOWABLE OUTPUT CURRENT IN mA/BIT 6040 10080 VCE = 1 V VCE = 2 V VCE = 3 V VCE = 4 V TA = +25°C VDD = 5 V R θJA = 75°C/W VCE = 0.7 V 0 20 DUTY CYCLE IN PER CENT 100 Dwg. GP-062-7 ALLOWABLE OUTPUT CURRENT IN mA/BIT 6040 10080 VCE = 1 V VCE = 2 V VCE = 3 V TA = +50°C VDD = 5 V R θJA = 75°C/W VCE = 0.7 V VCE = 4 V

16-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER Worcester, Massachusetts 01615-0036 (508) 853-50008 0 20 DUTY CYCLE IN PER CENT 100 Dwg. GP-062-9 ALLOWABLE OUTPUT CURRENT IN mA/BIT 6040 10080 VCE = 1 V VCE = 2 V TA = +85°C VDD = 5 V R θJA = 50°C/W VCE = 3 V VCE = 0.7 V VCE = 4 V ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE (cont.) A6276EA A6276ELW TYPICAL CHARACTERISTICS 0.5 Dwg. GP-063 1.0 2.01.5 VCE IN VOLTS OUTPUT CURRENT IN mA/BIT TA = +25°C REXT = 500 Ω 0 20 DUTY CYCLE IN PER CENT 100 Dwg. GP-062-8 ALLOWABLE OUTPUT CURRENT IN mA/BIT 6040 10080 VCE = 1 V VCE = 2 V VCE = 3 V TA = +85°C VDD = 5 V R θJA = 75°C/W VCE = 4 V VCE = 0.7 V VCE = 0.4 V

16-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER www.allegromicro.com 9 TERMINAL DESCRIPTION Terminal No. Terminal Name Function 1 GND Reference terminal for control logic. 2 SERIAL DATA IN Serial-data input to the shift-register. 3 CLOCK Clock input terminal for data shift on rising edge. 4 LATCH ENABLE Data strobe input terminal; serial data is latched with high-level input. 5-20 OUT 0-15 The 16 current-sinking output terminals.

21 OUTPUT ENABLE When (active) low, the output drivers are enabled; when high, all output

drivers are turned OFF (blanked). 22 SERIAL DATA OUT CMOS serial-data output to the following shift-register.

23 R EXT An external resistor at this terminal establishes the output current for all sink

drivers. 24 SUPPLY (V DD ) The logic supply voltage (typically 5 V). The products described here are manufactured under one or more Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.

16-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER Worcester, Massachusetts 01615-0036 (508) 853-500010 The load current per bit (IO ) is set by the external resistor (REXT ) as shown in the figure below. 300 500 700 1 k 2 k CURRENT-CONTROL RESISTANCE, R EXT IN OHMS 100 100 Dwg. GP-061 OUTPUT CURRENT IN mA/BIT 5 k200 3 k VCE = 0.7 V Package Power Dissipation (PD). The maximum allowable package power dissipation is determined as PD (max) = (150 - TA )/RθJA. The actual package power dissipation is PD (act) = dc(VCE • IO • 16) + (VDD • IDD ). When the load supply voltage is greater than 3 V to 5 V, considering the package power dissipating limits of these devices, or if P D (act) > PD (max), an external voltage reducer (VDROP ) should be used. Load Supply Voltage (VLED). These devices are designed to operate with driver voltage drops (VCE ) of 0.4 V to 0.7 V with LED forward voltages (VF) of 1.2 V to 4.0 V. If higher voltages are dropped across the driver, package power dissipation will be increased significantly. To minimize package power dissipation, it is recom- mended to use the lowest possible load supply voltage or to set any series dropping voltage (V DROP ) as V DROP = VLED - VF - VCE with VDROP = Io • RDROP for a single driver, or a Zener diode (VZ), or a series string of diodes (approximately 0.7 V per diode) for a group of drivers. If the available voltage source will cause unacceptable dissipation and series resistors or diode(s) are undesirable, a regulator such as the Sanken Series SAI or Series SI can be used to provide supply voltages as low as 3.3 V. For reference, typical LED forward voltages are: White 3.5 – 4.0 V Blue 3.0 – 4.0 V Green 1.8 – 2.2 V Yellow 2.0 – 2.1 V Amber 1.9 – 2.65 V Red 1.6 – 2.25 V Infrared 1.2 – 1.5 V Pattern Layout. This device has a common logic- ground and power-ground terminal. If ground pattern layout contains large common-mode resistance, and the voltage between the system ground and the LATCH ENABLE or CLOCK terminals exceeds 2.5 V (because of switching noise), these devices may not operate correctly. Dw g. EP-064 VLED V DROP VF V CE Applications Information

16-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER www.allegromicro.com 11 A6276EA Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only) NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative 3. Lead thickness is measured at seating plane or below. 4. Supplied in standard sticks/tubes of 15 devices. 0.014 0.008 0.300 BSC Dwg. MA-001-24 in 0.430 MAX 1 12 0.280 0.240 0.210 MAX 0.070 0.045 0.015 MIN 0.022 0.014 0.100 BSC 0.005 MIN 0.150 0.115 1.280 1.230 0.355 0.204 7.62 BSC Dwg. MA-001-24 mm 10.92 MAX 1 12 7.11 6.10 5.33 MAX 1.77 1.15 0.39 MIN 0.558 0.356 2.54 BSC 0.13 MIN 3.81 2.93 32.51 31.24

16-BIT SERIAL-INPUT, CONSTANT-CURRENT LATCHED LED DRIVER Worcester, Massachusetts 01615-0036 (508) 853-500012 NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Supplied in standard sticks/tubes of 31 devices or add “TR ” to part number for tape and reel. 0° TO 8° 1 2 30.020 0.013 0.0040 MIN. 0.0125 0.0091 0.050 0.016 Dwg. MA-008-24A in 0.050 BSC 24 13 0.2992 0.2914 0.419 0.394 0.6141 0.59850.0926 0.1043 0° TO 8° 2 30.51 0.33 0.10 MIN. 0.32 0.23 1.27 0.40 Dwg. MA-008-24A mm 1.27 BSC 7.60 7.40 10.65 10.00 15.60 15.202.65 2.35 A6276ELW Dimensions in Inches (for reference only) Dimensions in Millimeters (controlling dimensions)