ACPM-7372-TR1

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Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 16

Technical content

Features

• Thin Package (0.9mm typ)Thin Package (0.9mm typ)
• Excellent inearityExcellent inearity
• 3-mode power control with bp and mode3-mode power control with bp and mode – Bypass / Mid Power Mode / High Power Mode
• High Efficiency at max output powerHigh Efficiency at max output power
• 10-pin surface mounting package10-pin surface mounting package
• Internal 50ohm matching networks for both inputInternal 50ohm matching networks for both input and output
• ead-free, oHS compliant, Green

Applications

• UMTS Band8UMTS Band8 Block Diagram

Ordering Information

Part Number Number of Devices Container ACPM-7372-T1 1,000 178mm (7”) Tape/eel ACPM-7372-BK 100 BUK RF In(4) RF Out(8) Vcc1(5) Vbp(3) Ven(1) Vmode(2) Impedence Transformer Bypass Circuit Output Match Input Match & Power Divider Inter-Stage Match Vcc2(6) Bias Circuit & Control Logic

No damage assuming only one parameter is set at limit at a time with all other parameters set at or below nominal value. set at or below nominal value.set at or below nominal value. Operation of any single parameter outside these conditions with the remaining parameters set at or below nominal values may result in permanent damage. Description Min. Typ. Max. Unit Input Power (Pin) 0 10* dBm DC Supply oltage (cc1, cc2) 0 3.4 5.0 Enable oltage (en) 0 2.6 3.3 Mode Control oltage (mode) 0 2.6 3.3 Bypass Control (bp) 0 2.6 3.3 Storage Temperature (Tstg) -55 25 +125 °C * High Power Mode (5dBm for Bypass and Mid Power Mode) Recommended Operating Condition Description Min. Typ. Max. Unit DC Supply oltage (cc1, cc2) 3.2 3.4 4.2 Enable oltage (en) ow High 1.35 2.6 0.5 3.1 Mode Control oltage (mode) ow High 1.35 2.6 0.5 3.1 Bypass Control oltage (bp) ow High 1.35 2.6 0.5 3.1 Operating requency (fo) 880 915 MHz Ambient Temperature (Ta) -20 25 85 °C Operating Logic Table Power Mode Ven Vmode Vbp Pout (Rel99) Pout (HSDPA, HSUPA MPR=0dB) High Power Mode High ow ow ~ 28.5 dBm ~ 27.5 dBm Mid Power Mode High High ow ~ 17 dBm ~ 16 dBm Bypass Mode High High High ~ 8 dBm ~ 7 dBm Shut Down Mode ow ow ow – –

Electrical Characteristics for WCDMA Mode – Conditions: cc = 3.4, en = 2.6, T = 25°C, in/out = 50ohm, T = 25°C, in/out = 50ohmT = 25°C, in/out = 50ohm Characteristics Condition Min. Typ. Max. Unit Operating requency ange 880 – 915 MHz Gain High Power Mode, Pout=28.5dBm 24 27 dB Mid Power Mode, Pout=17dBm 13 17 dB Bypass Mode, Pout=8dBm 8 12 16 dB GPS Band Gain relative to Tx Gain, HPM Ggps@Pin=-15dBm – Gtx@Pout=28.5dBm -24 -3 dB x Band Gain relative to Tx Gain, HPM Grx@Pin=-15dBm – Gtx@Pout=28.5dBm -0.9 -0.5 dB ISM Band Gain relative to Tx Gain, HPM Gism@Pin=-15dBm – Gtx@Pout=28.5dBm -68 -6 dB Power Added Efficiency High Power Mode, Pout=28.5dBm 32.7 37.1 % Mid Power Mode, Pout=17dBm 14.4 19.3 % Bypass Mode, Pout=8dBm 8.7 12.4 % Total Supply Current High Power Mode, Pout=28.5dBm 560 635 mA Mid Power Mode, Pout=17dBm 75 100 mA Bypass Mode, Pout=8dBm 14 20 mA Quiescent Current High Power Mode 70 90 110 mA Mid Power Mode 10 20 30 mA Bypass Mode 2.3 3.3 4.3 mA Enable Current High Power Mode 10 25 µA Mid Power Mode 10 25 µA Bypass Mode 10 25 µA Mode Control Current Mid Power Mode 5 25 µA Bypass Mode 5 25 µA Bypass Control Current Bypass 5 25 µA Total Current in Power-down mode en=0, mode=0, bp=0 5 µA Adjacent Channel eakage atio

5 MHz offset

10 MHz offset

High Power Mode, Pout=28.5dBm -42 -55 -37 -47 dBc dBc High Power Mode, Pout=27.5dBm (HSDPA, HSUPA MP=0dB) -39 -55 -36 -47 dBc dBc Mid Power Mode, Pout=17dBm -44 -60 -37 -47 dBc dBc Mid Power Mode, Pout=16dBm (HSDPA, HSUPA MP=0dB) -42 -57 -37 -47 dBc dBc Bypass Mode, Pout=8dBm -43 -57 -37 -47 dBc dBc Bypass Mode, Pout=7dBm (HSDPA, HSUPA MP=0dB) -42 -55 -37 -47 dBc dBc

Electrical Characteristics for WCDMA Mode – Conditions: cc = 3.4, en = 2.6, T = 25°C, in/out = 50ohm, T = 25°C, in/out = 50ohmT = 25°C, in/out = 50ohm Characteristics Condition Min. Typ. Max. Unit Harmonic Suppression Second Third High Power Mode, Pout=28.5dBm -45 -60 -35 -40 dBc dBc Gain at Harmonics Second and Third 0 dB Input SW 1.3 2.5:1 Stability (Spurious Output) oad SW 5:1, All phase -60 dBc x Band Noise Power (cc=4.2) High Power Mode, Pout=28.5dBm -135.5 -134 dBm/Hz GPS Band Noise (cc=4.2) High Power Mode, Pout=28.5dBm -152 -140 dBm/Hz ISM Band Noise (cc=4.2) High Power Mode, Pout=28.5dBm -159 -144 Phase Discontinuity HPM↔MPM, Pout=17dBm MPM↔BPM, Pout=8dBm deg deg uggedness Pout<28.5dBm & Pin<5dBm, All phase, High Power Mode 8:1 SW 1. HSDPA - 3GPP TS 34.121-1 - User Equipment (UE) conformance specification; adio transmission and reception (DD); Part 1: Conformance specification - Annex C (normative): Measurement channels - C.10.1 U reference measurement channel for HSDPA tests - Table C.10.1.4: β values for transmitter characteristics tests with HS-DPCCH - Sub-test 2 (CM=1.0dB, MP=0.0dB) 2. HSUPA - 3GPP TS 34.121-1 - User Equipment (UE) conformance specification; adio transmission and reception (DD); Part 1: Conformance specification - Annex C (normative): Measurement channels - C.11.1 U reference measurement channel for E-DCH tests - Table C.11.1.3: β values for transmitter characteristics tests with HS-DPCCH and E-DCH - Sub-test 1 (CM=1.0dB, MP=0.0dB)

All dimensions are in millimeter PIN Description Pin # Name Description 1 en PA Enable 2 mode Mode Control 3 bp Bypass Control 4 in Input 5 cc1 DC Supply oltage 6 cc2 DC Supply oltage

7 GND Ground

9 GND Ground

10 GND Ground

All dimensions are in millimeter 4 ± 0.1 4 ± 0.1 Pin 1 Mark 0.6 0.9 ± 0.1 Marking Specification 1.90 1.70 0.85 1.20 1.90 0.40 0.40 0.10 X-Ray Top View Pin 1 Mark AVAGO ACPM-7372 PYYWW AAAAA Manufacturing Part Number Lot Number P Manufacturing info YY Manufacturing Year WW Work Week AAAAA Assembly Lot Number

Figure 1. PDF and Current output power ranges are high. on/off is controlled by en. This is digitally control pin. tion more, which accordingly gives extended talk time. cation of current and probability at each output power. tion is lowered. is lowered. not require constant voltage for interface.. of handset more compared with the CP4.

Application on mobile phone board Application example in mobile is shown below. C4 and C5 should be placed close to pin1 and pin10. Bypass cap C1, C2 and C3 should be also placed nearby from pin5, pin4 and pin3, respectively. The length of post-PA transmission line should be minimized to reduce line loss. Peripheral Circuits PCB layout and part placement on phone board Via hole PCB guideline on phone board Note 1. To prevent voltage drop, make the bias lines as wide as possible (Pink line). 2. Use many via holes to fence off PA input and output traces for better isolation. Output signal of the PA should be isolated from input signal and the receive signal. Output signal should not be fed into PA input. (Green line) 3. Use via holes to connect outer ground plates to internal ground planes. They help heat spread out more easily and accordingly the board temperature can be lowered. They also help to improve stability (Yellow square). 4. PA which has a ground slug requires many via holes which go through all the layers (ed square). BB output matching circuitACPM-7372 PA_R1 PA_R0 PA_ON Ven Vmode Vbp IN Vc1 GND GNDOUT GND Vcc2 TX filter RF In Coupler RF Out VBATT

0.25 0.85 0.4 0.6 0.5 0.1 Ø0.3mm on 0.6mm pitch Solder Mask Opening 0.7 0.5 0.55 0.85 2.4 1.8 Solder Paste Stencil Aperture 0.6 0.5 1.6 2.0 0.85 0.4 PCB Design Guidelines The recommended PCB land pattern is shown in figures on the left side. The substrate is coated with solder mask between the I/O and conductive paddle to protect the gold pads from short circuit that is caused by solder bleeding/bridging. Stencil Design Guidelines A properly designed solder screen or stencil is required to ensure optimum amount of solder paste is deposited onto the PCB pads. The recommended stencil layout is shown here. educing the stencil opening can potentially generate more voids. On the other hand, stencil openings larger than 100% will lead to excessive solder paste smear or bridging across the I/O pads or conductive paddle to adjacent I/O pads. Considering the fact that solder paste thickness will directly affect the quality of the solder joint, a good choice is to use laser cut stencil composed of 0.100mm(4mils) or 0.127mm(5mils) thick stainless steel which is capable of producing the required fine stencil outline.

1 Ven

2 Vmode

3 Vbp

4 RF in

5 Vcc1 Vcc2 6

2.2uF Ven 100pF 2.2uF 680pF Evaluation Board Description C5 C2 C1 C5 C7 AVAGO ACPM-7372 PYYWW AAAAA C5 C7 Evaluation Board Schematic

Annote Millimeter Annote Millimeter A0 4.40±0.10 P2 2.00±0.05 B0 4.40±0.10 P10 40.00±0.20 K0 1.70±0.10 E 1.75±0.10 D1 1.60±0.10 W 12.00±0.30 P0 4.00±0.10 T 0.30±0.05 P1 8.00±0.10 Tape and eel ormat – 4 mm x 4 mm.

NOTES: 1. eel shall be labeled with the following information (as a minimum). a. manufacturers name or symbol b. Avago Technologies part number c. purchase order number d. date code e. quantity of units 2. A certi cate of compliance (c of c) shall be issued and accompany each shipment of product. 3. eel must not be made with or contain ozone depleting materials. 4. All dimensions in millimeters (mm) 50 min. 12.4 +2.0 -0.0 18.4 max. min wide (ref) Slot for carrier tape insertion for attachment to reel hub (2 places 180° apart) BACK VIEW FRONT VIEW 178 Shading indicates thru slots +0.4 -0.2 21.0 ± 0.8 13.0 ± 0.2 1.5 min. Plastic eel ormat (all dimensions are in millimeters)

ESD (Electrostatic Discharge) Electrostatic discharge occurs naturally in the environ - ment. With the increase in voltage potential, the outlet of neutralization or discharge will be sought. If the acquired discharge route is through a semiconductor device, de - structive damage will result. ESD countermeasure methods should be developed and used to control potential ESD damage during handling in a factory environment at each manufacturing site. MSL (Moisture Sensitivity Level) Plastic encapsulated surface mount package is sensitive to damage induced by absorbed moisture and temperature. Avago Technologies follows JEDEC Standard J-STD 020B. Each component and package type is classified for moisture sensitivity by soaking a known dry package at various temperatures and relative humidity, and times. After soak, the components are subjected to three con - secutive simulated reflows. The out of bag exposure time maximum limits are de - termined by the classification test describe below which corresponds to a MS classification level 6 to 1 according to the JEDEC standard IPC/JEDEC J-STD-020B and J-STD- 033. ACPM-7372 is MS3. Thus, according to the J-STD-033 p.11 the maximum Manufacturers Exposure Time (MET) for this part is 168 hours. After this time period, the part would need to be removed from the reel, de-taped and then re-baked. MS classification reflow temperature for the ACPM-7372 is targeted at 260°C +0/-5°C. igure and table on next page show typical SMT profile for maximum temperature of 260 +0/-5°C. Moisture Classification Level and Floor Life MS evel loor ife (out of bag) at factory ambient = < 30°C/60% H or as stated

1 Unlimited at = < 30°C/85% H

6 Mandatory bake before use. After bake, must be reflowed within the time limit specified on the label Note : 1. The MS evel is marked on the MS abel on each shipping bag.

Reflow Profile Recommendations Time Temperature Tp TL tp tL t 25°C to Peak Ramp-up ts Tsmin Ramp-down Preheat Critical Zone TL to Tp Tsmax Typical SMT eflow Profile for Maximum Temperature = 260 +0/-5°C. Typical SMT Reflow Profile for Maximum Temperature = 260 +0/-5°C Profile Feature Sn-Pb Solder Pb-Free Solder Average ramp-up rate (T to TP) 3°C/sec max 3°C/sec max Preheat – Temperature Min (Tsmin) – Temperature Max (Tsmax) – Time (min to max) (ts) 100°C 150°C 60-120 sec 150°C 200°C 60-180 sec Tsmax to T – amp-up ate 3°C/sec max Time maintained above: – Temperature (T) – Time (T) 183°C 60-150 sec 217°C 60-150 sec Peak temperature (Tp) 240 +0/-5°C 260 +0/-5°C Time within 5°C of actual Peak Temperature (tp) 10-30 sec 20-40 sec amp-down ate 6°C/sec max 6°C/sec max Time 25°C to Peak Temperature 6 min max. 8 min max.

Packages described in this document must be stored in sealed moisture barrier, antistatic bags. Shelf life in a sealed moisture barrier bag is 12 months at <40°C and 90% relative humidity (H) J-STD-033 p.7. Out-of-Bag Time Duratio n After unpacking the device must be soldered to the PCB within 168 hours as listed in the J-STD-020B p.11 with factory conditions <30°C and 60% H. Baking It is not necessary to re-bake the part if both conditions (storage conditions and out-of bag conditions) have been satisfied. Baking must be done if at least one of the con - ditions above have not been satisfied. The baking condi - tions are 125°C for 12 hours J-STD-033 p.8. CAUTION Tape and reel materials typically cannot be baked at the temperature described above. If out-of-bag exposure time is exceeded, parts must be baked for a longer time at low temperatures, or the parts must be de-reeled, de- taped, re-baked and then put back on tape and reel. (See moisture sensitive warning label on each shipping bag for information of baking). Board Rework Component Removal, Rework and Remount If a component is to be removed from the board, it is recommended that localized heating be used and the maximum body temperatures of any surface mount component on the board not exceed 200°C. This method will minimize moisture related component damage. If any component temperature exceeds 200°C, the board must be baked dry per 4-2 prior to rework and/or component removal. Component temperatures shall be measured at the top center of the package body. Any SMD packages that have not exceeded their floor life can be exposed to a maximum body temperature as high as their specified maximum reflow temperature. Removal for Failure Analysis Not following the above requirements may cause moisture/ reflow damage that could hinder or completely prevent the determination of the original failure mechanism. Baking of Populated Boards Some SMD packages and board materials are not able to withstand long duration bakes at 125°C. Examples of this are some -4 materials, which cannot withstand a 24 hr bake at 125°C. Batteries and electrolytic capacitors are also temperature sensitive. With component and board temperature restrictions in mind, choose a bake tem - perature from Table 4-1 in J-STD 033; then determine the appropriate bake duration based on the component to be removed. or additional considerations see IPC-7711 andIPC-7721. Derating due to Factory Environmental Conditions actory floor life exposures for SMD packages removed from the dry bags will be a function of the ambient envi - ronmental conditions. A safe, yet conservative, handling approach is to expose the SMD packages only up to the maximum time limits for each moisture sensitivity level as shown in next table. This approach, however, does not work if the factory humidity or temperature is greater than the testing conditions of 30°C/60% H. A solution for addressing this problem is to derate the exposure times based on the knowledge of moisture diffusion in the component package materials ref. JESD22-A120). ecommended equivalent total floor life exposures can be estimated for a range of humidities and temperatures based on the nominal plastic thickness for each device. Table on next page lists equivalent derated floor lives for humidities ranging from 20-90% H for three tempera - ture, 20°C, 25°C, and 30°C. Table on next page is applicable to SMDs molded with novolac, biphenyl or multifunctional epoxy mold compounds. The following assumptions were used in cal- culating this table: 1. Activation Energy for diffusion = 0.35e (smallest known value). 2. or ≤60% H, use Diffusivity = 0.121exp (-0.35e/kT) mm2/s (this used smallest known Diffusivity @ 30°C). 3. or >60% H, use Diffusivity = 1.320exp (-0.35e/kT) mm2/s (this used largest known Diffusivity @ 30°C).

Recommended Equivalent Total Floor Life (days) @ 20°C, 25°C & 30°C, 35°C or ICs with Novolac, Biphenyl and Multifunctional Epoxies ( eflow at same temperature at which the component was classified) Maximum Percent elative Humidity Maximum Percent Relative Humidity Package Type and Body Thickness Moisture Sensitivity Level 5% 10% 20% 30% 40% 50% 60% 70% 80% 90% Body Thickness ≥3.1 mm Including PQPs >84 pin, PCCs (square) All MQPs or All BGAs ≥1 mm evel 2a ∞ 124 167 231 103 35°C 30°C 25°C 20°C evel 3 ∞ 35°C 30°C 25°C 20°C evel 4 ∞ 35°C 30°C 25°C 20°C evel 5 ∞ 35°C 30°C 25°C 20°C evel 5a ∞ 35°C 30°C 25°C 20°C Body 2.1 mm ≤ Thickness <3.1 mm including PCCs (rectangular) 18-32 pin SOICs (wide body) SOICs ≥20 pins, PQPs ≤80 pins evel 2a ∞ 148 35°C 30°C 25°C 20°C evel 3 ∞ 35°C 30°C 25°C 20°C evel 4 ∞ 35°C 30°C 25°C 20°C evel 5 ∞ 35°C 30°C 25°C 20°C evel 5a ∞ 0.5 0.5 0.5 0.5 35°C 30°C 25°C 20°C Body Thickness <2.1 mm including SOICs <18 pin All TQPs, TSOPs or All BGAs <1 mm body thickness evel 2a ∞ 0.5 0.5 35°C 30°C 25°C 20°C evel 3 ∞ 0.5 0.5 35°C 30°C 25°C 20°C evel 4 ∞ 0.5 0.5 35°C 30°C 25°C 20°C evel 5 ∞ 0.5 0.5 35°C 30°C 25°C 20°C evel 5a ∞ 0.5 0.5 0.5 35°C 30°C 25°C 20°C

For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved. AV02-1947EN - May 29, 2009