ACPM-5011

ACPM-5011 AVAGO | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 13

Technical content

Features

• Thin Package (0.9 mm typ)
• Excellent Linearity
• 3-mode power control with Vbp and Vmode
• Bypass / Mid Power Mode / High Power Mode
• High Efficiency at max output power
• 10-pin surface mounting package
• Internal 50 ohm matching networks for both RF input and output
• Integrated coupler
• Coupler and Isolation ports for daisy chain
• Green – Lead-free and RoHS complian

Applications

• UMTS(HSPA+)/LTE Handset for Band11 and Band 21

Ordering Information

ACPM-5011-TR1 1000 178 mm (7”) Tape/Reel ACPM-5011-BLK 100 Bulk

No damage assuming only one parameter is set at limit at a time with all other parameters set at or below nominal value. Operation of any single parameter outside these conditions with the remaining parameters set at or below nominal values may result in permanent damage. Description Min. Typ. Max. Unit RF Input Power (Pin) 0 10.0 dBm DC Supply Voltage (Vcc1, Vcc2) 0 3.4 5.0 V Enable Voltage (Ven) 0 2.6 3.3 V Mode Control Voltage (Vmode) 0 2.6 3.3 V Bypass Control (Vbp) 0 2.6 3.3 V Storage Temperature (Tstg) -55 25 +125 °C Recommended Operating Condition Description Min. Typ. Max. Unit DC Supply Voltage (Vcc1, Vcc2) 3.2 3.4 4.2 V Enable Voltage (Ven) Low High 1.35 2.6 0.5 3.1 V V Mode Control Voltage (Vmode) Low High 1.35 2.6 0.5 3.1 V V Bypass Control Voltage (Vbp) Low High 1.35 2.6 0.5 3.1 V V Operating Frequency (fo) 1427.9 1462.9 MHz Ambient Temperature (Ta) -20 25 90 °C Operating Logic Table Power Mode Ven Vmode Vbp Pout (UMTS Rel99) Pout (LTE MPR = 0 dB, HSPA+) High Power Mode High Low Low ~ 28.5 dBm ~ 27.5 dBm Mid Power Mode High High Low ~ 17 dBm ~ 16 dBm Bypass Mode High High High ~ 7 dBm ~ 6 dBm Shut Down Mode Low Low Low – –

Electrical Characteristics

– Conditions: Vcc = 3.4 V, Ven = 2.6 V, Ta = 25° C, Zin/Zout = 50 ohm Common Characteristics for LTE and UMTS Condition Min. Typ. Max. Unit Operating Frequency Range 1427.9 – 1462.9 MHz Quiescent Current High Power Mode 69 92 120 mA Mid Power Mode 9 16 25 mA Bypass Mode 1 3 5 mA Enable Current High Power Mode 4 100 µA Mid Power Mode 4 100 µA Bypass Mode 4 100 µA Mode Control Current Mid Power Mode 2.8 100 µA Bypass Mode 3.8 100 µA Bypass Control Current Bypass 3.8 100 µA Total Current in Power-down mode Ven = 0 V, Vmode = 0 V, Vbp = 0 V 10 µA Input VSWR 2:1 Stability (Spurious Output) VSWR 5:1, All phase -70 dBc Phase Discontinuity low power mode ↔ mid power mode, at Pout = 7 dBm mid power mode ↔ high power mode, at Pout = 16 dBm deg deg Ruggedness Pout <27.5 dBm, Pin <10 dBm, All phase High Power Mode 10:1 VSWR Coupling factor RF Out to CPL port 20 dB Daisy Chain Insertion Loss ISO port to CPL port, 698 - 2620 MHz, Ven = Low 0.25 dB Characteristics for UMTS Condition Min. Typ. Max. Unit Operating Frequency Range 1427.9 – 1462.9 MHz Maximum Output Power (UMTS Rel99) High Power Mode 28.5 dBm Mid Power Mode 17 dBm Bypass Mode 7 dBm Maximum Output Power (HSPA+, MPR = 0 dB) High Power Mode 27.5 dBm Mid Power Mode 16 dBm Bypass Mode 6 dBm Gain High Power Mode, Pout = 27.5 dBm 25 28.5 dB Mid Power Mode, Pout = 16 dBm 13 17.5 dB Bypass Mode, Pout = 6 dBm 8 12 dB Power Added Efficiency High Power Mode, Pout = 28.5 dBm, Rel99 41 % High Power Mode, Pout = 27.5 dBm, HSPA+, MPR = 0 dB 33.7 37.5 41.3 % Mid Power Mode, Pout = 16 dBm 15.1 20.9 27.4 % Bypass Mode, Pout = 6 dBm 3.1 6.5 11 % Total Supply Current High Power Mode, Pout = 27.5 dBm 400 440 490 mA Mid Power Mode, Pout = 16 dBm 42 55 76 mA Bypass Mode, Pout = 6 dBm 10 17 35 mA Adjacent Channel Leakage Ratio ACLR1 Pout < (maximum power – MPR), High Power Mode -38 -36 dBc ACLR2 Pout < (maximum power – MPR), High Power Mode -55 -46 dBc Harmonic Suppression Second Third High Power Mode, Pout = 27.5 dBm -39 -52 -35 -42 dBc dBc Rx Band Noise Power (Vcc = 4.2 V) High Power Mode, Pout = 27.5 dBm -136.5 -135 dBm/Hz GPS Band Noise Power (Vcc = 4.2 V) High Power Mode, Pout = 27.5 dBm -136.5 -135 dBm/Hz ISM Band Noise Power (Vcc = 4.2 V) High Power Mode, Pout = 27.5 dBm -153 -143 dBm/Hz

Electrical Characteristics (Continued) Characteristics for LTE (Band 11 and Band21) Condition Min. Typ. Max. Unit Operating Frequency Range 1427.9 – 1462.9 MHz Maximum Output Power (LTE, MPR = 0 dB) High Power Mode 27.5 dBm Mid Power Mode 16 dBm Bypass Mode 6 dBm Gain High Power Mode, Pout ≤ (max power - MPR ) 25 28.5 dB Mid Power Mode, Pout ≤ (max power - MPR ) 13 17.5 dB Bypass Mode, Pout ≤ (max power - MPR ) 8 12 dB Power Added Efficiency High Power Mode, Pout = 27.5 dBm (MPR = 0 dB) 33.7 37.1 41.3 % High Power Mode, Pout = 26.5 dBm (MPR = 1 dB) 30.2 34 37 % Mid Power Mode, Pout = 16 dBm (MPR = 0 dB) 15.5 21.1 27.6 % Bypass Mode, Pout = 6 dBm (MPR = 0 dB) 3.1 6.1 11 % Total Supply Current High Power Mode, Pout = 27.5 dBm (MPR = 0 dB) 400 445 490 mA High Power Mode, Pout = 26.5 dBm (MPR = 1 dB) 355 390 435 mA Mid Power Mode, Pout = 16 dBm (MPR = 0 dB) 42 55 76 mA Bypass Mode, Pout = 6 dBm (MPR = 0 dB) 10 18 35 mA LTE Adjacent Channel Leakage Ratio E-UTRAACLR Pout < (maximum power – MPR), High Power Mode -37 -33 dBc UTRAACLR1 Pout < (maximum power – MPR), High Power Mode -43 -36 dBc UTRAACLR2 Pout < (maximum power – MPR), High Power Mode -57 -39 dBc Harmonic Suppression Second Third High Power Mode, Pout = 27.5 dBm -39 -52 -35 -42 dBc dBc Rx Band Noise Power (Vcc = 4.2 V) B11 High Power Mode, Pout = 26.5 dBm, 25RB, Ch_BW = 10 MHz (averaging across 9 MHz) B21 High Power Mode, Pout = 26.5 dBm, 25RB, Ch_BW = 15 MHz (averaging across 13.5 MHz) -136.5 -133.5 -135 -132 dBm/Hz GPS Band Noise Power (Vcc = 4.2 V) B11 High Power Mode, Pout = 26.5 dBm, 50RB B21 High Power Mode, Pout = 26.5 dBm, 75RB -136.5 -135 -135 -133 dBm/Hz ISM Band Noise Power (Vcc = 4.2 V) High Power Mode -153 -143 dBm/Hz

Pin # Name Description

1 Vcc1 DC Supply Voltage

2 RFin RF Input

3 Vbp Bypass Control

4 Vmode Mode Control

5 Ven PA Enable

6 CPL Coupling port of Coupler

7 GND Ground

8 ISO Isolation port of Coupler

9 RFOut RF Out

10 Vcc2 DC Supply Voltage

0.125 0.10 0.35 0.35 0.60 0.10 1.50 0.25 0.3 All dimensions are in millimeter Package Dimensions Marking Specification All dimensions are in millimeter Pi n 1 M a rk 3 ± 0.1 3 ± 0.1 0 .5 0.9 ± 0.1 Pin 1 Mark Manufacturing Part Number Lot Number P Manufacturing Info YY Manufacturing Year WW Work Week AAAAA Assemby Lot Number A5011 PYYWW AAAAA

Solder Paste Stencil Aperture PCB Design Guidelines The recommended PCB land pattern is shown in figures on the left side. The substrate is coated with solder mask between the I/O and conductive paddle to protect the gold pads from short circuit that is caused by solder bleeding/bridging. Stencil Design Guidelines A properly designed solder screen or stencil is required to ensure optimum amount of solder paste is deposited onto the PCB pads. The recommended stencil layout is shown here. Reducing the stencil opening can potentially generate more voids. On the other hand, stencil openings larger than 100% will lead to excessive solder paste smear or bridging across the I/O pads or conductive paddle to adjacent I/O pads. Con - sidering the fact that solder paste thickness will directly affect the quality of the solder joint, a good choice is to use laser cut stencil composed of 0.100 mm(4 mils) or 0.127 mm (5 mils) thick stainless steel which is capable of producing the required fine stencil outline. 0. 30 0. 60 0. 35 0. 55 0. 45 on 0.5 mm pitch Ø 0.3 mm 0. 475 connected to a inner layer through a via hole for a better isolation between CPL_IN(ISO) and RFout 0.65 0.45 0.50 0.60 1.50 1.30 0.525 0.55 0.45 1.10 1.10 0.60 0.35 0.475

Evaluation Board Schematic Evaluation Board Description

1 Vcc1

2 RF In

3 Vbp

4 Vmode

5 Ven

2.2 µF C6 C7 680 pF 680 pF 2.2 µF Vbp 100 pF ISO 8 RF Out Coupler 50 ohm

A0 3.40±0.10 B0 3.40±0.10 K0 1.35±0.10 D0 1.55±0.05 D1 1.60±0.10 P0 4.00±0.10 P1 8.00±0.10 Annote Millimeter P2 2.00±0.05 P10 40.00±0.20 E 1.75±0.10 F 5.50±0.05 W 12.00±0.30 T 0.30±0.05 Tape and Reel Format – 3 mm x 3 mm A5011 PYYWW AAAAA

Plastic Reel Format (all dimensions are in millimeters) Reel Drawing NOTES: 1. Reel shall be labeled with the following information (as a minimum). a. manufacturers name or symbol b. Avago Technologies part number c. purchase order number d. date code e. quantity of units 2. A certificate of compliance (c of c) shall be issued and accompany each shipment of product. 3. Reel must not be made with or contain ozone depleting materials. 4. All dimensions in millimeters (mm) 50 min. 12.4 +2.0 -0.0 18.4 max. min wide (ref) Slot for carrier tape insertion for attachment to reel hub (2 places 180° apart) BACK VIEW FRONT VIEW 178 Shading indicates thru slots +0.4 -0.2 21.0 ± 0.8 13.0 ± 0.2 1.5 min.

ESD (Electrostatic Discharge) Electrostatic discharge occurs naturally in the environ - ment.With the increase in voltage potential, the outlet of neutralization or discharge will be sought. If the acquired discharge route is through a semiconductor device, de - structive damage will result. ESD countermeasure methods should be developed and used to control potential ESD damage during handling in a factory environment at each manufacturing site. MSL (Moisture Sensitivity Level) Plastic encapsulated surface mount package is sensitive to damage induced by absorbed moisture and temperature. Avago Technologies follows JEDEC Standard J-STD 020B. Each component and package type is classified for moisture sensitivity by soaking a known dry package at Moisture Classification Level and Floor Life MSL Level Floor Life (out of bag) at factory ambient = < 30° C/60% RH or as stated

1 Unlimited at = < 30° C/85% RH

6 Mandatory bake before use. After bake, must be reflowed within the time limit specified on the label Note: 1. The MSL Level is marked on the MSL Label on each shipping bag. various temperatures and relative humidity, and times. After soak, the components are subjected to three con - secutive simulated reflows. The out of bag exposure time maximum limits are deter- mined by the classification test describe below which cor- responds to a MSL classification level 6 to 1 according to the JEDEC standard IPC/JEDEC J-STD-020B and J-STD-033. ACPM-5011 is MSL3. Thus, according to the J-STD-033 p.11 the maximum Manufacturers Exposure Time (MET) for this part is 168 hours. After this time period, the part would need to be removed from the reel, de-taped and then re-baked. MSL classification reflow temperature for the ACPM-5011 is targeted at 260° C +0/-5° C. Figure and table on next page show typical SMT profile for maximum temperature of 260 +0/-5° C.

Reflow Profile Recommendations Typical SMT Reflow Profile for Maximum Temperature = 260 +0/-5° C Time Temperature Tp TL tp tL t 25° C to Peak Ramp-up ts Tsmin Ramp-down Preheat Critical Zone TL to Tp Tsmax Typical SMT Reflow Profile for Maximum Temperature = 260 +0/-5° C Profile Feature Sn-Pb Solder Pb-Free Solder Average ramp-up rate (TL to TP) 3° C/sec max 3° C/sec max Preheat – Temperature Min (Tsmin) – Temperature Max (Tsmax) – Time (min to max) (ts) 100° C 150° C 60-120 sec 150° C 200° C 60-180 sec Tsmax to TL – Ramp-up Rate 3° C/sec max Time maintained above: – Temperature (TL) – Time (TL) 183° C 60-150 sec 217° C 60-150 sec Peak temperature (TP) 240 +0/-5° C 260 +0/-5° C Time within 5° C of actual Peak Temperature (TP) 10-30 sec 20-40 sec Ramp-down Rate 6° C/sec max 6° C/sec max Time 25° C to Peak Temperature 6 min max. 8 min max.

Packages described in this document must be stored in sealed moisture barrier, antistatic bags. Shelf life in a sealed moisture barrier bag is 12 months at <40° C and 90% relative humidity (RH) J-STD-033 p.7. Out-of-Bag Time Duration After unpacking the device must be soldered to the PCB within 168 hours as listed in the J-STD-020B p.11 with factory conditions <30° C and 60% RH. Baking It is not necessary to re-bake the part if both conditions (storage conditions and out-of bag conditions) have been satisfied. Baking must be done if at least one of the con - ditions above have not been satisfied. The baking condi - tions are 125° C for 12 hours J-STD-033 p.8. CAUTION Tape and reel materials typically cannot be baked at the temperature described above. If out-of-bag exposure time is exceeded, parts must be baked for a longer time at low temperatures, or the parts must be de-reeled, de-taped, re-baked and then put back on tape and reel. (See moisture sensitive warning label on each shipping bag for information of baking). Board Rework Component Removal, Rework and Remount If a component is to be removed from the board, it is recommended that localized heating be used and the maximum body temperatures of any surface mount component on the board not exceed 200° C. This method will minimize moisture related component damage. If any component temperature exceeds 200° C, the board must be baked dry per 4-2 prior to rework and/or component removal. Component temperatures shall be measured at the top center of the package body. Any SMD packages that have not exceeded their floor life can be exposed to a maximum body temperature as high as their specified maximum reflow temperature. Removal for Failure Analysis Not following the above requirements may cause moisture/ reflow damage that could hinder or completely prevent the determination of the original failure mechanism. Baking of Populated Boards Some SMD packages and board materials are not able to withstand long duration bakes at 125° C. Examples of this are some FR-4 materials, which cannot withstand a 24 hr bake at 125° C. Batteries and electrolytic capaci - tors are also temperature sensitive. With component and board temperature restrictions in mind, choose a bake temperature from Table 4-1 in J-STD 033; then determine the appropriate bake duration based on the component to be removed. For additional considerations see IPC-7711 andIPC-7721. Derating due to Factory Environmental Conditions Factory floor life exposures for SMD packages removed from the dry bags will be a function of the ambient envi - ronmental conditions. A safe, yet conservative, handling approach is to expose the SMD packages only up to the maximum time limits for each moisture sensitivity level as shown in next table. This approach, however, does not work if the factory humidity or temperature is greater than the testing conditions of 30° C/60% RH. A solution for addressing this problem is to derate the exposure times based on the knowledge of moisture diffusion in the component package materials ref. JESD22-A120). Recommended equivalent total floor life exposures can be estimated for a range of humidities and temperatures based on the nominal plastic thickness for each device. Table on next page lists equivalent derated floor lives for humidities ranging from 20-90% RH for three tempera - ture, 20° C, 25° C, and 30° C. Table on next page is applicable to SMDs molded with novolac, biphenyl or multifunctional epoxy mold compounds. The following assumptions were used in cal- culating this table: 1. Activation Energy for diffusion = 0.35eV (smallest known value). 2. For ≤60% RH, use Diffusivity = 0.121exp (-0.35eV/kT) mm2/s (this used smallest known Diffusivity @ 30° C). 3. For >60% RH, use Diffusivity = 1.320exp (-0.35eV/kT) mm2/s (this used largest known Diffusivity @ 30° C).

For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved. AV02-2837EN - February 8, 2011 Recommended Equivalent Total Floor Life (days) @ 20° C, 25° C & 30° C , 35° C For ICs with Novolac, Biphenyl and Multifunctional Epoxies (Reflow at same temperature at which the component was classified) Maximum Percent Relative Humidity Maximum Percent Relative Humidity Package Type and Body Thickness Moisture Sensitivity Level 5% 10% 20% 30% 40% 50% 60% 70% 80% 90% Body Thickness ≥3.1 mm Including PQFPs >84 pin, PLCCs (square) All MQFPs or All BGAs ≥1 mm Level 2a ∞ 124 167 231 103 35° C 30° C 25° C 20° C Level 3 ∞ 35° C 30° C 25° C 20° C Level 4 ∞ 35° C 30° C 25° C 20° C Level 5 ∞ 35° C 30° C 25° C 20° C Level 5a ∞ 35° C 30° C 25° C 20° C Body 2.1 mm ≤ Thickness <3.1 mm including PLCCs (rectangular) 18-32 pin SOICs (wide body) SOICs ≥20 pins, PQFPs ≤80 pins Level 2a ∞ 148 35° C 30° C 25° C 20° C Level 3 ∞ 35° C 30° C 25° C 20° C Level 4 ∞ 35° C 30° C 25° C 20° C Level 5 ∞ 35° C 30° C 25° C 20° C Level 5a ∞ 0.5 0.5 0.5 0.5 35° C 30° C 25° C 20° C Body Thickness <2.1 mm including SOICs <18 pin All TQFPs, TSOPs or All BGAs <1 mm body thickness Level 2a ∞ 0.5 0.5 35° C 30° C 25° C 20° C Level 3 ∞ 0.5 0.5 35° C 30° C 25° C 20° C Level 4 ∞ 0.5 0.5 35° C 30° C 25° C 20° C Level 5 ∞ 0.5 0.5 35° C 30° C 25° C 20° C Level 5a ∞ 0.5 0.5 0.5 35° C 30° C 25° C 20° C