ACPL-074L-000E AVAGO | Alldatasheet

Document overview

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Technical content

Features

  • +3.3V and +5 V CMOS compatibility
  • 30 ns max. pulse width distortion
  • 40ns max. propagation delay (for 3.3V supply voltage)
  • 30 ns max. propagation delay skew
  • High speed: 15 MBd min
  • 10 kV/µs minimum common mode rejection
  • –40 to 105°C temperature range
  • Glitch-Free Power-Up Feature
  • Safety and regulatory approvals: - UL recognized: 3750 V rms for 1 min. per UL 1577 - CSA component acceptance Notice #5 - IEC/EN/DIN EN 60747-5-5 TRUTH TABLE LED VO, OUTPUT OFF H ON L A 0.1uF bypass capacitor must be connected between pins 5 and 8. NC ANODE CATHODE NC 4

1 VDD

Description

The ACPL-071L (single-channel) and ACPL-074L (dual- channel) are 15 MBd CMOS optocouplers in SOIC-8 pack - age. The optocouplers utilize the latest CMOS IC technol - ogy to achieve outstanding performance with very low power consumption. Basic building blocks of ACPL-071L and ACPL-074L are high speed LEDs and CMOS detector ICs. Each detector incorporates an integrated photodiode, a high speed transimpedance amplifier, and a voltage comparator with an output driver.

Applications

  • Digital field bus isolation:
  • CANBus, RS485, USB
  • Multiplexed data transmission
  • Computer peripheral interface
  • Microprocessor system interface
  • DC/DC converter Functional Diagram

Ordering Information

ACPL-071L/074L are UL Recognized with 3750 Vrms for 1 minute per UL1577. Part number Option Package Surface Mount Tape & Reel IEC/EN/DIN EN 60747-5-5 QuantityRoHS Compliant ACPL-071L -000E SO-8 X 100 per tube -500E X X 1500 per reel -060E X X 100 per tube -560E X X X 1500 per reel ACPL-074L -000E SO-8 X 100 per tube -500E X X 1500 per reel -060E X X 100 per tube -560E X X X 1500 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACPL-071L-500E to order product of Small Outline SO-8 package in Tape and Reel packaging in RoHS compliant. Example 2: ACPL-074L-000E to order product of Small Outline SO-8 package in tube packaging and RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Reflow Soldering Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used. Regulatory Information The ACPL-071L and ACPL-074L have been approved by the following organizations: UL Recognized under UL 1577, component recognition program, File E55361. CSA Approved under CSA Component Acceptance Notice #5, File CA88324. IEC/EN/DIN EN 60747-5-5

ACPL-071L and ACPL-074L (Small Outline S0-8 Package) XXXV YWW 8 7 6 5 4321 5.994 ± 0.203 (0.236 ± 0.008) 3.937 ± 0.127 (0.155 ± 0.005) 0.406 ± 0.076 (0.050) BSC 5.080 ± 0.127 (0.200 ± 0.005) 3.175 ± 0.127 (0.060) 45 X 0.432 (0.017) 0.228 ± 0.025 (0.009 ± 0.001) TYPE NUMBER (LAST 3 DIGITS) DATE CODE 0.305 (0.012) MIN. TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX. OPTION NUMBER 500 NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX. 0.203 ± 0.102 (0.008 ± 0.004) PIN ONE 0 ~ 7 7.49 (0.295) 1.9 (0.075) 0.64 (0.025) LAND PATTERN RECOMMENDATION

Insulation and Safety Related Specifications Parameter Symbol Value Units Conditions Minimum External Air Gap (Clearance) L(I01) 4.9 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (Creepage) L(I02) 4.8 mm Measured from input terminals to output terminals, shortest distance path along body. Minimum Internal Plastic Gap (Internal Clearance) 0.08 mm Insulation thickness between emitter and detector; also known as distance through insulation. Tracking Resistance (Comparative Tracking Index) CTI ≥175 Volts DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) All Avago Technologies data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. There are recom- mended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level.

IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* Description Symbol Option 060 Unit Installation classification per DIN VDE 0110, Table 1 for rated mains voltage ≤ 150 Vrms for rated mains voltage ≤ 300 Vrms for rated mains voltage ≤ 600 Vrms I – IV I – IV I – III Climatic Classification 40/85/21 Pollution Degree (DIN VDE 0110/39) 2 Maximum Working Insulation Voltage VIORM 567 Vpeak Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC VPR 1063 Vpeak Input to Output Test Voltage, Method a* VIORM x 1.6 = VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC VPR 907 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 6000 Vpeak Safety-limiting values – maximum values allowed in the event of a failure. Case Temperature Input Current Output Power TS IS, INPUT PS, OUTPUT 150 150 600 mA mW Insulation Resistance at TS, VIO = 500 V RS ≥109 Ω Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature TS –55 +125 °C Ambient Operating Temperature TA –40 +105 °C Supply Voltages VDD 0 6.0 Volts Output Voltage VO –0.5 VDD +0.5 Volts Average Forward Input Current IF - 20.0 mA Average Output Current Io - 10.0 mA Input Power Dissipation PI 35 mW Output Power Dissipation PO 100 mW Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane Solder Reflow Temperature Profile See Reflow Soldering Profile Recommended Operating Conditions Parameter Symbol Min. Max. Units Ambient Operating Temperature TA –40 +105 °C Supply Voltages VDD 4.5 5.5 V 3.0 3.6 V Input Current (ON) IF 9 18 mA Supply Voltage Slew Rate[1] SR 0.5 500 V/ms

All typical specifications are at TA=+25°C, VDD= +3.3V. Parameter Symbol Part Number Min. Typ. Max. Units Test Conditions Input Forward Voltage VF 1.3 1.5 1.8 V IF = 14mA Input Reverse Breakdown Voltage BVR 5.0 V IR = 10 µA Logic High Output Voltage VOH VDD-1 VDD-0.3 V IF = 0, IO = -4 mA, VDD=3.3V VDD-1 VDD-0.2 V IF = 0, IO = -4 mA, VDD=5V Logic Low Output Voltage VOL 0.35 0.8 V IF = 14mA, IO =4mA, VDD=3.3V 0.2 0.8 V IF = 14mA, IO = 4mA, VDD=5V Input Threshold Current ITH 4.5 8.8 mA IOL = 20 µA Logic Low Output Supply Current IDDL ACPL-071L 4.1 6.0 mA IF = 14 mA ACPL-074L 8.3 12.0 mA IF = 14 mA Logic Low Output Supply Current IDDH ACPL-071L 3.8 6.0 mA IF = 0 ACPL-074L 7.6 12.0 mA IF = 0 Switching Specifications All typical specifications are at TA=+25°C, VDD = +3.3V. Parameter Symbol Min. Typ. Max. Units Test Conditions Propagation Delay Time to Logic Low Output[2] tPHL 29 40 ns IF = 14mA, CL= 15pF, VDD=3.3V CMOS Signal Levels 50 ns IF = 14mA, CL= 15pF, VDD=5V CMOS Signal Levels Propagation Delay Time to Logic High Output[2] tPLH 22 40 ns IF = 14mA, CL= 15pF, VDD=3.3V, CMOS Signal Levels 50 ns IF = 14mA, CL= 15pF, VDD=5V, CMOS Signal Levels Pulse Width tPW 66.7 ns Pulse Width Distortion[3] |PWD | 0 7 25 ns IF = 14mA, CL= 15pF, VDD=3.3V, CMOS Signal Levels 30 ns IF = 14mA, CL= 15pF, VDD=5V, CMOS Signal Levels Propagation Delay Skew[4] tPSK 30 ns IF = 14mA, CL= 15pF CMOS Signal Levels Output Rise Time (10% – 90%) tR 20 ns IF = 14mA, CL= 15pF CMOS Signal Levels Output Fall Time (90% - 10%) tF 25 ns IF = 14mA, CL= 15pF CMOS Signal Levels Common Mode Transient Immunity at Logic High Output[5] | CMH | 10 15 kV/µs VCM = 1000 V, TA = 25°C, IF = 0 mA Common Mode Transient Immunity at Logic Low Output[6] | CML | 10 15 kV/µs VCM = 1000 V, TA = 25°C, IF = 14 mA

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved.

0 V SWITCH AT A: I = 0 mAF

Figure 13. Test circuit for common mode transient immunity and typical waveforms. Rtotal is the total resistance of the driver output impedence (which is assumed to be 50 Ω) and the limiting resistor (Rtotal=Rdrv+Rlimit) .