ACNW261L-500E

ACNW261L-500E AVAGO | Alldatasheet

Document overview

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• PDF pages: 17

Technical content

Features

• Ultra low current IDD consumption: 1.5 mA max
• Low input current capability: 1.6 mA min (ACPL-061L), 3 mA min (ACPL-C61L), 4 mA min (ACNW261L)
• Available packages: SO-8, Stretched SO-8 and 400 mil widebody
• Built-in slew-rate controlled output
• Tri-state output with enable pin VE
• Glitch free power-up and power-down
• 20 kV/μs minimum Common Mode Rejection (CMR) at VCM = 1000 V
• High Speed: 10 MBd min
• Guaranteed AC and DC performance over wide temperature: -40° C to +105° C
• Safety and Regulatory Approval – UL 1577 recognized – 3750 Vrms for 1 minute for ACPL-061L and 5000 Vrms for 1 minute for ACPL-C61L/ACNW261L – CSA Approval – IEC/EN/DIN EN 60747-5-5 Approval for Reinforced Insulation

Applications

• Communication Interface: RS485, CANBus, I2C
• Microprocessor System Interfaces
• Digital isolation for A/D, D/A conversion

Description

The ACPL-061L/ACPL-C61L/ACNW261L is an optically coupled optocoupler that combines an AlGaAs light emitting diode and an integrated high gain photo detector addresses the low power need. The optocoupler consumes extremely low power, at maximum 1.5 mA I DD per channel across temperature. The forward current is as low as 1.6 mA to 4 mA and allows direct current drive by most microprocessors. These optocouplers support both 3.3 V and 5 V supply voltage with guaranteed AC and DC operational parame - ters from temperature range -40° C to +105° C. The output of the detector IC is a CMOS output. An enable input allows the detector output to be strobed. The internal Faraday shield provides a guaranteed common mode transient immunity specification of 20 kV/μs. The CMOS output is slew-rate controlled and is designed to allow the rise time and fall time to be controlled over a wide range of the load capacitance. This unique design provides maximum AC and DC circuit isolation while achieving TTL/CMOS compatibility. These optocouplers are suitable for high speed logic interfacing, while consuming extremely low power. Functional Diagram Anode VDD GND VO Shield 1NC NC 4 7 VE Cathode

Ordering Information

ACPL-061L is UL Recognized with 3750 V rms for 1 minute per UL1577. ACPL-C61L and ACNW261L are UL Recognized with 5000 Vrms for 1 minute per UL1577. Part number Option Package Surface Mount Gull Wing Tape & Reel UL 1577

5000 Vrms /

1 Minute rating

60747-5-5 Quantity(RoHS Compliant) ACPL-061L -000E SO-8 X 100 per tube -060E X X 100 per tube -500E X X 1500 per reel -560E X X X 1500 per reel ACPL-C61L -000E Stretched SO-8 X X 80 per tube -060E X X X 80 per tube -500E X X X 1000 per reel -560E X X X X 1000 per reel ACNW261L -000E 400 mil DIP-8 X X 42 per tube -300E X X X X 42 per tube -500E X X X X X 750 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACPL-061L-560E to order product of Small Outline SO-8 package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval in RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.

ACPL-C61L Stretched SO-8 Package 5.850 ± 0.254 (0.230 ± 0.010) 5678 4321 Dimensions in millimeters (inches) Notes: Lead coplanarity = 0.1 mm (0.004 inches) Floating lead protrusion is 0.25mm (10mils) max 6.807 ± 0.127 (0.268 ± 0.005) RECOMMENDED LAND PATTERN 12.650 (0.498) 1.905 (0.075) 3.180 ± 0.127 (0.125 ± 0.005) 0.381 ± 0.130 (0.015 ± 0.005) 1.270 (0.050) BSG 0.254 ± 0.100 (0.010 ± 0.004) 0.750 ± 0.250 (0.0295 ± 0.010) 11.50 ± 0.250 (0.453 ± 0.010) 1.590 ± 0.127 (0.063 ± 0.005) (0.018) 0.450 45° RoHS-COMPLIANCE INDICATOR PART NUMBER DATE CODE C61L YWW 0.64 (0.025) 0.200 ± 0.100 (0.008 ± 0.004) XXXV YWW 8 7 6 5 4321 5.994 ± 0.203 (0.236 ± 0.008) 3.937 ± 0.127 (0.155 ± 0.005) 0.406 ± 0.076 (0.050) BSC 5.080 ± 0.127 (0.200 ± 0.005) 3.175 ± 0.127 (0.060) 45° X 0.432 (0.017) 0.228 ± 0.025 (0.009 ± 0.001) PART NUMBER (LAST 3 DIGITS) DATE CODE 0.305 (0.012) MIN. 0.203 ± 0.102 (0.008 ± 0.004) PIN ONE 0 ~ 7° Total package length (inclusive of mold /f_lash) Dimensions in Millimeters (Inches) Notes: Lead coplanarity = 0.10 mm (0.004 inches) max. Floating lead protrusion is 0.15 mm (6 mils) max. Option number 500 not marked 7.49 (0.295) 1.9 (0.075) 0.64 (0.025) LAND PATTERN RECOMMENDATION

ACNW261L 8-Pin Widebody DIP Package ACNW261L 8-Pin Widebody DIP Package with Gull Wing Surface Mount Option 300E A ACNWXXX YYWWX DATE CODE TYPE NUMBER Dimensions in millimeters (inches) Note: Floating lead protrusion is 0.25 mm (10 mils) max. 321 4 7° TYP. 8 5 11.15 ± 0.15 (0.442 ± 0.006) 9.00 ± 0.15 (0.354 ± 0.006) +0.0760.254 - 0.0051 +0.003)(0.010 - 0.002) MAX.11.00 (0.433) MAX.1.55 (0.061) MAX.5.10 (0.201) MIN.0.51 (0.021) TYP.10.16 (0.400) TYP.2.54 (0.100) 3.10 (0.122) 3.90 (0.154) 0.40 (0.016) 0.56 (0.022) 1.78 ± 0.15 (0.070 ± 0.006) 7° NOM. LAND PATTERN RECOMMENDATION 8 5 1 4 Dimensions in millimeters (inches) 11.15 ± 0.15 (0.442 ± 0.006) 9.00 ± 0.15 (0.354 ± 0.006) 13.56 (0.534) 1.3 (0.051) 2.29 (0.09) MAX.1.55 (0.061) MAX.4.00 (0.158) MAX.11.00 (0.433) BSC2.54 (0.100) 1.78 ± 0.15 (0.070 ± 0.006) 12.30 ± 0.30 (0.484 ± 0.012) 0.75 ± 0.25 (0.030 ± 0.010) +0.0760.254 - 0.0051 +0.003)(0.010 - 0.002) 1.00 ± 0.15 (0.039 ± 0.006) Notes: Lead coplanarity = 0.10 mm (0.004 inches) Floating lead protrusion is 0.25 mm (10 mils) max.

Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used. Regulatory Information The ACPL-061L, ACPL-C61L, ACNW261L and are pending approval by the following organizations: IEC/EN/DIN EN 60747-5-5 (Option 060E only) UL Approval under UL 1577, component recognition program up to VISO = 3750 VRMS for ACPL-061L and VISO = 5000 VRMS for ACPL-C61L/ACNW261L File E55361. CSA Approval under CSA Component Acceptance Notice #5, File CA 88324. Insulation and Safety Related Specifications Parameter Symbol ACPL-061L ACPL-C61L ACNW261L Unit Conditions Minimum External Air Gap (External Clearance) L(101) 4.9 8 9.6 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (External Creepage) L(102) 4.8 8 10 mm Measured from input terminals to output terminals, shortest distance path along body. Minimum Internal Plastic Gap (Internal Clearance) 0.08 0.5 1.0 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. Tracking Resistance (Comparative Tracking Index) CTI 175 175 175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa IIIa IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* (Option 060) Description Symbol Characteristic UnitACPL-061L ACPL-C61L ACNW261L Installation classification per DIN VDE 0110/39, Table 1 for rated mains voltage ≤ 150 Vrms for rated mains voltage ≤ 300 Vrms for rated mains voltage ≤ 600 Vrms for rated mains voltage ≤ 1000 Vrms I – IV I – III I – II I – IV I – IV I – IV I – III I – IV I – IV I – IV I – III Climatic Classification 55/105/21 55/105/21 55/105/21 Pollution Degree (DIN VDE 0110/39) 2 2 2 Maximum Working Insulation Voltage VIORM 567 1414 1414 Vpeak Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial discharge < 5 pC VPR 1063 2651 2651 Vpeak Input to Output Test Voltage, Method a* VIORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec, Partial discharge < 5 pC VPR 907 2262 2262 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 6000 8000 8000 Vpeak Safety-limiting values – maximum values allowed in the event of a failure. Case Temperature Input Current Output Power TS IS, INPUT PS, OUTPUT 150 150 600 175 230 600 150 400 700 mA mW Insulation Resistance at TS, VIO = 500 V RS >109 >109 >109 W * Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/ DIN EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test profiles. ** Refer to the following figure for dependence of PS and IS on ambient temperature. TS – CASE TEMPERATURE – °C 400 600 200 100 300 500 700 PS (mW) IS (mA) Surface Mount SO-8 Product 200 400 600 800 1000 0 25 50 75 100 125 150 175 TS – CASE TEMPERATURE – °C PS (mW) IS (mA) POWER OUTPUT – P S, INPUT CURRENT – I S Surface Mount SSO-8 Product 400 600 800 200 100 300 500 700 PS (mW) IS (mA) Widebody 400mil DIP-8 Product 1000 900 POWER OUTPUT – P S, INPUT CURRENT – I S POWER OUTPUT – P S, INPUT CURRENT – I S 0 25 50 75 100 125 150 175 0 25 50 75 100 125 150 175200 TS – CASE TEMPERATURE – °C

Parameter Symbol Min. Max. Units Note Storage Temperature TS -55 125 °C Operating Ambient Temperature TA -40 105 °C Reversed Input Voltage VR 5 V Supply Voltage VDD 6.5 V Average Forward Input Current IF – 8 mA Peak Transient Input Current IF(TRAN) – 1 A < 1 μs Pulse Width, < 300 pulses per second 80 mA < 1 μs Pulse Width, <10% Duty Cycle Output Current IO 10 mA Output Voltage VO -0.5 VDD + 0.5 V Input Power Dissipation PI 14 mW per channel Output Power Dissipation PO 20 mW per channel Lead Solder Temperature TLS 260°C for 10 sec., 1.6 mm below seating plane Solder Reflow Temperature Profile Refer to Solder Reflow Profile section Recommended Operating Conditions Parameter Symbol Part Number Min Max Units Operating Temperature TA -40 105 °C Input Current, Low Level IFL 0 250 μA Input Current, High Level IFH ACPL-061L 1.6 6 mA ACPL-C61L 3 8 mA ACNW261L 4 8 mA Power Supply Voltage VDD 2.7 5.5 V Forward Input Voltage VF (OFF) 0.8 V

Electrical Specifications (DC) Over recommended temperature (TA = -40° C to 105° C) and supply voltage (2.7 V ≤ VDD ≤ 5.5 V). All typical specifications are at VDD = 5 V, TA = 25° C. Parameter Symbol Part Number Min Typ Max Units Test Conditions Input Forward Voltage VF ACPL-061L 0.95 1.3 1.7 V IF = 2 mA, Figure 1a, 2a ACPL-C61L 1.2 1.5 1.9 V IF = 5 mA, Figure 1b, 2b ACNW261L 1.2 1.5 1.9 V IF = 5 mA, Figure 1b, 2b Input Reverse Breakdown Voltage BVR ACPL-061L 3 5 V IR = 10 μA ACPL-C61L 7 10 V IR = 10 μA ACNW261L 7 10 V IR = 10 μA Logic High Output Voltage VOH VDD - 0.1 VDD V IF = 0 mA, VI = 0 V, IO = -20 μA VDD - 1.0 VDD V IF = 0 mA, VI = 0 V, IO = -3.2mA Logic Low Output Voltage VOL 0.03 0.1 V IF = 2 mA, VI = 5 V/3.3 V, IO = 20 μA 0.18 0.4 V IF = 2 mA, VI = 5 V/3.3 V, IO = 3.2 mA Input Threshold Current ITH ACPL-061L 0.7 1.3 mA Figure 3a ACPL-C61L 1.5 2.2 mA Figure 3b ACNW261L 1.5 3 mA Figure 3b Logic Low Output Supply Current IDDL 0.8 1.5 mA Figure 4 Logic High Output Supply Current IDDH 0.8 1.5 mA Figure 5 Input Capacitance CIN 60 pF f = 1 MHz, VF = 0 V High Level Enable Current IEH -0.7 -1.6 mA VDD = 5.5 V, VE = 3.0 V Low Level Enable Current [4] IEL -0.9 -1.6 mA VDD = 5.5 V, VE = 0.5 V High Level Enable Voltage [10] VEH 0.7 x VDD V 3.0 V ≤ VDD ≤ 5.5 V Low Level Enable Voltage [10] VEL 0.3 x VDD V 3.0 V ≤ VDD ≤ 5.5 V Input Diode Temperature Coefficient ΔVF/ΔTA ACPL-061L -1.6 mV/°C IF = 2 mA ACPL-C61L -1.9 mV/°C IF = 3 mA ACNW261L -1.9 mV/°C IF = 5 mA

delay, either t PLH or t PHL. As mentioned earlier, t PSK can determine the maximum parallel data transmission rate. Figure 10 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocou - plers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 10 shows that there will be uncer - tainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t PSK. A cautious design should use a slightly longer pulse width to ensure that any additional un- certainty in the rest of the circuit does not cause a problem. The t PSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulse- width distortion and propagation delay skew over the recommended temperature, and power supply ranges. Optocoupler CMR performance The principal protection against common mode noise comes down to the fundamental isolation properties of the optocoupler, this in turn is directly related to the input- output leakage capacitance of the optocoupler. To provide maximum protection to circuitry connected to the input or output of the optocoupler the leakage capac- itance is minimized by having large separation distances at all points in the optocoupler construction, including the LED/photodiode interface. In addition to the constructional design, additional circuit design steps are taking to further mitigate the effects of common mode noise. The most important of these is the use of a Faraday shield on the photodetector stage. This faraday shield is effective in optocouplers because the internal modulation frequency (light) is many orders of magnitude higher than the common mode noise frequency. Application level CMR Performance In application, it desirable that the optocoupler’s common mode isolation perform as close as possible to that indicated in the data sheets specifications. The first step in meeting this goal is to ensure maintain - ing maximum separation between PCB interconnects on either side of the optocoupler and avoid routing tracks beneath the optocoupler. Nonetheless, it is inevitable that a certain amount of CMR noise will be coupled into the inputs which can potentially result in false-triggering of the input. This problem is frequently observed in devices with input high input impedence such as CMOS buffered inputs in either optocoupler or alternate isolator technologies. In some cases, this not only causes momentary missing pulses but in some technologies may even cause input circuitry to latch-up. ACPL-061L/ACPL-C61L/ACNW261L optocoupler family does not face input latch up issue even at very high CMR levels, such as those experienced in end equipment level tests (for example IEC61004-4-4) due to the simple diode structure of the LED. In some cases achieving the rated data sheet CMR perfor- mance levels is not possible in the intended application, often because of the practical need to actually connect the isolator input to the output of a dynamically changing signal rather than tying the input statically to VDD1 or GND1. This specsmanship issue is often observable with alterna - tive isolators utilizing AC encoding techniques. To address this requirement for clear transparency on the achievable end application performance, the ACPL-061L/ ACPL-C61L/ACNW261L series of optocouplers includes an additional typical performance indication of the dynamic CMR in the electrical parameter table. What this informa - tion indicates is the achievable CMR performance whilst the input is being toggled on or off during the occurrence of a CMR transient. The logic output of the optocoupler is mainly controlled by the level of the LED current due to the short transition rise/fall time of the LED current (approximately 10ns), the dynamic noise immunity is essentially the same as the static noise immunity. To achieve this goal of meeting the maximum inherent CMR capabilities of the ACPL-061L/ACPL-C61L/ACNW261L family, some simple consideration needs to be given to the operation of the LED at the application level. In particular ensuring that the LED stays either on or off during a CMR transient. Some common design techniques which are sometimes used to meet this goal: Keeping LED On: i) Overdrive the LED with a higher than required forward current. Keeping LED Off: i) Reverse bias the LED during the off state. ii) Minimize the off state impedance across the anode and cathode of the LED during the off state. All these methods are fully capability of enabling the full CMR capabilities off the ACPL-061L/ACPL-C61L/ ACNW261L family to be achieved. But they do come at the cost of practical implementation issues or a compromise on power consumption. An effective method to meet the goal of maintaining the LED status during a CMR event with no other design compromises other the addition of a single low cost component (resistor).

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2014 Avago Technologies. All rights reserved. Table 1. Effects of Common Mode Pulse Direction on Transient ILED can lead to false data in the optocoupler application. during power-up and power-down. communication line will have different load capacitances. and fall time remain stable across wide load capacitance. Figure 14. VDD Ramp when LED is off. Figure 15. VDD Ramp when LED is on.