ACNV2601 AVAGO | Alldatasheet
Document overview
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- PDF pages: 11
Technical content
Features
- High Voltage Insulation with minimum 13 mm creepage and clearance
- 20 kV/μs Minimum Common Mode Rejection (CMR) at VCM = 1500 V
- High Speed: 10 MBd Typical
- TTL Compatible
- Open Collector Output
- Guaranteed AC and DC performance over wide temperature: -40 °C to +105 °C
- Available in 10-pin widebody packages
- Safety Approval to be submitted for approval – Approval at 7500Vrms for 1 minute per UL1577 – CSA – IEC/EN/DIN EN 60747-5-5 with Viorm =2262Vpeak
Applications
- High voltage insulation
- Instrument input/output isolation
- Line receivers
- Ground loop elimination
- Isolation of high speed logic systems
- Microprocessor system interfaces A 0.1 μF bypass capacitor must be connected between pins VCC and GND. Truth Table (Positive Logic) LED ENABLE OUTPUT On H L Off H H On L H Off L H On NC L Off NC H
Ordering Information
ACNV2601 is UL recognized with 7500 Vrms for 1 minute per UL1577. Part number Option Package Surface Mount Gull Wing Tape & Reel UL 7500 Vrms/
1 Minute rating
60747-5-5 QuantityRoHS Compliant ACNV2601 -000E 500 mil DIP-10 X X 35 per tube -300E X X X X 35 per tube -500E X X X X X 500 per reel To order, choose a part number from the Part number column and combine with the desired option from the Option column to form an order entry. Example 1: ACNV2601-500E to order product of 500mil DIP-10 Widebody with Gull Wing Surface Mount package in Tape and Reel packaging with both UL 7500 Vrms/1min and IEC/EN/DIN EN 60747-5-5 Safety Approval in RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Schematic Use of a 0.1μF bypass capacitor connected between pins of 7 and 10 is recommended (see note 5) SHIELD VF IF ICC VCC VO GND IO VE IE 9
10-Pin Widebody (500mils) DIP Package 10-Pin Widebody (500mils) DIP Package with Gull Wing Surface Mount Option 300 Dimensions in Inches [Millimeters] [13.71 ± 0.15] 0.540 ± 0.006 [11.01 ± 0.15] 0.433 ± 0.006 [13.01 ± 0.15] 0.512 ± 0.006 [11.01 ± 0.15] 0.433 ± 0.006 [1.998] 0.08 [5.25] 0.21 [13.06] 0.514 +0.08 -0.05 +0.003 -0.002 [0.25 ] 0.0105° TYP [1.30] 0.05 TYP [5.25] 0.207 [1.78 ± 0.15] 0.10 TYP [0.51]
0.020 MIN
[0.48 ± 0.08] 0.019 ± 0.003 [3.10] 0.122 [3.90] 0.154 Dimension in Inches [Millimeter] LAND PATTERN RECOMMENDATION [13.71 ± 0.15] 0.540 ± 0.006 [11.01 ± 0.15] 0.433 ± 0.006 [16.35 ± 0.15] 0.644 ± 0.006 [1.78 ± 0.15] 0.070 ± 0.006 [0.75 ± 0.15] 0.030 ± 0.006 [1.00 ± 0.15] 0.039 ± 0.006 [14.90 ± 0.15] 0.587 ± 0.006 [13.01 ± 0.15] 0.512 ± 0.006 [2.29 ± 0.15] 0.090 ± 0.006 [1.30 ± 0.15] 0.051 ± 0.006 [2.29 ± 0.15] 0.090 ± 0.006 [1.30] 0.051 TYP MAX[5.25] 0.207 5° NOM +0.076 -0.051 +0.003 -0.002 [0.254 ] 0.010
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used. Insulation and Safety Related Specifications Parameter Symbol ACNV2601 Units Conditions Minimum External Air Gap (External Clearance) L(101) 13 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (External Creepage) L(102) 13 mm Measured from input terminals to output terminals, shortest distance path along body. Minimum Internal Plastic Gap (Internal Clearance) 2.0 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. Minimum Internal Tracking (Internal Creepage) 4.6 mm Measured from input terminals to output terminals, along internal cavity. Tracking Resistance (Comparative Tracking Index) CTI 200 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* Description Symbol Characteristic Unit Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 600 Vrms for rated mains voltage ≤ 1000 Vrms I – IV I – III Climatic Classification 55/105/21 Pollution Degree (DIN VDE 0110/1.89) 2 Maximum Working Insulation Voltage VIORM 2262 Vpeak Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial discharge < 5 pC VPR 4241 Vpeak Input to Output Test Voltage, Method a* VIORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec, Partial discharge < 5 pC VPR 3619 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 12000 Vpeak Safety-limiting values – maximum values allowed in the event of a failure. Case Temperature Input Current Output Power TS IS, INPUT PS, OUTPUT 150 400 mA W Insulation Resistance at TS, VIO = 500 V RS >109 Ω * Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/ DIN EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test profiles. ** Refer to the following figure for dependence of PS and IS on ambient temperature.
Parameter Symbol Min. Max. Units Storage Temperature TS -55 125 °C Operating Temperature TA -40 105 °C Average Input Current IF(AVG) 20 mA Reverse Input Voltage VR 3 V Input Power Dissipation PI 40 mW Supply Voltage (1 Minute Maximum) VCC 7 V Enable Input Voltage (Not to Exceed VCC by more than 500mV) VE VCC+0.5 V Enable Input Current IE 5 mA Output Collector Current IO 50 mA Output Collector Voltage VO 7 V Output Collector Power Dissipation PO 85 mW Lead Solder Temperature TLS 245°C for 10 sec, up to seat plane Recommended Operating Conditions Parameter Symbol Min. Max. Units Note Input Current, Low Level IFL* 0 250 μA Input Current, High Level IFH** 9 16 mA 1 Power Supply Voltage VCC 4.5 5.5 V Low Level Enable Voltage VEL 0 0.8 V High Level Enable Voltage VEH 2.0 VCC V Operating Temperature TA - 40 105 °C Fan Out (at RL = 1k Ω) N 5 TTL Loads Output Pull-up Resistor RL 330 4k Ω * The off condition can also be guaranteed by ensuring that VFL ≤0.8volts. ** The initial switching threshold is 8mA or less. It is recommended that 9mA to 16mA be used for best performance and to permit at least a 20% LED degradation guardband.
Electrical Specifications (DC) Over recommended operating conditions unless otherwise specified. All typicals at VCC = 5 V, TA = 25°C. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note High Level Output Current IOH 5.5 100 μA VCC = 5.5 V, VE = 2.0 V VO = 5.5 V, IFL = 250 μA Input Threshold Current ITH 3.5 8 mA VCC = 5.5 V, VE = 2.0 V, VO = 0.6 V, IOL > 13 mA 1, 2 12 Low Level Output Voltage VOL 0.35 0.6 V VCC = 5.5 V, VE = 2.0 V, IF = 8 mA, IOL(Sinking) = 13 mA 1, 2, 3, 4 High Level Supply Current ICCH 7.0 12 mA VE = 0.5V VCC = 5.5 V, IF = 0 mA 6.5 VE = VCC Low Level Supply Current ICCL 9.0 13 mA VE = 0.5V VCC = 5.5 V, IF = 10 mA 8.5 VE = VCC High Level Enable Current IEH -0.7 mA VCC = 5.5 V, VE = 2.0 V Low Level Enable Current IEL -0.9 mA VCC = 5.5 V, VE = 0.5 V High Level Enable Voltage VEH 2.0 mA VCC = 5.5 V, VE = 2.0 V 12 Low Level Enable Voltage VEL 0.8 mA VCC = 5.5 V, VE = 0.5 V Input Forward Voltage VF 1.25 1.64 1.85 V TA = 25 °C IF = 10 mA 5 1.2 2.05 Input Reverse Breakdown Voltage BVR 5 V IR = 100 μA, TA = 25 °C Input Capacitance CIN 60 pF f = 1 MHz, VF = 0 V Input Diode Temperature Coefficient ΔVF/ΔTA -1.9 mV/°C IF = 10 mA
Switching Specifications (AC) Over recommended temperature (TA = -40°C to 105°C), VCC = 5 V, IF = 10mA unless otherwise specified. All typicals are at TA = 25°C, VCC = 5V. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay Time to High Output Level tPLH 30 50 80 ns TA = 25 °C RL = 350 Ω, CL = 15 pF 6, 7, 8 3, 12 120 Propagation Delay Time to Low Output Level tPHL 35 55 80 ns TA = 25 °C 4,12 120 Pulse Width Distortion |tPHL - tPLH| 5 40 ns RL = 350 Ω, CL = 15 pF 6, 7, 8, 9 6, 12 Propagation Delay Skew tpsk 50 ns 5, 6, Output Rise Time (10%-90%) Tr 25 ns 10 12 Output Fall Time (10%-90%) Tf 10 ns 10 12 Propagation Delay Time of Enable from VEH to VEL tELH 30 ns RL = 350 Ω, CL = 15 pF, VEL = 0 V, VEH = 3V 11, 12 7 Propagation Delay Time of Enable from VEL to VEH tEHL 20 ns RL = 350 Ω, CL = 15 pF, VEL = 0 V, VEH = 3V 11, 12 8 Output High Level Common Mode Transient Immunity |CMH| 20 25 kV/μs VCC = 5 V, IF = 0 mA, VO(MIN) = 2 V, RL = 350 Ω, TA = 25 °C, VCM = 1500 V 13 9, 11, Output Low Level Common Mode Transient Immunity |CML| 20 25 kV/μs VCC = 5 V, IF = 10 mA, VO(MAX) = 0.8 V, RL = 350 Ω, TA = 25 °C, VCM = 1500 V 10, 11, All typicals at TA = 25°C. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Input-Output Insulation VISO 7500 Vrms RH < 50% for 1 min. TA = 25°C 13, 14 Input-Output Resistance RI-O 1012 Ω VI-O = 500 V 13 Input-Output Capacitance CI-O 0.5 0.6 pF f = 1 MHz, TA = 25°C 13 Notes: 1. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 20mA. 2. By passing of power supply line is required, with a 0.1 μF ceramic disc capacitor adjacent to each optocoupler as illustrated in Figure 15. Total lead length between both ends of the capacitor and the isolator pins should ot exceed 20 mm. 3. The tPLH propagation delay is measured from the 5 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of the output pulse. 4. The tPHL propagation delay is measured from the 5 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the output pulse. 5. tPSK is equal to the worst case difference in t PHL and/or t PLH that will be seen between units at any given temperature and specified test conditions. 6. See application section titled “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information. 7. The tELH enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the rising edge of the output pulse. 8. The tEHL enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the falling edge of the output pulse. 11. For sinusoidal voltages, (|dVCM | / dt)max = πfCMVCM(p-p). 12. No external pull up is required for a high logic state on the enable input. If the V E pin is not used, tying V E to V CC will result in improved CM R performance. 13. Device considered a two-terminal device: pins 1, 2, 3, 4 and 5 shorted together, and pins 6, 7, 8, 9 and 10 shorted together. 14. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 9000 Vrms for one second (leakage detection current limit, I I-O ≤ 5 μA). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table, if applicable.
0 V SWITCH AT A: IF = 0 mA
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved. Figure 13. Test circuit for common mode transient immunity and typical waveforms Figure 14. Thermal derating curve, dependence of safety limiting value with Figure 15. Recommended printed circuit board layout