ACE24AC128EFMUH

ACE24AC128E ACE | Alldatasheet

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Technical content

Features

⚫ Low voltage and low power operations: ACE24AC128E: VCC = 1.8V to 5.5V ⚫ 64 bytes page write mode. ⚫ Partial page write operation allowed. ⚫ Internally organized: 16,384 × 8 (128K). ⚫ Standard 2-wire bi-directional serial interface. ⚫ Schmitt trigger, filtered inputs for noise protection. ⚫ Self-timed Write Cycle (5ms maximum). ⚫ 1 MHz (2.5V-5.5V), 400kHz (1.8V) Compatibility. ⚫ Automatic erase before write operation. ⚫ Write protect pin for hardware data protection. ⚫ High reliability: typically 1,000,000 cycles endurance. ⚫ 100 years data retention. ⚫ Industrial temperature range (-40℃to 85℃). ⚫ Standard 8-lead DIP/SOP/MSOP/TSSOP/USON3*2-8 Pb-free packages. Absolute Maximum Ratings Industrial operating temperature: -40℃ to 85℃ Storage temperature: -50℃ to 125℃ Input voltage on any pin relative to ground: -0.3V to VCC + 0.3V Maximum voltage: 8V ESD Protection on all pins: >4000V Notice: Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the device. Functional operation of the device at conditions beyond those listed in the specification is not guaranteed. Prolonged exposure to extreme conditions may affect device reliability or functionality.

VER 1.1 2 Packaging Type SOP-8 TSSOP -8 DIP-8 MSOP-8 USON3*2-8 Pin Configurations Pin Name Functions AO-A2 Device Address Inputs SDA Serial Data Input / Open Drain Output SCL Serial Clock Input WP Write Protect NC No-Connect

Ordering information

U: Tube T: Tape and Reel DP: DIP-8 FM: SOP-8 OM: MSOP-8 TM: TSSOP-8 UA8: USON3*2-8 Halogen-free

VER 1.1 3 Block Diagram Pin Descriptions (A) DEVICE / CHIP SELECT ADDRESSES (A2, A1, A0) These are the chip select input signals for the serial EEPROM devices. Typically, these signals are hardwired to either VIH or VIL. If left unconnected, they are internally recognized as VIL. (B) SERIAL CLOCK (SCL) The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of this clock is to clock data out of the EEPROM device. (C) SERIAL DATA LINE (SDA) SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can be wired-OR with other open-drain output devices. (D) WRITE PROTECT (WP) The ACE24AC128E devices have a WP pin to protect the whole EEPROM array from programming. Programming operations are allowed if WP pin is left un -connected or input to V IL. Conversely all programming functions are disabled if WP pin is connected to VIH or VCC. Read operations is not affected by the WP pin’s input level.

VER 1.1 4 Memory Organization The ACE24AC128E devices have 256 pages respectively. Since each page has 64 bytes, random word addressing to ACE24AC128E will require 14 bits data word addresses respectively. Device Operation (A) Serial Clock And Data Transitions The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when Serial clock SCL is at VIL. Any SDA signal transition may interpret as either a start or stop condition as described below. (B) Start Condition With SCL ≥ VIH, a SDA transition from high to low is interpreted as a start condition. All valid commands must begin with a start condition. (C) Stop Condition With SCL ≥ VIH, a SDA transition from low to high is interpreted as a stop condition. All valid read or write commands end with a stop condition. The device goes into the standby mode if it is after a read command. A stop condition after page or byte write command will trigger the chip into the standby mode after the self-timed internal programming finish (see Figure 1). (D) Acknowledge The 2 -wire protocol transmits address and data to and from the EEPROM in 8 bit words. The EEPROM acknowledges the data or address by outputting a "0" after rec eiving each word. The acknowledge signal occurs on the 9th serial clock after each word. (E) Standby Mode The EEPROM goes into low power standby mode after a fresh power up, after receiving a stop bit in read mode, or after completing a self-time internal programming operation. Figure 1: Timing diagram for start and stop conditions

VER 1.1 5 Figure 2: Timing diagram for output acknowledge Device Addressing The 2-wire serial bus protocol mandates an 8 bits device address word after a start bit condition to invoke a valid read or write command. The first four most significant bits of the device address must be 1010, which is common to all serial EEPROM devices. The next three bits are device address bits. These three device address bits (5 th, 6th and 7th) are to match with the external c hip select/address pin states. If a match is made, the EEPROM device outputs an acknowledge signal after the 8th read/write bit, otherwise the chip will go into standby mode. However, matching may not be needed for some or all device address bits (5th, 6thand 7th) as noted below. The last or 8th bit is a read/write command bit. If the 8th bit is at VIH then the chip goes into read mode. If a “0” is detected, the device enters programming mode. Write Operations (A) Byte Write A write operation requires two 8 -bit data word address following the device address word and acknowledge signal. Upon receipt of this address, the EEPROM will respond with a “0” and then clock in the first 8 -bit data word. Following receipt of the 8-bit data word, the EEPROM will again output a “0”. The addressing device, such as a microcontroller, mus t terminate the write sequence with a stop condition. At this time the EEPROM enters into an internally-timed write cycle state. All inputs are disabled during this write cycle and the EEPROM will not respond until the writing is completed (figure 3).

VER 1.1 6 (B) Page Write The 128K EEPROM are capable of 64-byte page write. A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. The microcontroller can transmit up to 63 more data words after the EEPROM acknowledges receipt of the first data word. The EEPROM will respond with a “0” after each data word is receive d. Th e microcontroller must terminate the page write sequence with a stop condition (see Figure 4). The lower five bits of the data word address are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. If more than 64 data words are transmitted to the EEPROM, the data word address will “roll over” and the previous data will be overwritten. (C) Acknowledge Polling Acknowledge polling may be used to poll th e pro gramming status during a self -timed internal programming. By issuing a valid read or write address command, the EEPROM will not acknowledge at the 9 th clock cycle if the device is still in the self -timed programming mode. However, if the programming completes and the chip has returned to the standby mode, the device will return a valid acknowledge signal at the 9th clock cycle. Read Operations The read command is similar to the write command except the 8th read/write bit in address word is set to “1”. The three read operation modes are described as follows: (A) Current Address Read The EEPROM internal address word counter maintains the last read or write address plus one if the power supply to the device has not been cut off. T o initiate a current address read operation, the micro- controller issues a start bit and a valid device address word with the read/write bit (8th) set to “1”. The EEPROM will response with an acknowledge signal on the 9th serial clock cycle. An 8 -bit data word will then be serially clocked out. The internal address word counter will then automatically increase by one. For current address read the micro-controller will not issue an acknowledge signal on the 18th clock cycle. The micro -controller issues a valid stop bit after the 8th clock cycle to terminate the read operation. The device then returns to standby mode (see Figure 5). (B) Sequential Read The sequential read is very similar to current address read. The micro -controller issues a start bit and a valid device address word with read/write bit (8th) set to “1”. The EEPROM will response with an acknowledge signal on the 9th serial clock cycle. An 8 -bit data word will then be serially clocked out. Meanwhile the internally address word counter will then automatically increase by one.

VER 1.1 9 Electrical Specifications (A) Power-Up Requirements During a power-up sequence, the VCC supplied to the device should monotonically rise from GND to the minimum VCC level, with a slew rate no faster than 0.05 V/μs and no slower then 0.1 V/ms. A decoupling cap should be connected to the VCC PAD which is no smaller than 10nF . (B) Device Reset To prevent inadvertent write operations or any other spurious events from occurring during a power- up sequence, this device includes a Power-on Reset (POR) circuit. Upon power-up, the device will not respond to any commands until the VCC level crosses the internal voltage threshold (VPOR) that brings the device out of Reset and into Standby mode. The system designer must ensure the instructions are not sent to the device until the VCC supply has reached a stable value greater than or equal to the minimum VCC level. Figure 9: Power on and Power down If an event o ccurs in the system where the VCC level supplied to the device drops below the maximum VPOR level specified, it is recommended that a full power cycle sequence be performed by first driving the VCC pin to GND, waiting at least the minimum t POFF time and then performing a new power-up sequence in compliance with the requirements defined in this section.

VER 1.1 10 AC Characteristics Symbol Parameter 1.8V 2.5V~5.0V Units Min Max Min Max fSCL Clock Frequency, SCL 400 1000 kHz TLOW Clock Pulse Width Low 1.3 0.6 µs THIGH Clock Pulse Width High 0.6 0.3 µs TI Noise Suppression Time(1) 100 50 ns TAA Clock Low to Data Out Valid 0.9 0.55 µs TBUF Time the bus must be free before a new transmission can Start(1) 1.3 0.5 µs THD.STA Start Hold Time 0.6 0.25 µs TSU.STA Start Setup Time 0.6 0.25 µs THD.DAT Data In Hold Time 0 0 µs TSU.DAT Data In Setup Time 100 100 ns TR Inputs Rise Time(1) 0.3 0.3 µs TF Inputs Fall Time(1) 300 100 ns TSU.STO Stop Setup Time 0.6 0.25 µs TDH Data Out Hold Time 50 50 ns tPWR,R Vcc slew rate at power up 0.1 50 0.1 50 V/ms tPUP Time required after VCC is stable before the device can accept commands 100 100 µs tPOFF Minimum time at Vcc=0V between power cycles 500 500 ms TWR Write Cycle Time (for 04B/16B) 5 5 ms Endurance(1) 25℃, Page Mode, 3.3V 1,000,000 Write Cycles Notes: 1. This Parameter is expected by characterization but are not fully screened by test. 2. AC Measurement conditions: RL (Connects to Vcc): 1.3KΩ Input Pulse Voltages: 0.3Vcc to 0.7VCC Input and output timing reference Voltages: 0.5VCC

VER 1.1 11 DC Characteristics Symbol Parameter Test Condition Min Typ Max Units VCC1 24AC128E supply VCC 1.8 5.5 V ICC Supply Read Current VCC@5.5V SCL=100 kHz 0.4 1.0 mA ICC Supply Write Current VCC@5.5V SCL=100 kHz 2.0 3.0 mA ISB1 Supply Current VCC@1.8V,VIN = VCC or VSS < 1.0 µA ISB2 Supply Current VCC@2.5V,VIN = VCC or VSS < 1.0 µA ISB3 Supply Current VCC@5.5V,VIN = VCC or VSS < 1.0 µA ILI Input Leakage Current VIN= VCC or VSS 3.0 µA ILO Output Leakage Current VIN= VCC or VSS 3.0 µA VIL Input Low Level -0.6 VCC*0.3 V VIH Input High Level VCC*0.7 VCC+0.5 V VOL2 Output Low Level VCC@3.0V, IOL= 2.1 mA 0.4 V VOL1 Output Low Level VCC@1.8V, IOL= 0.15 mA 0.4 V

VER 1.1 12 Packaging information SOP-8 Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 1.350 1.750 0.053 0.069 A1 0.100 0.250 0.004 0.010 A2 1.350 1.550 0.053 0.061 b 0.330 0.510 0.013 0.020 c 0.170 0.250 0.006 0.010 D 4.700 5.100 0.185 0.200 E 3.800 4.000 0.150 0.157 E1 5.800 6.200 0.228 0.244 e 1.270 (BSC) 0.050 (BSC) L 0.400 1.270 0.016 0.050 θ 0° 8° 0° 8°

VER 1.1 13 Packaging information TSSOP-8 Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max D 2.900 3.100 0.114 0.122 E 4.300 4.500 0.169 0.177 b 0.190 0.300 0.007 0.012 c 0.090 0.200 0.004 0.008 E1 6.250 6.550 0.246 0.258 A 1.100 0.043 A2 0.800 1.000 0.031 0.039 A1 0.020 0.150 0.001 0.006 e 0.65 (BSC) 0.026 (BSC) L 0.500 0.700 0.020 0.028 H 0.25 (TYP) 0.01 (TYP) θ 1° 7° 1° 7°

VER 1.1 14 Packaging information DIP-8 Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 3.710 4.310 0.146 0.170 A1 0.510 0.020 A2 3.200 3.600 0.126 0.142 B 0.380 0.570 0.015 0.022 B1 1.524（BSC） 0.060（BSC） C 0.204 0.360 0.008 0.014 D 9.000 9.400 0.354 0.370 E 6.200 6.600 0.244 0.260 E1 7.320 7.920 0.288 0.312 e 2.540 (BSC) 0.100（BSC） L 3.000 3.600 0.118 0.142 E2 8.400 9.000 0.331 0.354

VER 1.1 15 Packaging information MSOP-8 Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.820 1.100 0.320 0.043 A1 0.020 0.150 0.001 0.006 A2 0.750 0.950 0.030 0.037 b 0.250 0.380 0.010 0.015 c 0.090 0.230 0.004 0.009 D 2.900 3.100 0.114 0.122 e 0.65 (BSC) 0.026 (BSC) E 2.900 3.100 0.114 0.122 E1 4.750 5.050 0.187 0.199 L 0.400 0.800 0.016 0.031 θ 0° 6° 0° 6°

VER 1.1 16 Packaging information USON3*2-8 Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.450 0.550 0.017 0.021 A1 0.000 0.050 0.000 0.002 b 0.180 0.300 0.007 0.039 b1 0.160REF 0.006REF c 0.100 0.200 0.004 0.008 D 1.900 2.100 0.075 0.083 D2 1.400 1.600 0.055 0.062 e 0.500BSC 0.020BSC Nd 1.500BSC 0.059BSC E 2.900 3.100 0.114 0.122 E2 1.500 1.700 0.059 0.067 L 0.300 0.500 0.012 0.020 h 0.200 0.300 0.066 0.12

VER 1.1 17 Notes ACE does not assume any responsibility for use as critical components in life support devices or systems without the express written approval of the president and general counsel of ACE Technology Co., LTD. As sued herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and shoes failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ACE Technology Co., LTD. http://www.ace-ele.com/