ACD2202 ANADIGICS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 24

Technical content

CATV/TV/Video Downconverter with Dual Synthesizer Data Sheet - Rev 2.1 Figure 1: Downconverter Block Diagram

FEATURES

  • Integrated Downconverter
  • Integrated Dual Synthesizer
  • 256 QAM Compatibility
  • Single +5 V Power Supply Operation
  • Low Power Consumption: <0.6 W
  • Low Noise Figure: 8 dB
  • High Conversion Gain: 10 dB
  • Low Distortion: -53 dBc
  • Three-Wire Interface
  • Small Size
  • -40 °C to +85 °C

APPLICATIONS

  • Set Top Boxes
  • CATV Video Tuners
  • Digital TV Tuners
  • CATV Data Tuners
  • Cable Modems

28 Pin SSOP

The ACD2202 uses both GaAs and Si technology to provide the downconverter and dual synthesizer functions in a double conversion tuner gain block, local oscillator, balanced mixer and dual synthesizer. The specifications meet the requirements of CATV/TV/Video and Cable Modem Data applications. The ACD2202 is supplied in a 28 lead SSOP package and requires a single +5 V supply voltage. The IC is well suited for applications where small size, low cost, low auxiliary parts count and a no- compromise performance is important. It provides for cost reduction by lowering the component and packaged IC count and decreasing the amount of labor-intensive production alignment steps, while significantly improving performance and reliability. Figure 2: Dual Synthesizer Block Diagram RF2: 64/65 Prescaler

18 Bit RF2

15 Bit RF2

15 Bit RF1

18 Bit RF1

RF1: 64/65 Prescaler Oscillator

22 Bit

2 Data Sheet - Rev 2.1 ACD2202 Figure 3: Pinout RFIN+ VIF +I FOUT+ VSS OSCGND EN DATA T CKT ISET CLK GND REFIN REFOUT VSS VSS GND VSS GND RFD OSCOUT CPD VSUP CPU GND RFU VSYN RFIN- OSCGND VIF +I FOUT-

Data Sheet - Rev 2.1 ACD2202 Table 1: Pin Description NIP EMAN NOITPIRCSED NIP EMAN NOITPIRCSED 1F R +NI retrevnocnwoD tupnIFRlaitnereffiD 82V FI FI+ +TUO retrevnocnwoD tuptuOFIlaitnereffiD otdelpuocylevitcudnI V+ DD 2F R -NI retrevnocnwoD tupnIFRlaitnereffiD 72V FI FI+ TUO- retrevnocnwoD tuptuOFIlaitnereffiD otdelpuocylevitcudnI V+ DD 3D NG dnuorGretrevnocnwoD )detcennocebtsuM( 62D NG dnuorGretrevnocnwoD )detcennocebtsuM( 4I TES trebliGretrevnocnwoD ecruoStnerruClleC rotsiseR 52V PUS esahPdnarotallicsO V+(ylppuSrettilpS DD ) 5T TKC troPtupnIrotallicsO )noitcennoctiucricknaT( 42C SO TUO tuptuOrotallicsO otdetcennoC( )tupnIFRrezisehtnyS 6C SO DNG tiucriCknaTrotallicsO ebottoN(dnuorG rehtoynaotdetcennoc )dnuorgtiucric 32G DN dnuorGretrevnocnwoD )detcennocebtsuM( 7C SO DNG 6niPsaemaS2 2G DN dnuorGretrevnocnwoD )detcennocebtsuM( 8V SS dnuorGrezisehtnyS )deriuqeR( 12V SS dnuorGrezisehtnyS )deriuqeR( 9V SS dnuorGrezisehtnyS )deriuqeR( 02V SS dnuorGrezisehtnyS )deriuqeR( 01N Ee lbanEecafretnIeriW-39 1F R D rezisehtnyS tupnIFRretrevnocnwoD 11A TADa taDecafretnIeriW-38 1P C D rezisehtnyS retrevnocnwoD tuptuOpmuPegrahC 21K LCk colCecafretnIeriW-37 1P C U retrevnocpUrezisehtnyS tuptuOpmuPegrahC 31F ER NI tupnIecnerefeRlatsyrC6 1F R U retrevnocpUrezisehtnyS tupnIFR 41F ER TUO tuptuOecnerefeRlatsyrC5 1V NYS ylppuSrezisehtnyS V+( DD )

4 Data Sheet - Rev 2.1 ACD2202

ELECTRICAL CHARACTERISTICS

Table 2: Absolute Minimum and Maximum Ratings Stresses in excess of the absolute ratings may cause permanent damage. Functional operation is not implied under these conditions. Exposure to absolute ratings for extended periods of time may adversely affect reliability. The device may be operated safely over these conditions; however, parametric performance is guaranteed only over the conditions defined in the electrical specifications. Table 3: Operating Ranges Notes: (1) Mixer operation is possible beyond these frequencies with slightly reduced performance. (2) Case Temperature is 15 °C higher than Ambient Temperature, when Ambient Temperature is +25 °C, using the PC Board Layout shown in Figures 23-25. RETEMARAP NIM XAM TINU )82&72,52snip(egatloVylppuS )51nip( 5.6+ CDV 61,41hguorht01snipnoegatloV Vhtiw91hguorht SS V0= 3.0-V NYS 3.0+C DV )5&2,1snip(segatloVtupnI- 0 C DV )2&1snip(rewoPtupnI )5nip( )91&61,31snip( 01+ 71+ 02+ mBd erutarepmeTegarotS5 5-0 51+C ° erutarepmeTgniredloS- 0 62C ° emiTgniredloS- 4 c eS ,ecnadepmIlamrehT θ CJ -0 4W /C° RETEMARAP NIM PYT XAM TINU seicneuqerFretrevnocnwoD )1( )FR(tupnIFR )FI(tuptuOFI )OL(rotallicsOlacoL 009 568 0021 051 0531 zHM seicneuqerFrezisehtnyS FR(rezisehtnySretrevnocpU FR(rezisehtnySretrevnocnwoD D) FER(rotallicsOecnerefeR NI ) rotceteDesahP 004 004 0012 0041 zHM V:egatloVylppuS DD )82,72,52,51snip(0 7.4+5 +5 2.5+C DV T:erutarepmeTgnitarepOtneibmA A )2( 04--5 8+C °

Data Sheet - Rev 2.1 ACD2202 Table 4: Electrical Specifications - Downconverter Section (TA = 25 °C (7) , VDD = +5 VDC, RFIN = 1087 MHz, IFOUT = 45 MHz) Notes: (1) As measured in ANADIGICS test fixture with single-ended RF input. (2) As measured in ANADIGICS test fixture with differential RF inputs. (3) SSB noise figure will be approximately 3 dB higher with single-ended RF input. (4) Two tones: 1085 and 1091 MHz, -20 dBm each, 1091 MHz tone AM-modulated 99% at 15 kHz. (5) Two tones: 1085 and 1091 MHz, -15 dBm each. (6) R1 = 10 Ohms. (7) Case Temperature is 15 °C higher than Ambient Temperature, when Ambient Temperature is +25 °C, using the PC Board Layout shown in Figures 23-25. RETEMARAP NIM PYT XAM TINU niaGnoisrevnoC )1( niaGnoisrevnoC )2( 71 Bd erugiFesioNBSS )3(,)2( -47 B d noitaludoMssorC )6(,)4(,)2( -6 5-3 5-c Bd 3 dr noitrotsiDnoitaludomretnIredrO 3enoT-2 dr tnioPtpecretnItupnIredrO )tesffOzHK01@(esioNesahPOL )2(,)1( -0 9-5 .58-z H/cBd )42nip(rewoPtuptuOOL )2(,)1( 01-5 -- m Bd tuptuOFI@suoirupS scinomraHdnaslangiSOL lennahCtuptuOnihtiWstaeB zHM002ot2morfstaeBrehtO suoirupSrehtO 01- 84- 05- 01- mBd cBd mBd mBd )82&72nip(tnerruCylppuSFI tnerruCylppuSrettilpSesahP/csO )52nip( -0 35 4A m noitpmusnoCrewoP- 0 040 55W m

6 Data Sheet - Rev 2.1 ACD2202 Table 5: Electrical Specifications - Synthesizer Section (TA = 25 °C (4) , VDD = +5 VDC) Notes: (1) Measured at 250 kHz comparison frequency. (2) Measured at 62.5 kHz comparison frequency. (3) CP U and CPD = VCC/2. (4) Case Temperature is 15 °C higher than Ambient Temperature, when Ambient Temperature is +25 °C, using the PC Board Layout shown in Figures 23-25. RETEMARAP NIM PYT XAM TINU STNEMMOC ytivitisneStupnIralacserP FR:retrevnocpU U )61nip( )1( FR:retrevnocnwoD D )91nip( )2( FR:retrevnocpU U )61nip( )1( FR:retrevnocnwoD D )91nip( )2( 31- 11- 02+ 02+ mBd )ycneuqerfgnitareporevo( T A V,C°58+= DD V7.4+= TA V,C°58+= DD V7.4+= )31nip(ytivitisneSrotallicsOecnerefeR- 5 .0- V p-p tnerruCtuptuOpmuPegrahC )3( KNIS ECRUOS 52.1 52.1- - Am tnerruCylppuS- 5 30 5A m noitpmusnoCrewoP- 5 610 52W m

Data Sheet - Rev 2.1 ACD2202 Figure 4: Serial Data Input Timing Table 6: Digital Interface Specifications (TA = 25 °C, VDD = +5 VDC, ref. Figure 4) DATA N20: MSB N19 N10 N9 C2 C1: LSB (R20: MSB) (R19) R10 (R9) (C2) (C1: LSB) (R8) CLOCK LE LE OR tCS tCH tCWH tES tEW tCWL RETEMARAP NIM PYT XAM TINU V:tupnIhgiHcigoL H )21,11,01snip(0 .2- -V V:tupnIwoLcigoL L )21,11,01snip(- - 8 .0V noitpmusnoCtnerruCtupnIcigoL t:emiTpUteSkcolCotataD SC 05- - s n t:emiTdloHkcolCotataD HC 01-- s n t:hgiHhtdiWesluPkcolC HWC 05- - s n t:woLhtdiWesluPkcolC LWC 05- - s n t:emiTputeSelbanEdaoLotkcolC SE 05- - s n t:htdiWesluPelbanEdaoL WE 05- - s n t:emiTesiR R -0 1- s n t:emiTllaF F -0 1- s n

Divide ratios less than 3 are prohibited. bus, consisting of Data, Clock and Enable lines. programmed during a particular data entry cycle. to program each of the available registers. Table 8. The fifteen divider bits allow a divide ratio from 3 to 32767, inclusive, as shown in Table 9.

B > A, Divide ratios less than 3 are prohibited. Table 12. Note that there are some limitations on the ranges of the values for each counter.

Data Sheet - Rev 2.1 ACD2202 Table 15: Phase Detector Polarity Selection Programmable Modes Each register contains bits set aside for programming different modes of operation in the synthesizers. Currently, the only programmable mode is the polarity of the phase detector in each of the synthesizers. Bit D1 in each reference divider register controls this feature. Bits D2 through D5 in the reference divider registers and bits C1 and C2 in the main divider registers are reserved for future use, and have no current function. They can be set Table 14: Phase Detector Polarity Bit Figure 21: VCO Characteristics either high or low without affecting synthesizer performance. Setting Phase Detector Polarity Table 14 shows how bit D1 of each reference divider register controls the polarity of the phase detector associated with each PLL. The correct setting is determined by using Table 15 and Figure 21. Synthesizer Programming Example The following example for programming the two synthesizers in the ACD2202 details the calculations used to determine the required value of each bit in all four registers: Requirements Desired CATV input channel: “HHH” - 499.25 MHz picture carrier (501 MHz digital channel center frequency) (Second) IF picture carrier output frequency: 45.75 MHz (44 MHz digital channel center frequency) First IF frequency: 1087.75 MHz Phase detector comparison frequency for down converter (also tuning increment): 62.5 KHz Phase detector comparison frequency for up converter: 250 KHz Crystal reference oscillator frequency: 4 MHz Calculation of Reference Divider V alues The value for each reference divider is calculated by dividing the reference oscillator frequency by the desired phase detector comparison frequency: R = f OSC / fPD For the down converter, the 4 MHz crystal oscillator frequency and the 62.5 KHz phase detector comparison frequency are used to yield R PLL2 = 4 MHz / 62.5 KHz = 64, and so the bit values for the down converter R counter are R PLL2 = 000000001000000. S S D 00 ytiraloProtceteDesahP2LLP 10 y tiraloProtceteDesahP1LLP D ESAHP ROTCETED YTIRALOP OCV SCITSIRETCARAHC )21ERUGIFEES( 0e vitageN) 2(evruc 1e vitisoP) 1(evruc (1) (2) VCO INPUT VOLTAGE VCO OUTPUT FREQUENCY

14 Data Sheet - Rev 2.1 ACD2202 LSBMSB LSBMSB For the up converter, the 4 MHz crystal oscillator frequency and the 250 KHz phase detector comparison frequency are used to yield RPLL1 = 4 MHz / 250 KHz = 16, and so the bit values for the up converter R counter are R PLL1 = 000000000010000. Calculation of Main Divider V alues The values for the A and B counters are determined by the desired VCO output frequency for the local oscillator and the phase detector comparison frequency: N = f VCO / f PD B = trunc(N / P) A = N - (B x P) The down converter local oscillator frequency will be 1087.75 MHz - 45.75 MHz = 1042 MHz in this example. The main divider ratio for the down converter, then, is NPLL2 = 1042 MHz / 62.5 KHz = 16672. Since P = 64 in the ACD2202, BPLL2 = trunc(16672 / 64) = 260, and APLL2 = 16672 - (260 x 64) = 32. These results give bit values of BPLL2 = 00100000100 and A PLL2 = 0100000 for the B and A counters. The up converter local oscillator frequency will be 499.25 MHz + 1087.75 MHz = 1587 MHz in this example. Therefore, NPLL1 = 1587 MHz / 250 KHz = 6348, BPLL1 = trunc(6348 / 64) = 99, and APLL1 = 6348 - (99 x 64) = 12. These results give bit values of B PLL1 = 00001100011 and APLL1 = 0001100 for the B and A counters. Phase Detector Polarity Assuming the VCO for the up converter has a negative slope, the phase detector polarity for PLL1 should be negative, and D1 PLL1 = 1. If the VCO for the down converter has a positive slope, the phase detector polarity for PLL2 should be positive, and D1 PLL2 = 0. In summary, for this example, the four register programming words are shown in Tables 16 and 17: Table 16: PLL1 and PLL2 Reference Divider Register Bits for Synthesizer Programming Example Table 17: PLL1 and PLL2 Main Divider Register Bits for Synthesizer Programming Example 22 12 02 91 81 71 61 51 41 31 21 11 01 9 8 7 6 5 4 3 2 1 edoMmargorPr etnuoCRrediviDecnerefeRt celeS D D D D D R R R R R R R R R R R R R R R S S 0000100000000100000000 0000000000000001000010 22 12 02 91 81 71 61 51 41 31 21 11 01 9 8 7 6 5 4 3 2 1 margorP edoM retnuoCBrediviDniaMr etnuoCArediviDniaMt celeS C C B B B B B B B B B B B A A A A A A A S S 0 0 0010000010001 0 0 0 0 00 1 0 0 00001100011 0 0 01 1 0 01 1

Data Sheet - Rev 2.1 ACD2202

APPLICATION INFORMATION

17,18 VSYN VSS 20 k/c87 AV~ -1000 VSYN VSS pins 16,19 300 k/c87 VSYN VSS pin 13 VSYN VSS pin 14 200 /c87 GND pin 1 pin 2 pin 4 GND 5k /c87 5k /c87 10 /c87 pin 24 pin 5 OSCGND VSUP 15 /c87 10 pF GND pin 28pin 27 GND 5 /c87 5 /c87 5p F 5p F Figure 22: Equivalent Circuits

Data Sheet - Rev 2.1 ACD2202 Figure 27: Evaluation Fixture Schematic 27 16 15 1 14 222425 23 21 20 19 18 1728 26 987 106 115 124 133 RF IN OSC GND OSC GND T CKT ISET GNDRF IN DATACLK REF IN REF OUT V SYN V SS GND V SS GND RF D CP D V SUP OSC OUT CP U V IF +I F OUT- RF U V IF +I F OUT+ V SS V SS EN GND C20 ACD2202 C2 C3 C21 C23 C22 C24 C12 C11 C10 R9 C13 R10 C14 C15 R11 C17 C16 R13 RF RF +5V LO IN DT1 IF +5V R12 AFC OUT C18 C19 +30V 16 5 4 3 2J1 +30V +5V

18 Data Sheet - Rev 2.1 ACD2202 Table 20: Evaluation Fixture Parts List #METI EULAV EZIS NOITPIRCSED #TRAP YTQ RODNEV ,2C,1C 02C Fp0013 060r oticapac-pihC V05J101GOC93MRG 3 ataruM 3CF p93 060r oticapac-pihC V05C090GOC93MRG 1 ataruM 8C,7CF p033 060r oticapac-pihC V05J003GOC93MRG 2 ataruM 21CF u022A VV01 seireS roticapaC DN-TC0402ECP 1 YEK-IGID ,11C,9C ,12C,41C 22C Fu1.3 060r oticapac-pihC V61Z401V5Y93MRG 5 ataruM 32C,01CF p00013 060r oticapac-pihC V05K201R7X93MRG 2 ataruM 71C,51CF p00743 060r oticapac-pihC V52K274R7X93MRG 2 ataruM 61CF u13 060d ael-laidaR roticapac-pihC 050-K-501-R7X-311EPR 1 ataruM 81CF u10.3 060r oticapac-pihC V52K301R7X93MRG 1 ataruM 91CF u01V 53 TNAT .paCseireSET DN-TC6016SCP 1 YEK-IGID 42CF p513 060r oticapac-pihC V05J051GOC93MRG 1 ataruM 31CF p00653 060r oticapac-pihC V05K265R7X93MRG 1 ataruM ,5C,4C Fp333 060r oticapac-pihC V05J033GOC93MRG 3 ataruM 8R1 53 060r otsiseRpihC 015JYSG3-JRE 1 cinosanaP 5RK 013 060r otsiseRpihC 301JYSG3-JRE 1 cinosanaP 4R,3R,2RK 23 060r otsiseRpihC 202JYSG3-JRE 3 cinosanaP 21RK 13 060r otsiseRpihC 201JYSG3-JRE 1 cinosanaP 11RK 7.23 060r otsiseRpihC 272JYSG3-JRE 1 cinosanaP 7RK 33 060r otsiseRpihC 203JYSG3-JRE 1 cinosanaP 31RK 223 060r otsiseRpihC 322JYSG3-JRE 1 cinosanaP 01RK 2.83 060r otsiseRpihC 228JYSG3-JRE 1 cinosanaP 1R0 13 060r otsiseRpihC0 01JYSG3-JRE 1 cinosanaP

Data Sheet - Rev 2.1 ACD2202 Table 20: Evaluation Fixture Parts List continued #METI EULAV EZIS NOITPIRCSED #TRAP YTQ RODNEV 9R,6R0 3 060r otsiseRpihC 3060CZ 2 DCR 1LH n6.55 080r otcudnI CB-X050-SC5080 1 tfarclioC 2LH n865 080r otcudnI CB-X086-SC5080 1 tfarclioC 3LH n0725 080r otcudnI CB-X172-SC5080 1 tfarclioC 1D5 42VS1e doidrotcaraV 542VS1 1 abihsoT 1TD1 :4r emrofsnarT 2-1-4CTE 1 .cnI,MOC-A/M aciremAhtroN 1QV 03 DMS 32-TOSN PNrotsisnarT .lraD DN-TC31ATMMF 1 YEK-IGID 1XZ HM4l atsyrC DN-TC8162ES 1Y EK-IGID

20 Data Sheet - Rev 2.1 ACD2202 PACKAGE OUTLINE Figure 28: S8 Package Outline - 28 Pin SSOP

Data Sheet - Rev 2.1 ACD2202 NOTES

22 Data Sheet - Rev 2.1 ACD2202 NOTES

Data Sheet - Rev 2.1 ACD2202 NOTES

ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to change prior to a product’s formal introduction. Information in Data Sheets have been carefully checked and are assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers to verify that the information they are using is current before placing orders. WARNING ANADIGICS products are not intended for use in life support appliances, devices, or systems. Use of an ANADIGICS product in any such application without written consent is prohibited. ANADIGICS, Inc.

141 Mount Bethel Road

Warren, New Jersey 07059, U.S.A Tel: +1 (908) 668-5000 Fax: +1 (908) 668-5132 URL: http://www.anadigics.com E-mail: Mktg@anadigics.com Data Sheet - Rev 2.1 ACD2202

ORDERING INFORMATION

NOITPIRCSED GNIGAKCAPTNENOPMOC 1P8S2022DCAC °58+otC°04-P OSSniP82l eerrepseceip0053,leeR&epaT 0P8S2022DCAC °58+otC°04-P OSSniP82e butrepseceip05,sebuT