A8259 ALTERA | Alldatasheet
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Technical content
Features
n Optimized for FLEX and MAX architectures n Offers eight levels of individually maskable interrupts n Expandable to 64 interrupts n Offers a flexible priority resolution scheme n Provides programmable interrupt modes and vectors n Uses approximately 399 logic elements (LEs) in FLEX devices n Functionally based on the Intel 8259 device, except as noted in the “Variations & Clarifications” section on page 79 General
Description
function is a programmable interrupt controller. The a8259 can be initialized by the microprocessor through eight data bus lines ( din[7..0] and dout[7..0] ), and the ncs nrd nwr int , and ninta control signals. Figure 1 shows the symbol for the a8259 Figure 1. a8259 Symbol
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Word (ICW) 1 (see “ICW 1” on page 62 for more information). Table 1. a8259 Ports is idle, awaiting initialization. Input – Clock. All registers are clocked on the positive edge of the clock. and microprocessor during an interrupt service cycle. as a single device. This signal should also be ignored in buffered mode. signal to external bidirectional I/O buffers on the cascade control bus. external bidirectional I/O buffers.
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configuration, expanding the number of interrupts from 8 up to 64. usually have data significance. shows the a8259 initialization sequence flow diagram. Table 2. ICW & OCW Register Access for Programming & Initialization Note (1) nwr signal.ICW 2 1 Don’t Care Don’t Care This register always follows ICW 1.
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Figure 5. Typical Read Cycle There are four ICW command registers: ICW 1, ICW 2, ICW 3, and ICW 4. edge of the nwr signal. Table 3 describes the ICW 1 register format. Table 3. ICW 1 Register Format (Part 1 of 2) sequence), and the initialization cycle to skip ICW 4. When high, ICW 4 is accessed normally. a8259 is not cascaded with other a8259 functions.
clk. ICW 2 is deselected with the next falling edge of the nwr signal. Table 4 describes the ICW 2 register format. “ICW 3” on page 64). If SINGLE is high, ICW 3 is skipped. Table 3. ICW 1 Register Format (Part 2 of 2) otherwise, they are positive-edge-triggered.
5 A5 These bits set the interrupt vector address (bits 5
Table 4. ICW 2 Register Format
2 A10
3 A11 / T3
4 A12 / T4
5 A13 / T4
6 A14 / T6
7 A15 / T7
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via the din[7..0] bus, and data is clocked by the rising edge of clk. ICW 3 is deselected with the next falling edge of the nwr signal. format for the a8259 configured as a master. the a8259 is ready to accept interrupts. Table 5. ICW 3 Register Format (a8259 Master Configuration) Table 6. ICW 3 Register Format (a8259 Slave Configuration)
2 ID2
clk. ICW 4 is deselected with the next falling edge of the nwr signal. Table 7 describes the ICW 4 register formats. will be ready for operation. under program control whenever needed and in any order. Table 7. ICW 4 Register Format AEOI is enabled; otherwise, the AEOI is disabled. in buffered mode, this bit is in a “don’t care” condition. Events” on page 76 for more information. a8259 is in special fully nested mode. 5 0 These bits are unused and should be set low.
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via the din[7..0] bus, and the data is clocked by the rising edge of clk. Table 8 describes the OCW 1 register format. bus, and the data is clocked by the rising edge of clk. Table 9 describes the OCW 2 register format. Table 8. OCW 1 Register Format
0 M0 When more than one of these bits is high, the
otherwise, they are not masked. Table 9. OCW 2 Register Format
5 EOI These bits control the rotate and end of interrupt (EOI)
through 7 of the OCW 2 command register. OCW 3 is selected by setting the a0 pin, resetting bit 4 low, and bit 3 high. clocked by the rising edge of clk. Table 10. Interrupt Levels for SL (Bit 6 of OCW 2) Table 11. Rotate & EOI Commands Controlled by Bits 5 Through 7 of OCW 2
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Table 12 describes the OCW 3 register format. (1) Enable special mask mode. Table 12. OCW 3 Register Format
2 P When this bit is high and RR is high, the a8259 enters
(see “Poll Command” on page 75).
6 ESMM
7 0 This bit is unused and should be tied to GND. Table 13. Read Register Commands for Bits 0 & 1 of OCW 3 Table 14. Read Register Commands for Bits 0 & 1 of OCW 3
from the microprocessor freezes the IRR so all interrupts can be evaluated. protocol must be completed before the next interrupt can be received. Table 15 shows the IRR format. register. Table 16 shows the ISR format. Table 15. IRR Format
0 IR0
1 IR1
2 IR2
3 IR3
4 IR4
5 IR5
6 IR6
7 IR7
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The 3-byte interrupt sequence mode provides a 24-bit interrupt vector.
- One or more of the interrupt request signals (ir[7..0]) are high,
which sets the corresponding bit in the IRR.
- The a8259 checks the priority and masks for the interrupt, and if
appropriate, sets the int signal.
- The microprocessor responds by asserting ninta to the a8259.
- The a8259 latches the interrupt request signals on the falling edge
corresponding bit in the IRR on the following rising edge of ninta. following two bytes will contain the interrupt vector.
- The microprocessor responds to the vector opcode by sending two
Table 16. ISR Format
0 ISR0
1 ISR1
2 ISR2
3 ISR3
4 ISR4
5 ISR5
6 ISR6
7 ISR7
(1) Interval = 4 (bit 2 of ICW 1 is high). (2) A7 through A5 are derived from the contents of bits 5, 6, and 7 of ICW 1. (3) Interval = 8 (bit 2 of ICW 1 is low).
- The upper eight interrupt vector address bytes are released on the
contents of ICW 2. See Table 19.
- In AEOI mode, a bit in the ISR is reset on the rising edge of the last
command must be issued to end the interrupt sequence. Table 17. Contents of the First Interrupt Vector Bytes Notes (1), (2)
7 A7 A6 A5 1 1 1 0 0
6 A7 A6 A5 1 1 0 0 0
5 A7 A6 A5 1 0 1 0 0
4 A7 A6 A5 1 0 0 0 0
3 A7 A6 A5 0 1 1 0 0
2 A7 A6 A5 0 1 0 0 0
1 A7 A6 A5 0 0 1 0 0
0 A7 A6 A5 0 0 0 0 0
Table 18. Contents of the First Interrupt Vector Bytes Notes (2), (3)
7 A7 A6 1 1 1 0 0 0
6 A7 A6 1 1 0 0 0 0
5 A7 A6 1 0 1 0 0 0
4 A7 A6 1 0 0 0 0 0
3 A7 A6 0 1 1 0 0 0
2 A7 A6 0 1 0 0 0 0
1 A7 A6 0 0 1 0 0 0
0 A7 A6 0 0 0 0 0 0
Table 19. Contents of the Second Interrupt Vector Bytes
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Figure 6. 3-Byte Interrupt Sequence Mode Timing Waveforms
- One or more of the ir[7..0] signals are high, which sets the
corresponding bit in the IRR.
- The a8259 checks the priority and masks for the interrupt, and if
appropriate, sets the int signal.
- The microprocessor responds by asserting ninta to the a8259.
- The a8259 latches the ir signal on the falling edge of the ninta
dout[7..0] bus for this cycle.
- The microprocessor issues a second ninta pulse. An 8-bit interrupt
vector is driven onto the dout[7..0] bus. See Table 20.
(1) T7 through T3 derive from the contents of ICW 2 (bits 4 through 7).
- In AEOI mode, the ISR bit is reset on the rising edge of the last
command is issued to end the interrupt sequence. Figure 7. Single-Byte Interrupt Sequence Mode Timing Waveforms Table 20. Contents of the Interrupt Vector Bytes Note (1)
7 T7 T6 T5 T4 T3 1 1 1
6 T7 T6 T5 T4 T3 1 1 0
5 T7 T6 T5 T4 T3 1 0 1
4 T7 T6 T5 T4 T3 1 0 0
3 T7 T6 T5 T4 T3 0 1 1
2 T7 T6 T5 T4 T3 0 1 0
1 T7 T6 T5 T4 T3 0 0 1
0 T7 T6 T5 T4 T3 0 0 0
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a8259 Programmab le Interrupt Controller Data Sheet Operational Commands The a8259 supports several operational commands: n Priority rotation n EOI n Special mask mode (SMM) n Trigger modes n Poll command Priority Rotation The priority rotation command can adjust the interrupt request priority. The a8259 supports two types of rotation commands: automatic and specific rotation. The automatic rotation command rotates an interrupt that has just been serviced to the lowest priority. For example, if the ir5 interrupt has just been serviced, it is assigned the lowest priority, and the ir6 interrupt is then given the highest priority. For a system with equal priority interrupts, this process ensures that an interrupt waits for no more than seven other devices to be serviced. Automatic priority can be configured to operate on a non-specific EOI, or an automatic EOI using the OCW 2 command register. The specific rotation command is similar to the automatic rotation command, except the interrupt to be assigned the lowest priority is specified using bits 0 through 2 of the OCW 2 command register. Specific rotation can be accomplished by issuing a set priority command or a rotate-on-specific EOI command. End of Interrupt The EOI command is used to clear the last interrupt request serviced in an ISR bit. There are two methods used to issue an EOI command: automatic or non-specific. If an automatic EOI command is used (bit 1 of ICW 4 is high), a non-specific EOI command is issued at the rising edge of the last ninta pulse in the interrupt sequence. A non-specific EOI clears the ISR bit currently set at the highest priority. As long as a specific rotation is not used, a non-specific EOI will always clear last interrupt request serviced in the ISR bit. When the interrupt priority scheme is disturbed (usually in specific rotation), a specific EOI command is issued to clear the ISR bit of the interrupt request specified in bits 0 through 2 of the OCW 2 command register.
SMM, any interrupt may be selectively enabled using the mask register. after the falling edge of the first ninta pulse of the interrupt sequence. interrupt ID byte (bit 7) set high is placed on the dout[7..0] bus. Table 21 shows the interrupt ID word format for the poll command. Table 21. Interrupt ID Word Format
3 Don’t Care –
4 Don’t Care –
5 Don’t Care –
6 Don’t Care –
interrupt ID will be ignored.
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Figure 8 shows timing waveforms of the poll mode. Figure 8. Poll Mode Timing Waveforms for Bit 2 of OCW 3
- The interrupt requests are prioritized from 0 (highest priority) to 7
- When an interrupt request is acknowledged, the highest priority,
active until the interrupt is serviced.
a8259 Programmab le Interrupt Controller Data Sheet 3. During the appropriate handshaking sequence using the inta and ninta signals, the interrupt vector information is placed on the dout[7..0] bus. 4. In AEOI mode, the ISR bit is reset on the rising edge of the last ninta pulse. When not in AEOI mode, an appropriate EOI command is issued to end the interrupt sequence. Cascade Mode The cascade mode provides easy expansion of the a8259. In this mode, a single a8259 is configured as a master, while other a8259 functions (from 1 to 8 a8259 functions) are configured as slaves. The int signal of each slave is connected to an ir input on the master. The master’s int signal serves as an interrupt to the microprocessor. The master’s a8259 has a unique ncs signal and all other inputs to the a8259 are connected in parallel. When a slave receives an interrupt, the master asserts its int signal. The master enables the slave by placing the slave’s address on the casout[2..0] bus at the rising edge of the first ninta pulse. The slave is then responsible for completing the int and ninta handshaking required by the interrupt sequence. The slave will place its interrupt vector information on the dout[7..0] bus as required by the interrupt sequence. 3-Byte Interrupt Sequence in Cascade Mode For a 3-byte interrupt sequence in cascade mode, the handshaking between the int and ninta signals is as follows: 1. The master clocks the ISR bit that corresponds to the slave input on the falling edge of the first ninta pulse. The master also simultaneously resets the IRR bit and places a fixed vector opcode of binary 11001101 on the dout[7..0] bus. The vector opcode indicates that the two bytes that follow will contain the interrupt vector. The master enables the slave by placing the slave’s address on the casout[7..0] bus at the rising edge of the first ninta pulse.
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a8259 Programmab le Interrupt Controller Data Sheet 2. The microprocessor responds to the vector opcode by sending two more ninta pulses. The slave sets the appropriate ISR bit on the falling edge of the second ninta pulse. Simultaneously, the slave’s IRR bit is reset. The falling edge of the second ninta pulse also causes the slave to place the lower eight interrupt vector address bits on the slave’s dout[7..0] bus. The upper eight interrupt vector address bits are released on the falling edge of the third ninta pulse. 3. Two EOI commands must be issued to end the interrupt sequence: one to the master and the other to the slave. Single-Byte Interrupt Sequence in Cascade Mode In a single-byte interrupt sequence in cascade mode, the handshaking between the int and ninta signals is as follows: 1. The master sets the ISR bit that corresponds to the slave input on the falling edge of the first ninta pulse. The master also simultaneously resets the IRR bit and no data is driven onto the dout[7..0] bus for this cycle. The master enables the slave by placing the slave’s address on the casout[7..0] bus at the rising edge of the first ninta pulse. 2. The microprocessor issues a second ninta pulse. The slave sets the corresponding ISR bit on the falling edge of the second ninta pulse. Simultaneously, the slave’s IRR bit is reset. The slave drives the eight interrupt vector address bits onto the dout[7..0] bus. 3. Two EOI commands must be issued to end the interrupt sequence: one to the master and one to the slave. The slave’s address will remain on the casout[2..0] bus until the rising edge of the last ninta pulse. Special Fully Nested Mode This mode is used in conjunction with the cascade mode to preserve the priority structure within each slave. To operate in this mode, only bit 1 of ICW 4 of the master should be high. The slaves are configured in normal fully nested mode. When a slave is in service, it will not be locked out of the master’s priority logic; the master can recognize interrupts from higher priority sources within that slave.
a8259 Programmab le Interrupt Controller Data Sheet To complete the interrupt service and ensure that all interrupts from the slave have been serviced, the microprocessor sends a non-specific EOI command to the slave and reads the slave’s interrupt request register for active low signals. If the interrupt request register is low, a non-specific EOI command is issued to the master. Otherwise, the master services the pending interrupt request. Buffered Mode The buffered mode was originally intended to support board designs where tri-state buffers were needed to drive the data bus. The a8259 has separate nsp and nen signals, and the nen signal is always available. Instead of using the nsp signal, the buffered mode can determine the master/slave configuration by using bits 2 and 3 of the ICW 4 command register. Variations & Clarifications The following characteristics distinguish the Altera a8259 function from the Intel 8259A device: n A master clear is provided with the a8259. n A clock signal has been added, and synchronous design rules have been incorporated to improve operation and reliability. All input signals except nmrst and ir should be synchronous to the clock signal. All inputs must be asserted for one clock cycle to ensure reliable operation. n Bidirectional I/O pins are split into separate inputs, outputs, and corresponding tri-state control lines. This features makes the a8259 compatible with the bus or multiplexer scheme used internally in a design. n The dout[7..0], casout[2..0], int, cas_en, en, and nen outputs are driven by complex logic structures and are prone to glitches. If appropriate, these signals should be registered in a target application. n Because the a8259 can be used in various Altera architectures, no timing information is included in this data sheet. n Automatic EOI in slave mode is implemented within the a8259.
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