A8251

A8251 ALTERA | Alldatasheet

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Technical content

Features

n a8251 MegaCore function that provides an interface between a microprocessor and a serial communication channel n Optimized for FLEX architecture n Programmable word length, stop bits, and parity n Offers divide-by-1, -16, or -64 mode n Supports synchronous and asynchronous operation n Uses approximately 528 FLEX logic elements (LEs) n Includes: – Error detection – False start bit detection – Automatic break detection – Internal and external sync character detection n Functionally based on the Intel M8251A device, except as noted in the “Variations & Clarifications” on page 44 General

Description

MegaCore function provides an interface between a microprocessor and a serial communications channel. The a8251 receives and transmits data in a variety of configurations including 7- or 8-bit data words, with odd, even, or no parity, and 1 or 2 stop bits. The transmitter and receiver can be designed for synchronous or asynchronous operation. See Figure 1. Figure 1. a8251 Symbol

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Table 1. a8251 Ports (Part 1 of 2) selects receiver/transmitter data to read/write. Input – Parallel data input from the microprocessor or other controlling device. read or write operations are enabled. low, the microprocessor reads from the registers. low, the microprocessor writes to the registers. Input Low Asynchronous reset for the registers and control logic. Input – Receive data. Serial input from the modem or peripheral. Output Low Parallel data output to the microprocessor or other controlling device. a character to be read by the microprocessor.

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a8251 operates asynchronously. contains the bits shown in Table 2. Table 2. Mode Instruction Register Bits (Asynchronous Operation)

0 Baud rate factor ( b1)

1 Baud rate factor ( b2)

2 Word length select ( l1)

3 Word length select ( l2)

4 Parity select ( pen)

5 Parity select ( ep)

6 Stop bit select ( s1)

7 Stop bit select ( s2)

provide a means of programming the a8251 for synchronous operation. corresponding programmed function. level of the word length select bits and the corresponding word length. Table 3. Baud Rate Factor Bits 1 0 Divide-by-16 mode. The clock rate is 16 times the data rate. the ntxc signal and every 16 clocks thereafter. 1 1 Divide-by-64 mode. The clock rate is 64 times the data rate.

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select bits and the corresponding parity. stop bit select bits and the corresponding number of stop bits. contains the bits shown in Table 7. Table 4. Word Length Select Bits Table 5. Parity Select Bits Table 6. Stop Bit Select BIts

bits (bit 0 and bit 1) are always a logic low. programmed for asynchronous or synchronous operation. a8251 receiver. Otherwise the receiver is responsible for sync detection. receiver looks for two sync characters. Table 7. Mode Instruction Register Bits (Synchronous Operation)

6 External sync detect ( esd)

7 Single character sync ( scs)

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command instruction register data bits. name, and function of the status register data bits. Table 8. Command Instruction Register Format 0 Transmitter enable ( txen) A logic high enables the transmitter. 1 Data terminal ready ( dtr) A logic high forces the ndtr signal to go low. 2 Receiver enable ( rxe) A logic high enables the receiver. 3 Send break character ( sbrk) A logic high forces the txd signal to go low. 4 Error reset ( er) A logic high resets all error signals ( pe, oe, fe). 5 Request to send ( rts) A logic high forces the nrts signal to go low. 6 Internal reset ( ir) A logic high forces an internal state reset operation. 7 Enter hunt ( eh) A logic high causes the receiver to “hunt” for sync characters. The eh command is ignored during asynchronous operation.

to bit 4 (er) of the command instruction register. transmitter for sync character transmission. Table 9. Status Register Format

0 Transmitter ready

1 Receiver ready (rxrdy) Bit 1 reflects the state of the rxrdy signal.

2 Transmitter empty

Bit 2 reflects the state of the txempty signal.

3 Parity error (pe)

4 Overrun error (oe)

register were read by the microprocessor.

5 Framing error (fe)

6 Sync or break detect

Bit 6 reflects the state of the syn_brk output.

7 Data set ready (dsr) Bit 7 reflects the logical inverse of the state of

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a8251 Programmable Communications Interface Data Sheet Sync Character Two Register The sync character two register holds the value of the second sync character. The information is used by the receiver for sync comparison and by the transmitter for sync character transmission. Transmitter Buffer Register The transmitter buffer register (TBR) holds the transmitter data, which the a8251 formats, serializes, and transmits on the txd output. Once the existing data bits in the shift register are completely transmitted, the TBR transfers new data into the shift register. Receiver Buffer Register The receiver buffer register (RBR) holds the data received from the shift register. After the shift register receives a new data word, it is ready to transfer the new data word to the RBR. If the existing data in the RBR has already been read by the microprocessor, then the transfer takes place. If the existing RBR data has not been read, the overrun error (oe) bit is set. Operation This section describes the following: n Programming operation n Receiver operations: asynchronous and synchronous n Transmitter operations: asynchronous and synchronous n Reset operation Programming Operation The a8251 must be programmed in a specific order and immediately following a total state reset or an internal state reset. First, the microprocessor writes to the MIR. When synchronous operation is selected in the MIR, the microprocessor writes to the first sync character. If two sync characters are selected in the MIR, the second character is written immediately after the first; if only one sync character is selected, the second character is skipped. However, when asynchronous operation is selected, both sync characters are skipped. Once the microprocessor writes to the MIR and sync characters (if appropriate), the command instruction, status, TBR and RBR can be randomly accessed. Table 10 outlines the a8251 programming sequence including the logic level of control signals.

Table 10. a8251 Programming Sequence state reset or internal state reset. Skipped in asynchronous operation. command instruction register. 0 1 0 0 Microprocessor writes to the TBR. Random access. 0 0 1 0 Microprocessor reads the RBR. Random access.

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32nd rising edge of nrxc. Data is then sampled every 64 rising edges. calculated for future error detection. See Figure 3. Figure 3. Receiver Clock Signals the a8251 expects either a parity bit or a stop bit.

to a logic high. See Figure 4. Figure 4. Receiver Control & Error Signals (Asynchronous)

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a8251 Programmable Communications Interface Data Sheet Transmitter Operation (Asynchronous) When the a8251 is programmed for asynchronous operation, the transmitter includes the following functions: n Transmitter data register write/transfer n Transmitter start bit n Transmitter data n Transmitter parity bit n Transmitter stop bit Transmitter Data Register Write/Transfer After a total state reset operation and when bit 1 (txen) of the command instruction register is high, a transmit operation begins when the ncts signal is asserted. At this point, a data byte can be written to the TBR. However, if no data is written, the txd signal is held in a logic high state. In the initial write operation, if the shift register is empty, the data is immediately transferred and the shift operation begins. If a shift operation is underway, the microprocessor can write to the TBR; however, the data is not transferred to the shift register until the active shift operation is finished. When the TBR contains data that has not been transferred to the shift register, the txrdy signal and corresponding status bit go low. Once the data is transferred to the shift register and the TBR is empty, the txrdy signal and corresponding status bit will again be asserted. If both the shift register and TBR become empty, the txempty signal and corresponding status bit will be asserted. See Figure 5.

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If parity is enabled, the bit following the last data bit is the parity bit. there are an even number of 1s. character or characters. See Figure 7. Figure 7. Receiver Control & Error Signals (Synchronous)

a8251 Programmable Communications Interface Data Sheet Synchronization may occur either externally or internally. When external sync detect is selected, the synchronization process is as follows: 1. The microprocessor issues an enter hunt ( eh) command to the command instruction register. 2. The external sync detect circuitry forces the extsyncd signal high for at least one nrxc cycle. The extsyncd is sampled on the falling edge of nrxc, which forces the a8251 to stop looking for sync characters. At this point, the a8251 begins sampling rxd on the next rising edge of nrxc. The syn_brk signal and corresponding status bit are asserted and automatically cleared when the microprocessor reads the status data. When internal sync detect is selected, the receiver is responsible for detecting sync characters on the rxd signal. The sequence is as follows: 1. The microprocessor issues an enter hunt ( eh) command to the command instruction register. 2. The receiver section begins sampling for rxd on the rising edge of nrxc. The rxd input data is compared to the sync character(s). 3. Upon detecting the sync character(s), the a8251 begins sampling for the rxd signal on the next rising edge of nrxc. The syn_brk output and the corresponding status bit are asserted and automatically cleared when the microprocessor reads the status data. Parity and overrun errors are detected as in asynchronous operation. Synchronous operation continues until the microprocessor issues another enter hunt (eh) command. Transmitter Operation (Synchronous) A transmitter operation starts when the microprocessor writes the first character (usually a sync character) to the TBR. Once the ncts signal is asserted, the a8251 begins shifting the data byte out on the falling edge of the ntxc signal. Data transmission is synchronous to the ntxc clock. As in asynchronous operation, a parity bit is added to each data byte to determine the parity. See Figure 8.

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Figure 8. Transmitter Control Signals (Synchronous) character is inserted. Otherwise, two sync characters are inserted. reset to their initial state. running to achieve an internal state reset.

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Figure 10 shows the read and write data cycles for the a8251. Figure 10. Read & Write Data Cycles Intel 8251A device has a bidirectional data bus. Intel 8251A device has a bidirectional SYNDET/BRKDET signal. one ntxc clock cycle after the rising edge of the nwr signal.

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