A8237

A8237 ALTERA | Alldatasheet

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Table 1. a8237 Ports (Part 1 of 2) write transactions to internal registers are enabled. Input Low End of process. Permits external termination of the current DMA service. transactions from internal registers are enabled. Input High Reset. Clears the command, status, request, and temporary registers. peripherals requesting DMA service. into an external address latch. significant address byte of a DMA transfer. signals, and the lower four bits of the address bus. Output High Hold request. Requests control of the system bus. Output Low End of process. Indicates normal termination of a DMA transfer. Output Low I/O read output. Read strobe to I/O devices as DMA writes to memory.

Output Low I/O write output. Write strobe to I/O devices as DMA reads from memory. significant byte of the DMA address. has been granted to the peripheral. Table 1. a8237 Ports (Part 2 of 2)

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a8237 Programmab le DMA Controller Data Sheet Functional

Description

Figure 2 shows a block diagram of the a8237 MegaCore function. Figure 2. a8237 Block Diagram

Write Timing” and “Host Processor Read Timing” in Figure 3. contents of registers, effectively acting as write commands. (1) If the byte pointer is set to 0, the byte pointer flag selects the least significant byte. If the byte pointer is set to 1, the byte pointer flag selects the most significant byte. Byte Pointer Command” and “Set Byte Pointer Command” on page 17 for more information. Table 2. Register Address Map

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a8237 Programmab le DMA Controller Data Sheet Registers The a8237 MegaCore function contains the following registers: n Base address n Current address n Base word count n Current word count n Command n Mode n Request n Mask n Status n Temporary Base Address Register Each of the four DMA channels has a base address register, which is a 16-bit register that contains the starting address for DMA transfers. If auto-initialization is enabled, the a8237 loads the base address value into the current address register at the conclusion of a DMA cycle. The microprocessor writes to the base address register in two parts via dbin[7..0], and simultaneously loads the current address register. The byte pointer flag chooses either the least significant or most significant byte. The microprocessor cannot read the base address register. Current Address Register Each of the four DMA channels has a current address register, which is a 16-bit register containing the working address value for DMA transfers. The microprocessor loads the current address register simultaneously with the base address register via dbin[7..0]. If auto-initialization is enabled, the a8237 reloads the base address value at the conclusion of a DMA cycle. The microprocessor reads or writes to the current address register in two parts via the 8-bit data bus. The byte pointer flag chooses the least significant or most significant byte. After each DMA transfer, the current address value is updated with the incremented or decremented value from the temporary address register (except for channel 0 in memory-to-memory mode when the address can be held constant).

a8237 Programmab le DMA Controller Data Sheet Base Word Count Register Each of the four DMA channels has a base word count register, which is a 16-bit register containing the beginning word count for DMA transfers. If auto-initialization is enabled, the a8237 loads the base word count value into the current word count register at the conclusion of a DMA cycle. The microprocessor writes to the base word count register in two parts via dbin[7..0], and simultaneously loads the current word count register. The byte pointer flag chooses the least significant or most significant byte. The microprocessor cannot read the base word count register. Current Word Count Register Each of the four DMA channels has a current word count register, which is a 16-bit register containing the working word count value for DMA transfers. The microprocessor loads the current word count value simultaneously with the base word count register via dbin[7..0]. If auto-initialization is enabled, the a8237 reloads the base word count value at the conclusion of a DMA cycle. The microprocessor reads or writes to the current word count register in two parts via the 8-bit data bus. The byte pointer flag chooses the least significant or most significant byte. After each DMA transfer, the current word count value is updated with the decremented value from the temporary word count register. A terminal count flag is generated when the count rolls over from zero to hexadecimal FFFF. The number of DMA transfers is one more than the value written to the current word count register. For example, if a 16-word transfer is desired, the word count should be hexadecimal 000F. Command Register The command register configures the operation of the a8237, such as dreq and dack polarity, request priority, function enables/disables, and transfer timing. The microprocessor reads from or writes to the command register via the 8-bit data bus. The reset input or a master clear command clears the command register. See Table 3.

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Table 3. Command Register Format

software requests generated from the request register are unmaskable. the request register. See Table 5. Table 4. Mode Register Format Table 5. Request Register Format

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channels. Each DMA channel has a terminal count flag and a request flag. terminated by the neopin signal since the last read of the status register. flags are reset on each read of the status register. See Table 7. Table 6. Mask Register Format

cleared by the reset input or a master clear command. how to issue these commands. Table 7. Status Register Format

0 Channel 0 terminal count

1 Channel 1 terminal count

2 Channel 2 terminal count

3 Channel 3 terminal count

4 Channel 0 request

5 Channel 1 request

6 Channel 2 request

7 Channel 3 request

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The single mask bit command alters a single bit of the 4-bit mask register. Table 8. Single Request Bit Command Format Table 9. Single Mask Bit Command Format

a8237 Programmab le DMA Controller Data Sheet Clear Byte Pointer Command The byte pointer is a single-bit internal register that selects either the least significant or most significant byte of the 16-bit registers in the a8237. The byte pointer allows microprocessor write and read operations via the 8-bit data bus. The clear byte pointer command is a write command that resets the byte pointer, allowing subsequent access to the least significant byte of any 16-bit register. The data bus value for the clear byte pointer command is ignored. The reset input and the master clear command resets the byte pointer. Set Byte Pointer Command The set byte pointer command is a read command that sets the byte pointer, allowing subsequent access to the most significant byte of any 16-bit register. The data bus value for the set byte pointer command is unknown. The byte pointer is reset by the reset input and the master clear command. Master Clear Command The master clear command performs the same function as the reset input. This command resets the command, status, request, temporary and byte pointer registers, mode register counter, state machine, and also sets the mask register. Clear Mask Register Command The clear mask register command is a write command that resets the 4-bit mask register, enabling DMA requests from the dreq inputs. The data bus value for the clear mask register command is ignored. Clear Mode Register Counter Command The clear mode register counter command is a read command that resets the 2-bit mode register counter. This counter is incremented after each subsequent read of the mode register, allowing the user to cycle through all four mode registers. The data bus value for the clear mode register counter command is unknown. Operation This section describes the following a8237 MegaCore function operations: n State machine n Transfer modes n Other operations

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a8237 Programmab le DMA Controller Data Sheet State Machine The a8237 state machine synchronously controls various functions and can execute two types of DMA transfers. The memory to/from I/O transfer executes a simultaneous read and write operation, which requires a total of four states. The memory-to-memory transfer must perform the read and write operation separately, which requires a total of eight states (i.e., four states to read a memory location and store the data value in the temporary register, and another four to write the data value to a new memory location). The state machine loops through these states until the word count decrements to zero or until the transfer is externally aborted. Upon reset, the state machine enters an SI state. In the SI state, the internal registers can be programmed to the appropriate configuration. After programming, the a8237 continuously samples any unmasked DMA request (dreq) inputs. If a valid dreq is detected, the state machine transitions into the acquire bus state. See Figure 3 on page 22. In the S0 state, the hrq output is asserted, and the state machine waits for the microprocessor to assert hlda. When the hlda input is asserted, the a8237 controls the microprocessor via the 8-bit data bus, allowing DMA transfers to begin. n The S1 state is the first state of a DMA transfer, where the aen and adstb signals are asserted. The most significant byte of the address appears on the dbout[7..0] bus, and the least significant byte of the address appears on the aout[7..0] bus. n The S2 state is the second state, where adstb is deasserted, latching the most significant byte of the address from dbout[7..0] into the external latch. n The S3 state is the third state, where niorout or nmemr is asserted, depending on the direction of the DMA transfer. n The S4 state is the fourth state, where niowout or nmemw is asserted. If the end of the DMA cycle has not been reached, the state machine loops to the S2 state for the next transfer. If the most significant byte of the address does not change in subsequent cycles of the DMA transfer, then the S4 state transitions directly to the S2 state (i.e., the S1 state is skipped), which effectively suppresses adstb generation and speeds up block transfers.

a8237 Programmab le DMA Controller Data Sheet For memory-to-memory transfers, eight states are executed: four states to read a memory location and store the data value in the temporary register, and another four to write the data value to a new memory location. The equivalent of a S1 state is always executed for both memory accesses. To compensate for slower memory or peripherals, additional wait states can be inserted before the write state by holding ready low. Returning ready to high halts the insertion of wait states, allowing normal operation to continue beginning with the next cycle. Transfer Modes The a8237 MegaCore function has three transfer modes: single transfer, block transfer, and demand transfer modes. n In single transfer mode, only one DMA transfer is executed, and the state machine enters the SI state to allow prioritized access by other DMA channels. n In block transfer mode, the DMA transfers continue uninterrupted until the transfer is completed or neopin is asserted. n In demand transfer mode, the DMA transfers can be interrupted by deasserting the dreq input. When dreq is reasserted, the DMA transfers restart from the point at which they were stopped. Other Operations In addition to the state machine and transfer modes, the a8237 also provides the following operations for controlling DMA transfers: n Auto-initialization n Verify transfer n Memory-to-memory transfer n Priority encoding n Compressed timing n Extended timing

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a8237 Programmab le DMA Controller Data Sheet Auto-initialization Auto-initialization allows each DMA channel to reinitialize after the completion of a DMA cycle without microprocessor intervention. This feature is enabled by setting bit 4 of each channel’s mode register. The current address and current word count registers are loaded with the values contained in the base address and base word count registers following the normal or aborted (by the neopin signal) conclusion of a DMA cycle. Verify Transfer The verify transfer type operates as a normal DMA read or write operation, except that the I/O and memory control signals remain deasserted. (The verify transfer type originated as a means to refresh DRAM in early personal computers.) Memory-to-Memory Transfer The memory-to-memory DMA transfers are enabled via bit 0 of the command register, and must be performed using channels 0 and 1. The transfer is initiated by a software or hardware request on channel 0. At the conclusion of the DMA cycle, the terminal count bit for channel 1 is set in the status register, while the counterpart for channel 0 remains unchanged. Also, channel 0 can be configured to hold the address constant, allowing memory fills with a single data value. Priority Encoding The DMA requests are priority encoded to arbitrate between simultaneous requests or multiple pending requests. Two modes of priority encoding are available via bit 4 of the command register: n In fixed priority mode, the highest priority pending request is selected, with channel 0 as the highest priority and channel 3 as the lowest priority. n In rotating priority mode, the last channel to be serviced becomes the lowest priority when selecting the next channel, with the other channels rotating accordingly.

a8237 Programmab le DMA Controller Data Sheet Compressed Timing Compressed timing operation speeds the DMA transfer state machine loop by skipping the S3 state, thereby forcing the read and write pulses to be of equal duration (i.e., one clock cycle). This operation is enabled by setting bit 3 of the command register. Compressed timing operation cannot be used for memory-to-memory transfers. Extended Timing Extended timing operation asserts the write pulse during the S3 state, thereby forcing the read and write pulses to be of equal duration (i.e., two clock cycles). This operation is enabled by setting bit 5 of the command register. Extended timing operation cannot be used for memory-to- memory transfers.

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Figure 3 shows the timing waveforms for the a8237 MegaCore function. Figure 3. a8237 Timing Waveforms (Part 1 of 3)

Figure 3. a8237 Timing Waveforms (Part 2 of 3)

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Figure 3. a8237 Timing Waveforms (Part 3 of 3) be consistent with the implementation of the Intel and Harris devices. DMA cycle is aborted by a neopin. temporary address and word count registers. 8237A and Harris 82C27A devices. split into separate inputs, outputs, and enables as necessary.

a8237 Programmab le DMA Controller Data Sheet n The a8237 does not support the cascade mode because it would not be an efficient use of device resources. To implement this capability, the designer should use a hand-coded module or a stripped down a8237 function. n On the rising edge of CLK, the Harris 82C37A deasserts nMEMR on states 4 and 14, and deasserts nIOROUT on state 4. However, this approach is not reliable from a timing perspective for a CPLD. The Altera a8237 deasserts nMEMR on the falling edge of CLK at the end of states 4 and 14 and nIOROUT at the end of state 4. This action effectively extends the assertion of these signals by a 1/2 clock cycle. Revision History The information contained in the a8237 Programmable DMA Controller Data Sheet version 1.01 supersedes information published in previous versions. Version 1.01 includes the following changes: n The “State Machine” on page 18 was updated. n The waveforms in Figures 2 and 3 were updated. n The “Variations & Clarifications” on page 24 was updated. n Minor style and text changes were made throughout the document.

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