A6850

A6850 ALTERA | Alldatasheet

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Technical content

Features

n a6850 MegaCore function implementing an asychronous communications interface adapter (ACIA) n Optimized for FLEX and MAX architectures n Programmable word lengths, stop bits, and parity n Offers divide-by-1, -16, or -64 mode n Includes error detection n Uses approximately 237 FLEX logic elements (LEs) n Functionally based on the Motorola MC6850 device, except as noted in the “Variations & Clarifications” section on page 94 General

Description

MegaCore function implements an ACIA, which is a universal asynchronous receiver/transmitter (UART). The a6850 provides an interface between a microprocessor and a serial communications channel. The a6850 receives and transmits data in a variety of configurations, including 7- or 8-bit data words, with odd, even, or no parity, and 1 or 2 stop bits. See Figure 1. Figure 1. a6850 Symbol

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Table 1. a6850 Ports microprocessor can access the registers. pin was not included in the original MC6850 device. = 0 selects the control register. Input – Receive data. Serial data input from the modem or peripheral. Output Low Interrupt request to microprocessor. low, or bits 5 and 6 are both high. Output – Transmit data. Serial output to the modem or peripheral. Output – Parallel data output to the microprocessor or other controlling device.

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The receiver data register (RDR) is written to by the input shift register. new data into the RDR. If 7-bit data is selected, bit 7 is set to a logic low. The control register contains the control bits shown in Table 2. to a known state. See Table 3. Table 2. Control Register Bits

0 Counter divide select 0 (

1 Counter divide select 1 (

2 Word select 0 (

3 Word select 1 (

4 Word select 2 (

5 Transmitter control 0 (

6 Transmitter control 1 (

word length, parity, and number of stop bits. See Table 4. Table 3. Counter Divide Select Bits the txdata signal is asserted on the falling edge of txclk. 0 1 Divide-by-16 mode. The clock rate is 16 times the data rate. the first falling edge of txclk and every 16 clocks thereafter. 1 0 Divide-by-64 mode. The clock rate is 64 times the data rate. the first falling edge of txclk and every 64 clocks thereafter.

00072 Even

00172 O d d

01071 Even

01171 O d d

10082 None

10181 None

11081 Even

11181 O d d

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register empty (tdre) condition. n Controlling the request to send (nrts) signal. n Transmitting a break character on the txdata output. low, nirq generation is disabled. The status register contains the status bits shown in Table 6. Table 5. Transmitter Control Bits Table 6. Status Register Bits

0 Receive data register full ( rdrf)

1 Transmit data register empty ( tdre)

2 Data carrier detect ( ndcd)

3 Clear to send ( ncts)

4 Framing error ( fe)

5 Receiver overrun ( ovr)

6 Parity error ( pe)

7 Interrupt request ( irq)

a6850 Asynchronous Communications Interface Adapter Data Sheet Receiver Data Register Full Bit 0 of the status register is the rdrf bit. When high, the rdrf bit indicates that received data has been transferred into the receiver data register and is ready to be read by the microprocessor. If the receive interrupt is enabled, then the nirq signal is asserted. The rdrf bit is cleared when either the nreset signal is asserted, the microprocessor reads the receiver data register, or the control register is set to master reset mode. Transmitter Data Register Empty Bit 1 of the status register is the tdre bit. When high, the tdre bit indicates that data has been transferred from the transmitter data register to the output shift register. At this point, the a6850 is ready to accept a new transmit data byte. However, if the ncts signal is high, the tdre bit remains low regardless of the status of the transmitter data register. Also, if transmit interrupt is enabled, the nirq output is asserted. The tdre bit is cleared when the nreset signal is asserted, the microprocessor writes to the transmitter data register, or the control register is set to master reset mode. Data Carrier Detect Bit 2 of the status register is the ndcd bit, which reflects the status of the ndcd input. When the ndcd input transitions from low to high, the status bit is set to a logic high. If the receive interupts are enabled, a low on the nirq output is produced. Once the ndcd bit is set, it remains high regardless of the state of the ndcd input until one of the following conditions occurs: n The status register is read after reading the receiver data register. n The nreset signal is asserted. n The control register is set to master reset mode. Clear to Send Bit 3 of the status register is the ncts bit, and reflects the status of the ncts input. The nreset input sets ncts bit to a logic high until the next rising edge of txclk.

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a6850 Asynchronous Communications Interface Adapter Data Sheet Framing Error Bit 4 of the status register is the fe bit. The fe bit is asserted when a received character does not end with the specified stop bit, which is usually caused by a transmission error. The fe bit is set when the received character is transferred to the receiver data register, and remains set until another character is written to the receiver data register. The fe bit is cleared when either the nreset signal is asserted, a character is written to the receiver data register that does not have an fe error, or the control register is set to master reset mode. Receiver Overrun Bit 5 of the status register is the ovr bit. The ovr bit indicates a receiver overrun condition, i.e., one or more receiver data words have been overwritten in the input shift register. The overrun condition is considered to occur at the midpoint of the last received bit in the input shift register, when the previous word (in the RDR) has not yet been read by the microprocessor. However, the ovr bit is not set immediately when the overrun occurs, but is set when the valid word in the RDR is read. Thus, when the overrun condition occurs, it is the input shift register data that is overwritten, not the RDR data. The ovr bit is cleared when either the nreset signal is asserted, the data in the receiver data register is read, or the control register is set to master reset mode. Parity Error Bit 6 of the status register is the pe bit. When it is high, pe indicates that the parity bit received (over the rxdata input), does not match the parity calculated during the receive process. The pe bit is set when the data is written into the receiver data register. If no parity is selected, the parity error will not occur. The pe bit is cleared when either the nreset signal is asserted, the data is read from the receiver data register, or the control register is set in master reset mode. Interrupt Request Bit 7 of the status register is the irq bit, the logical inverse of the nirq output. See “Interrupt Operation” on page 93 of this data sheet for more information.

status, and control registers. operation as shown in Table 7. edge of the e input. See Figure 3. Table 7. Register Operations

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Figure 3. Read & Write Cycle Waveforms by-16 mode, however, the a6850 counts 8 clock edges and samples again. low sampled at the first rising edge and the 32nd rising edge of rxclk. Data is then sampled every 64 rising edges.

calculated for future error detection. See Figure 4. Figure 4. a6850 Receiver Functional Waveforms a6850 expects either a parity bit or a stop bit.

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a6850 Asynchronous Communications Interface Adapter Data Sheet The a6850 receives data with one or two stop bits. If one stop bit is specified in the control register, the a6850 will expect one stop bit before starting the synchronization process. Similarly, if two stop bits are specified, the synchronization process begins after detecting two stop bits. Error Detection Three errors can occur when receiving: framing, overrun, and parity. Refer to the status register error definitions on page 88 of this data sheet for more information. Receive Data Register Transfer Once the last stop bit is received or a framing error is detected, the data in the input shift register is transferred to the receiver data register. At this point, all status bits associated with this data word are set, including the rdrf bit. If receive interrupt is enabled, an interrupt on nirq is generated. The receive process concludes when the microprocessor reads data from the receiver data register. Transmit Operation The transmit operation includes the following functions: n Transmit data register write/transfer n Transmit start bit n Transmit data n Transmit parity bit n Transmit stop bit Transmit Data Register Write/Transfer A transmit operation starts when the microprocessor writes data to the transmitter data register. In the initial write operation, if the output shift register is empty, data is immediately transferred and the shift operation begins. However, if a shift operation is underway, the data is held in the transmitter data register until the active shift operation is finished. When data is in the transmitter data register, the tdre signal is cleared. Once the data is transferred to the output shift register, the tdre status bit is set. At this point, if transmit interrupt is enabled, an interrupt on nirq is generated.

a6850 Asynchronous Communications Interface Adapter Data Sheet Transmit Start Bit After data is transferred to the output shift register, a start bit (i.e., logic low) is placed on the txdata output on the falling edge of txclk. The start bit stays active for the number of clock cycles specified by the divide-by mode (i.e., 1, 16, or 64). Transmit Data After the start bit, the data bits shift out of the register one at a time, from the least significant to the most significant. The cycle time for each bit starts at the beginning of the specified clock cycle (i.e., -1, -16, or -64). The number of bits shifted out corresponds to the number of bits specified in the control register. Transmit Parity Bit If parity is enabled, the bit following the last data bit is a parity bit. The parity bit has a value that forces all the data to have the correct parity. For example, if parity is set to odd in the control register, then the parity bit guarantees there are an odd number of 1s (i.e., data plus the parity bit). If parity is set to even in the control register, then the parity bit guarantees there is an even number of 1s (i.e., data plus the parity bit). Transmit Stop Bit After the parity bit is transmitted, or the last data bit if parity is not enabled, one or two stop bits are transmitted on txdata output. The output then stays high until the beginning of the next data word transmission. Interrupt Operation The nirq output is designed to be an interrupt to a microprocessor or other controlling device. The nirq outputs a variety of conditions including transmit and receive.

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a6850 Asynchronous Communications Interface Adapter Data Sheet The transmit operation produces an interrupt (i.e., logic low on nirq) when the following conditions all occur: n Transmit interrupts are enabled. n The tdre flag is set. n The ncts signal is low. The receive operation produces an interrupt when the following conditions occur: n Receive interrupts are enabled (i.e., the rie control signal is high). n Any one of the following signals is set: rdrf, ovr, or ndcd. Reset Operation The a6850 is reset in one of two ways: n Driving the nreset input low. n Writing logic 1s into the cds bits of the control register. The nreset input is used as an asynchronous clear to all internal registers. Placing the a6850 into master reset will synchronously clear the registers. However, master reset only works if both clocks are running. Variations & Clarifications The following characteristics distinguish the Altera® a6850 from the Motorola MC6850 device: n The a6850 has separate input and output data buses, while the MC6850 device has a single tri-state data bus. n The nreset (asychronous reset) input on the a6850 is not available in the Motorola MC6850 device. n The a6850 bus interface was designed using synchronous design techniques, allowing it to operate using various part designations, speed grades, and optimization techniques. n The a6850 requires that the txclk signal is always connected to a free running clock, and that the e signal is high for at least one txclk clock cycle when reading and writing data.

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