A6402

A6402 ALTERA | Alldatasheet

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Technical content

Features

n a6402 MegaCore function implementing a universal asynchronous receiver/transmitter (UART) n Optimized for FLEX and MAX architectures n Uses approximately 162 FLEX logic elements (LEs) n Programmable word length, stop bits, and parity n Full duplex operation n Includes status flags for parity, framing, and overrun errors n Functionally based on the Harris HD-6402 device, except as noted in the “Variations & Clarifications” section on page 63 General

Description

MegaCore function implements a universal asynchronous receiver/transmitter (UART), which provides an interface between a microprocessor and a serial communications channel. See Figure 1. Figure 1. a6402 Symbol

58 Altera Corporation

Table 1. a6402 Ports Input High/low Even parity enable. When high, even parity; when low, odd parity. is asserted, parity is neither generated nor checked. Input – Receiver register clock. Operates at 16 times the receive data rate. Input – Receiver register input. Serial input data. Input – Transmitter buffer register input bus. Input – Transmitter register clock. Operates at 16 times the transmit data rate. Output High Framing error. Asserted when the expected stop bit(s) is not detected. Output – Receiver buffer register bus. transmitted out of the transmitter register. Output – Transmitter register output. Serial output data.

Table 2. a6402 Available Configurations

5 Odd 1 1 0 0 0 0 0

6 Odd 1 1 0 1 0 0 0

7 Odd 1 1 1 0 0 0 0

8 Odd 1 1 1 1 0 0 0

60 Altera Corporation

a6402 Universal Asynchronous Receiver/Transmitter Data Sheet Functional Figure 2 shows a block diagram of the a6402 Figure 2. a6402 Block Diagram

a6402 Universal Asynchronous Receiver/Transmitter Data Sheet Master Reset When the mr input is asserted, the pe fe oe , and dr outputs are asynchronously cleared and tbre and tre are asserted. The assertion of mr also sets all state machines to a default idle state. This condition does not affect the receiver buffer register. The mr input must be pulsed high at least once after power-up. When mr is deasserted, normal operation resumes at the next rising edge of trc or rrc Once the pe fe , and oe outputs are set, the only exit condition available is through asserting mr Control Register The control register contains the configuration of the data word, including the number of bits, calculated parity, and the number of stop bits. The crl input, an active high register enable, controls how the data word is loaded into the control register. When crl is asserted, the cls2 cls1 , pi, epe, and sbs inputs are loaded on the next rising edge of the trc input. Transmitter The transmitter consists of the following elements: n Transmitter control—The transmitter control contains three interconnected state machines. The first state machine regulates the baud rate by performing a divide-by-16 operation on the trc input. The second state machine detects the low-to-high transition on ntbrl, starts the serial transmission through tro, transfers data from the transmitter buffer register to the transmitter register, and generates the status signals tbre and tre. The third state machine controls the multiplexing of data bits to the tro output. n Transmitter buffer register—The transmitter buffer register is loaded via ntbrl, an active-low register enable, that causes tbr[7..0] to be loaded from the microprocessor on the next trc clock edge. n Transmitter register—The transmitter register loads the data from the transmitter buffer register and holds that data until transmission is complete.

62 Altera Corporation

a6402 Universal Asynchronous Receiver/Transmitter Data Sheet n Parity generator—The parity generator calculates the appropriate parity value depending on the epe input (even or odd parity) and the cls inputs (data word length). n Transmitter multiplexer—The transmitter multiplexer selects a single-bit data value and drives the tro output. Inputs to the transmitter multiplexer include the start bit, all eight bits from the transmitter register, the parity bit, and a stop or idle bit. Receiver The receiver consists of the following elements: n Receiver control—The receiver control contains three interconnected state machines. The first state machine performs a divide-by-16 operation on the rrc clock to determine when to sample the rri serial input. The second state machine detects the high-to-low transition on rri, determines if a valid start bit has been received, transfers data from the receiver register to the receiver buffer register, and generates the status signals dr and oe. The third state machine loads the individual bits of the receiver register and the fe and pe outputs. n Receiver register—The receiver register loads the number of data bits determined by the cls inputs. If the data word is less than eight bits, the data is right-justified with the MSBs filled with logic lows. When the stop bit is detected, the receiver register transfers its contents to the receiver buffer register. n Parity check—The parity check calculates the parity of the data word and the parity bit. If an error occurs, the pe output is asserted. Once asserted, the pe output can only be cleared by asserting the mr input. n Stop check—The stop check samples the middle of the first expected stop bit. If an error occurs, the fe output is asserted. Once asserted, the fe output can only be cleared by asserting the mr input.

Timing Waveforms Figure 3 shows the timing waveforms for the a6402. Figure 3. a6402 Functional Timing Waveforms registers are implemented as latches in the HD-6402 device. device, normal operation does not resume for 18 clock cycles. after the low-to-high transition of ntbrl. n In the a6402, the tro output is registered to remove glitches. This register uses trc as the clock source. device has no exit condition other than through asserting mr.

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