A1324LLHLX-

A1324_16 ALLEGRO | Alldatasheet

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Technical content

Description

New applications for linear output Hall-effect devices, such as displacement, angular position, and current measurement, require high accuracy in conjunction with small package size. The Allegro ™ A1324, A1325, and A1326 linear Hall-effect sensor ICs are designed specifically to achieve both goals. This temperature-stable device is available in a miniature surface mount package (SOT23W) and an ultra-mini through-hole single in-line package. These ratiometric Hall effect sensor ICs provide a voltage output that is proportional to the applied magnetic field. They feature a quiescent voltage output of 50% of the supply voltage. The A1324/25/26 feature factory programmed sensitivities of 5.0 mV/G, 3.125 mV/G, and 2.5 mV/G, respectively. The features of these linear devices make them ideal for use in automotive and industrial applications requiring high accuracy, and operate through an extended temperature range, –40°C to 150°C. Each BiCMOS monolithic circuit integrates a Hall element, temperature-compensating circuitry to reduce the intrinsic sensitivity drift of the Hall element, a small-signal high-gain amplifier, a clamped low-impedance output stage, and a proprietary dynamic offset cancellation technique. These devices are available in a 3-pin ultra-mini SIP package (UA), and a 3-pin surface mount SOT-23 style package (LH). Both are lead (Pb) free, with 100% matte tin leadframe plating. A1324-DS, Rev. 4 Features and Benefits

• Temperature-stable quiescent output voltage and sensitivity
• Output voltage proportional to magnetic flux density
• Low-noise output increases accuracy
• Precise recoverability after temperature cycling
• Ratiometric rail-to-rail output
• Wide ambient temperature range: –40°C to 150°C
• Immune to mechanical stress
• Solid-state reliability
• Enhanced EMC performance for stringent automotive

applications

Low Noise, Linear Hall Effect Sensor ICs with Analog Output Functional Block Diagram Not to scale A1324, A1325, and A1326 Packages Approximate footprint 3-pin SOT23-W 2 mm × 3 mm × 1 mm (suffix LH) 3-pin ultramini SIP 1.5 mm × 4 mm × 3 mm (suffix UA) Trim Control Sensitivity and Sensitivity TC Offset Tuned Filter GND VC C VOUT Dynamic Offset Cancellation To All Subcircuits Preliminary Datasheet Subject to Change Without Notice February 25, 2011

Linear Hall Effect Sensor ICs with Analog OutputA1324, A1325, and A1326 Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A. Absolute Maximum Ratings Characteristic Symbol Notes Rating Unit Forward Supply Voltage VCC 8 V Reverse Supply Voltage VRCC –0.1 V Forward Output Voltage VOUT 15 V Reverse Output Voltage VROUT –0.1 V Output Source Current IOUT(SOURCE) VOUT to GND 2 mA Output Sink Current IOUT(SINK) VCC to VOUT 10 mA Operating Ambient Temperature TA L temperature range –40 to 150 ºC Maximum Junction Temperature TJ(max) 165 ºC Storage Temperature Tstg –65 to 170 ºC Terminal List Table Name Number Function LH UA VCC 1 1 Input power supply; tie to GND with bypass capacitor VOUT 2 3 Output signal; also used for programming GND 3 2 Ground Selection Guide Part Number Packing1 Package Sensitivity (Typ.) (mV/G) A1324LLHLT-T 3 000 pieces per reel 3-pin SOT-23W surface mount 5.000A1324LLHLX-T 10 000 pieces per reel 3-pin SOT-23W surface mount A1324LUA-T2 500 pieces per bag 3-pin ultramini SIP through hole mount A1325LLHLT-T 3 000 pieces per reel 3-pin SOT-23W surface mount 3.125A1325LLHLX-T 10 000 pieces per reel 3-pin SOT-23W surface mount A1325LUA-T2 500 pieces per bag 3-pin ultramini SIP through hole mount A1326LLHLT-T 3 000 pieces per reel 3-pin SOT-23W surface mount 2.500A1326LLHLX-T 10 000 pieces per reel 3-pin SOT-23W surface mount A1326LUA-T2 500 pieces per bag 3-pin ultramini SIP through hole mount 1Contact Allegro™ for additional packing options. 2Contact factory for availability. Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Symbol Test Conditions* Value Unit Package Thermal Resistance RθJA Package LH, on 4-layer PCB with copper limited to solder pads 228 ºC/W Package LH, on 2-layer PCB with 0.463 in.2 of copper area each side, connected by thermal vias 110 ºC/W Package UA, on 1-layer PCB with copper limited to solder pads 165 ºC/W *Additional thermal information available on the Allegro website Description (continued) 2 3121 Pin-out Diagrams

Linear Hall Effect Sensor ICs with Analog OutputA1324, A1325, and A1326 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. OPERATING CHARACTERISTICS Valid throughout TA range, CBYPASS = 0.1 µF, VCC = 5 V; unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit1

Electrical Characteristics

Supply Voltage VCC 4.5 5.0 5.5 V Supply Current ICC No load on VOUT – 6.9 9 mA Power-On Time2 tPO TA = 25°C, CL (PROBE) = 10 pF – 32 – µs Supply Zener Clamp Voltage VZ TA = 25°C, ICC = 12 mA 6 8.3 – V Internal Bandwidth BWi Small signal, –3 dB – 17 – kHz Chopping Frequency3 fC TA = 25°C – 400 – kHz Output Characteristics Quiescent Voltage Output VOUT(Q) B = 0 G, TA = 25°C 2.425 2.500 2.575 V Output Referred Noise VN A1324, TA = 25°C, CBYPASS = 0.1 µF – 7.0 – mV(p-p) A1325, TA = 25°C, CBYPASS = 0.1 µF – 4.4 – mV(p-p) A1326, TA = 25°C, CBYPASS = 0.1 µF – 3.5 – mV(p-p) Input Referred RMS Noise Density VNRMS TA = 25°C, CBYPASS = open, no load on VOUT, f << BWi – 1.3 – mG/√Hz DC Output Resistance ROUT – < 1 – Ω Output Load Resistance RL VOUT to VCC 4.7 – – kΩ VOUT to GND 4.7 – – kΩ Output Load Capacitance CL VOUT to GND – – 10 nF Output Saturation Voltage VOUT(sat)HIGH RPULLDOWN = 4.7 kΩ, VCC = 5 V 4.7 – – V VOUT(sat)LOW RPULLUP = 4.7 kΩ, VCC = 5 V – – 0.30 V Magnetic Characteristics Sensitivity Sens A1324, TA = 25°C 4.750 5.000 5.250 mV/G A1325, TA = 25°C 2.969 3.125 3.281 mV/G A1326, TA = 25°C 2.375 2.500 2.625 mV/G Sensitivity Temperature Coefficient TCSens LH package; programmed at TA = 150°C, calculated relative to Sens at 25°C – 0 – %/°C UA package; programmed at TA = 150°C, calculated relative to Sens at 25°C – 0.03 – %/°C Error Components Sensitivity Drift at Maximum Ambient Operating Temperature ∆Sens(TAmax) LH package; from hot to room temperature –5 – 5 % UA package; from hot to room temperature –2.5 – 7.5 % Sensitivity Drift at Minimum Ambient Operating Temperature ∆Sens(TAmin) LH package; from cold to room temperature –3.5 – 8.5 % UA package; from cold to room temperature –6 – 4 % Continued on the next page…

Linear Hall Effect Sensor ICs with Analog OutputA1324, A1325, and A1326 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. OPERATING CHARACTERISTICS (continued) Valid throughout TA range, CBYPASS = 0.1 µF, VCC = 5 V; unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit1 Error Components (continued) Quiescent Voltage Output Drift Through Temperature Range ∆VOUT(Q) Defined in terms of magnetic flux density, B –10 – 10 G Linearity Sensitivity Error LinERR –1.5 – 1.5 % Symmetry Sensitivity Error SymERR –1.5 – 1.5 % Ratiometry Quiescent Voltage Output Error

4 RatVOUT(Q)

Throughout supply voltage range (relative to Ratiometry Sensitivity Error4 RatSens Throughout supply voltage range (relative to V Throughout supply voltage range (relative to V Sensitivity Drift Due to Package Hysteresis ∆SensPKG TA = 25°C, after temperature cycling – ±2 – % 11 G (gauss) = 0.1 mT (millitesla). 2See Characteristic Definitions section. 3fC varies up to approximately ±20% over the full operating ambient temperature range and process. 4Percent change from actual value at VCC = 5 V, for a given temperature.

Linear Hall Effect Sensor ICs with Analog OutputA1324, A1325, and A1326 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Power-On Time When the supply is ramped to its operating voltage, the device output requires a finite time to react to an input magnetic field. Power-On Time is defined as the time it takes for the output voltage to begin responding to an applied magnetic field after the power supply has reached its minimum specified operating voltage, V CC(min). V VCC VCC(min.) VOUT 90% VOUT t1= time at which power supply reaches minimum specified operating voltage t2= time at which output voltage settles within ±10% of its steady state value under an applied magnetic field t1 t2 tPO VCC(typ.) Quiescent Voltage Output In the quiescent state (that is, with no significant magnetic field: B = 0), the output, VOUT(Q) , equals a ratio of the supply voltage, VCC , throughout the entire operat- ing range of VCC and the ambient temperature, TA . Quiescent Voltage Output Drift Through Temperature Range Due to internal component tolerances and thermal con- siderations, the quiescent voltage output, VOUT(Q) , may drift from its nominal value through the operating ambient temperature range, T A . For purposes of specification, the Quiescent V oltage Output Drift Through Temperature Range, ∆VOUT(Q) (mV), is defined as: ∆VOUT(Q) VOUT(Q)TA – VOUT(Q)25°C= (1) Sensitivity The presence of a south-polarity magnetic field perpendicular to the branded surface of the package increases the output voltage from its quiescent value toward the supply voltage rail. The amount of the output voltage increase is proportional to the magnitude of the magnetic field applied. Conversely, the application of a north polarity field will decrease the output volt- age from its quiescent value. This proportionality is specified as the magnetic sensitivity, Sens (mV/G), of the device and is defined as: VOUT(B+) – VOUT(B–) B(+) – B(–)Sens = (2) where B(+) and B(–) are two magnetic fields with opposite polarities. Sensitivity Temperature Coefficient The device sensitivity changes with temperature, with respect to its sensitivity tem- perature coefficient, TCSENS . TCSENS is programmed at 150°C, and calculated relative to the nominal sensitivity programming temperature of 25°C. TCSENS (%/°C) is defined as: SensT2 – SensT1 SensT1 T2–T1 1TCSens = × 100% (3) where T1 is the nominal Sens programming temperature of 25°C, and T2 is the TCSENS programming temperature of 150°C. The ideal value of sensitivity through the temperature range, Sens IDEAL(TA), is defined as: SensT1 × (100% + TCSENS(TA –T1) )SensIDEAL(TA) = (4) Sensitivity Drift Through Temperature Range Second order sensitivity temperature coefficient effects cause the mag- netic sensitivity to drift from its ideal value through the operating ambient temperature, TA. For purposes of specification, the sensi- tivity drift through temperature range, ∆SensTC , is defined as: SensTA – SensIDEAL(TA) SensIDEAL(TA) ∆SensTC = × 100% (5) Sensitivity Drift Due to Package Hysteresis Package stress and relaxation can cause the device sensitivity at TA = 25°C to change during or after temperature cycling. This change in sensitivity follows a hysteresis curve. For purposes of specification, the Sensitivity Drift Due to Pack- age Hysteresis, ∆SensPKG , is defined as: Sens(25°C)2 – Sens(25°C)1 Sens(25°C)1 ∆SensPKG = × 100% (6) where Sens(25°C)1 is the programmed value of sensitivity at Characteristic Definitions

Linear Hall Effect Sensor ICs with Analog OutputA1324, A1325, and A1326 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. TA = 25°C, and Sens(25°C)1 is the value of sensitivity at TA = 25°C after temperature cycling TA up to 150°C, down to –40°C, and back to up 25°C. Linearity Sensitivity Error The 132x is designed to provide linear output in response to a ramping applied magnetic field. Consider two magnetic fields, B1 and B2. Ideally the sensitivity of a device is the same for both fields for a given supply voltage and temperature. Linearity sensitivity error is present when there is a difference between the sensitivities measured at B1 and B2. Linearity Sensitivity Error is calculated separately for the positive (LIN ERR+) and negative (LINERR– ) applied magnetic fields. Lin- earity Sensitivity Error (%) is measured and defined as: SensB(++) SensB(+) 1–LinERR+ = × 100% SensB(– –) SensB(–) (7) and LinERR = max(| LinERR+| , |LinERR–| ) (8) where: |VOUT(Bx) – VOUT(Q)| BX SensBx =  (9) and B(++), B(+), B(– –), and B(–) are positive and negative mag- netic fields with respect to the quiescent voltage output such that Symmetry Sensitivity Error The magnetic sensitivity of a device is constant for any two applied magnetic fields of equal magnitude and opposite polarities. Symmetry Error (%), is measured and defined as: SensB(+) SensB(–) 1–SymERR = × 100% (11) where SensBx is defined as in equation 9, and B(+), B(–) are posi- tive and negative magnetic fields such that |B(+)| = |B(–)|. Ratiometry Error The A132x features a ratiometric output. This means that the quiescent voltage output, VOUT(Q) , magnetic sensitivity, Sens, and clamp voltages, VCLPHIGH and VCLPLOW , are proportional to the supply voltage, VCC. In other words, when the supply voltage increases or decreases by a certain percent- age, each characteristic also increases or decreases by the same percentage. Error is the difference between the measured change in the supply voltage, relative to 5 V , and the measured change in each characteristic. The ratiometric error in quiescent voltage output, RatVOUT(Q) (%), for a given supply voltage, VCC, is defined as: VOUT(Q)VCC ⁄ VOUT(Q)5V VCC ⁄ 5 V1–RatVOUT(Q) = × 100% (12) The ratiometric error in magnetic sensitivity, RatSENS (%), for a given supply voltage, VCC, is defined as: SensVCC ⁄ Sens5V VCC ⁄ 5 V1–RatVOUT(Q) = × 100% (13)

Linear Hall Effect Sensor ICs with Analog OutputA1324, A1325, and A1326 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Typical Characteristics (30 pieces, 3 fabrication lots) ICCav (mA) Average Supply Current versus Ambient Temperature VCC = 5 V Average Postive Linearity versus Ambient Temperature VCC = 5 V Average Sensitivity Ratiometry versus Ambient TemperatureAverage Quiescent Voltage Output Ratiometry versus Ambient Temperature Average Negative Linearity versus Ambient Temperature VCC = 5 V – 40 25 150 TA (°C) – 40 25 150 TA (°C) – 40 25 150 TA (°C) – 40 25 150 TA (°C) – 40 25 150 TA (°C) 100 101 102 103 104 105Lin+av (%) 100 101 102 103 104 105Lin–av (%) RatSens(av) (%) 99.0 99.2 99.4 99.6 99.8 100.0 100.2 100.4 100.6 100.8 101.0 98.0 98.5 99.0 99.5 100.0 100.5 101.0 101.5 102.0 RatVOUTQ(av) (%) 5.5 to 5.0 V VCC 4.5 to 5.0 V 5.5 to 5.0 V VCC 4.5 to 5.0 V

Linear Hall Effect Sensor ICs with Analog OutputA1324, A1325, and A1326 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Typical Characteristics, continued (30 pieces, 3 fabrication lots) – 40 25 150 TA (°C) – 40 25 150 TA (°C) – 40 25 150 TA (°C) – 40 25 150 TA (°C) 2.425 2.445 2.465 2.485 2.505 2.525 2.545 2.565 ∆VOUT(Q)av (G) VOUT(Q) (V) VOUT(Q)av (V) 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Sensav (mV/G) Sensav (mV/G) 2.0 2.5 1.0 1.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ∆Sensav (%) -10 -10 10 4.5 5 VCC (V) 5.5 4.5 5 VCC (V) 5.5 Average Absolute Quiescent Voltage Output versus Ambient Temperature VCC = 5 V Quiescent Voltage Output versus Supply Voltage TA = 25°C Average Sensitivity versus Supply Voltage TA = 25°C Average Absolute Sensitivity versus Ambient Temperature VCC = 5 V Average Quiescent Voltage Output Drift versus Ambient Temperature ∆VOUT(Q)av values relative to 25°C, VCC = 5 V Average Sensitivity Drift versus Ambient Temperature ∆Sensav values relative to 25°C, VCC = 5 V A1324 A1325 A1326 A1324 A1325 A1326 A1324 A1325 A1326 A1324 A1325 A1326

Linear Hall Effect Sensor ICs with Analog OutputA1324, A1325, and A1326 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Amp Regulator Clock/Logic Hall Element Tuned Filter Anti-Aliasing LP Filter Concept of Chopper Stabilization Technique Typical Application Circuit Chopper Stabilization Technique When using Hall-effect technology, a limiting factor for switchpoint accuracy is the small signal voltage developed across the Hall element. This voltage is disproportionally small relative to the offset that can be produced at the output of the Hall IC. This makes it difficult to process the signal while maintaining an accurate, reliable output over the specified operating temperature and voltage ranges. Chopper stabilization is a unique approach used to minimize Hall offset on the chip. Allegro employs a patented technique to remove key sources of the output drift induced by thermal and mechanical stresses. This offset reduc- tion technique is based on a signal modulation-demodulation process. The undesired offset signal is separated from the magnetic field-induced signal in the frequency domain, through modulation. The subsequent demodulation acts as a modulation process for the offset, causing the magnetic field-induced signal to recover its original spectrum at baseband, while the DC offset becomes a high-frequency signal. The magnetic-sourced signal then can pass through a low-pass filter, while the modulated DC offset is suppressed. In addition to the removal of the thermal and stress related offset, this novel technique also reduces the amount of thermal noise in the Hall IC while completely removing the modulated residue resulting from the chopper operation. The chopper stabilization technique uses a high frequency sampling clock. For demodulation process, a sample-and-hold technique is used. This high-frequency operation allows a greater sampling rate, which results in higher accuracy and faster signal-processing capability. This approach desensitizes the chip to the effects of thermal and mechanical stresses, and produces devices that have extremely stable quiescent Hall output voltages and precise recoverability after temperature cycling. This technique is made possible through the use of a BiCMOS process, which allows the use of low-offset, low-noise amplifiers in combination with high- density logic integration and sample-and-hold circuits. GND 1[1] 3[2] Pin numbers in brackets refer to the UA package 2[3]VOUT VOUT A132x VCC 0.1 µF CBYPASS

Linear Hall Effect Sensor ICs with Analog OutputA1324, A1325, and A1326 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A.

0.55 REF

0.25 BSC

0.95 BSC

0.95 1.00 0.70 2.40 A Active Area Depth, 0.28 mm REF B C C B Reference land pattern layout All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances Branding scale and appearance at supplier discretion A PCB Layout Reference View Standard Branding Reference View Branded Face N = Last three digits of device part number NNN 2.90 +0.10 –0.20 4° +4° –0° 8X 10° REF 0.180+0.020 –0.053 0.05 +0.10 –0.05

0.25 MIN

1.91 +0.19 –0.06 2.98 +0.12 –0.08 1.00 ±0.13 0.40 ±0.10 For Reference Only; not for tooling use (reference DWG-2840) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown D Hall element, not to scale D D D1.49 0.96

Linear Hall Effect Sensor ICs with Analog OutputA1324, A1325, and A1326 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Package UA, 3-Pin SIP 2 31

1.27 NOM

1.02 MAX 45° 45° C 1.52 ±0.05 B Gate and tie bar burr area A B C Dambar removal protrusion (6X) A D E D E E

1.44 NOM

2.05 NOM

E Active Area Depth, 0.50 mm REF Branding scale and appearance at supplier discretion Hall element (not to scale) For Reference Only; not for tooling use (reference DWG-9065) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown Standard Branding Reference View NNN Mold Ejector Pin Indent = Supplier emblem N = Last three digits of device part number 0.41 +0.03 –0.06 0.43 +0.05 –0.07 14.99 ±0.25 4.09 +0.08 –0.05 3.02 +0.08 –0.05

0.79 REF

10° Branded Face

Linear Hall Effect Sensor ICs with Analog OutputA1324, A1325, and A1326 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Copyright ©2010-2013, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com

Revision History

Revision Revision Date Description of Revision Preliminary February 8, 2011 Update pin assignments Revision Revision Date Description of Revision Rev. 3 September 16, 2013 Update product selection Rev. 4 September 26, 2013 Fixed UA package drawing