951200201

ATMEL Corporation

Rad. Hard 32/40-bit IEEE Floating Point DSP

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TSC21020F ATMEL | Alldatasheet

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Superscalar IEEE Floating-Point-Processor
Off-Chip Harvard Architecture Maximizes Signal Processing Performance
50 ns, 20 MIPS Instruction Rate, Single Cycle Execution
60 MFLOPS Peak, 40 MFLOPS Sustained Performance
1024-Point Complex FFT Benchmark: 0.975 ms
Divide (y/x): 300 ns
Inverse Square Root (1/ /x): 450 ns
32-bit Single-Precision and 40-bit Extended-Precision IEEE Floating-Point Data Formats
32-bit Fixed-Point Formats, Integer and Fractional, with 80-bit Accumulators
IEEE Exception Handling with Interrupt on Exception
Three Independent Computation Units: Multiplier, ALU, and Barrel Shifter
Dual Data Address Generators with Indirect, Immediate, Modulo, and Bit Reverse Addressing Modes
Two Off-Chip Memory Transfers in Parallel with Instruction Fetch and Single-Cycle Multiply and ALU Operations
Multiply with Add and Subtract for FFT Butterfly Computation
Efficient Program Sequencing with Zero Overhead Looping: Single-Cycle Loop Setup
Single-Cycle Register File Context Switch
23ns External RAM Access Time for Zero-Wait-State, 40 ns Instruction Execution
IEEE JTAG Standard 1149.1 Test Access Port and On-chip Emulation Circuitry
223 CPGA package for breadboarding
256 Multi-layer Quad Flat Pack, Flat Leads, For Flight Models
Fully compatible with Analog Devices ADSP-21020
No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm 2
Tested up to a Total Dose of 100 krads (Si) according to MIL STD 883 Method 1019
SEU Error Note in GEO Orbit Better than 5E -7 Error/Device/Day (worst case)
For 25 MHz Specification, Contact Atmel for Availability
Quality Grades - ESCC with 9512/002 and QML-Q or V with 5962-99539 Introduction Atmel is manufacturing a radiation hard version of the Analog Devices ADSP-21020 32/40-bit Floating-Point DSP . The product is pin and code compatible with ADI pro duct, making system develop- ment straight forward and cost effective, using exi sting development tools and algorithms. Notes: 1. Design using patent from INPG-CNRS Denis BE SSOT/Raoul VELAZCO 2. Product licensed from Analog Devices Inc. Rad. Hard 32/40-bit IEEE Floating Point DSP TSC21020F

4153H–AERO–04/07 Functional Block Diagram

4153H–AERO–04/07 General Description The TSC21020F is single-chip IEEE floating-point pr ocessor optimized for digital signal processing applications (1) . Its architecture is similar to that of Analog Dev ices' ADSP- 2100 family of fixed-point DSP processors. Fabricated in a high-speed, low-power and radiation hard CMOS process, the TSC21020F has a 50ns instruction cycle time. With a high-performance On-chip instruc- tion cache, the TSC21020F can execute every instruction in a single cycle. The TSC21020F features: Independent Parallel Computation Units The arithmetic/logic unit (ALU), multiplier and shi fter perform single-cycle instructions. The units are architecturally arranged in parallel, maximizing computational throughput. A single multifunction instruction executes parallel ALU and multiplier operations. These computation units support IEEE 32-bit single-precis ion floating-point, extended preci- sion 40-bit floating-point, and 32-bit fixed-point data formats. Data Register File A general-purpose data register file is used for tr ansferring data between the computa- tion units and the data buses, and for storing inte rmediate results. This 10-port (16- register) register file, combined with the TSC21020 F's Harvard architecture, allows unconstrained data flow between computation units and off-chip memory. Single-Cycle Fetch of Instruction and Two Operands The TSC21020F uses a modified Harvard architecture in which data memory stores data and program memory stores both instructions an d data. Because of its separate program and data memory buses and On-chip instructi on cache, the processor can simultaneously fetch an operand from data memory, an operand from program memory, and an instruction from the cache, all in a single cycle. Memory Interface Addressing of external memory devices by the TSC210 20F is facilitated by On-chip decoding of high-order address lines to generate memory bank select signals. Separate control lines are also generated for simplified add ressing of page-mode DRAM. The TSC21020F provides programmable memory wait states, and external memory acknowledge controls allow interfacing to peripheral devices with variable access times. Instruction Cache The TSC21020F includes a high performance instructi on cache that enables three-bus operation for fetching an instruction and two data values. The cache is selective-only the instructions whose fetches conflict with program me mory data accesses are cached. This allows full-speed execution of core, looped operations such as digital filter multiply- accumulates and FFT butterfly processing. Hardware Circular Buffers The TSC21020F provides hardware to implement circul ar buffers in memory, which are common in digital filters and Fourier transform imp lementations. It handles address pointer wraparound, reducing overhead (thereby incr easing performance) and simplify- ing implementation. Circular buffers can start and end at any location. Flexible Instruction Set The TSC21020F's 48-bit instruction word accommodate s a variety of parallel opera- tions, for concise programming. For example, the TSC21020F can conditionally execute a multiply, an add, a subtract and a branch in a single instruction. 1. It is fully compatible with Analog Devices ADSP-2 1020

4153H–AERO–04/07 Development System The TSC21020F is supported with a complete set of s oftware and hardware develop- ment tools from Analog Devices. The ADSP-21000 Fami ly Development System from Analog Devices includes development software, an ev aluation board and an in-circuit emulator. Assembler Creates relocatable, COFF (Common Object File Forma t) object files from ADSP-21xxx assembly source code. It accepts standard C preproc essor directives for conditional assembly and macro processing. The algebraic syntax of the ADSP-21xxx assembly language facilitates coding and debugging of DSP algorithms. Linker/Librarian The Linker processes separately assembled object fi les and library files to create a sin- gle executable program. It assigns memory locations to code and to data in accordance with a user-defined architecture file that describe s the memory and I/O configuration of the target system. The Librarian allows you to grou p frequently used object files into a single library file that can be linked with your main program. Simulator The Simulator performs interactive, instruction-lev el simulation of ADSP-21xxx code within the hardware configuration described by a sy stem architecture file. It flags illegal operations and supports full symbolic disassembly. It provides an easy-to-use, window oriented, graphical user interface that is identica l to the one used by the ADSP- 21020 EZ-ICE Emulator. Commands are accessed from pull-down menus with a mouse. PROM Splitter Formats an executable file into files that can be u sed with an industry-standard PROM programmer. C Compiler and Runtime Library The C Compiler complies with ANSI specifications. I t takes advantage of the TSC21020F's high-level language architectural featu res and incorporates optimizing algorithms to speed up the execution of code. It in cludes an extensive runtime library with over 100 standard and DSP-specific functions. C Source Level Debugger A full-featured C source level debugger that works with the simulator or EZ-ICE emula- tor to allow debugging of assembler source, C source, or mixed assembler and C. Numerical C Compiler Supports ANSI Standard (X3J11.1) Numerical C as def ined by the Numeric C Exten- sions Group. The compiler accepts C source input co ntaining Numerical C extensions for array selection, vector math operations, comple x data types, circular pointers, and variably dimensioned arrays, and outputs ADSP-21xxx assembly language source code. ADSP- 21020 EZ-LAB ® Evaluation Board The EZ-LAB Evaluation Board is a general-purpose, s tandalone TSC21020F system that includes 32K words of program memory and 32K w ords of data memory as well as analog I/O. A PC RS-232 download path enables the u ser to download and run pro- grams directly on the EZ-LAB. In addition, it may be used in conjunction with the EZ-ICE Emulator to provide a powerful software debug environment. ADSP- 21020 EZ-ICE ® Emulator This in-circuit emulator provides the system design er with a PC-based development environment that allows non-intrusive access to the TSC21020F's internal registers through the processor's 5-pin JTAG Test Access Port . This use of On-chip emulation circuitry enables reliable, full-speed performance in any target. The emulator uses the same graphical user interface as the ADSP- 21020 Si mulator, allowing an easy transi-

4153H–AERO–04/07 tion from software to hardware debug. (See "Target System Requirements for Use of EZ-ICE Emulator" on page 27.) ®EZ-LAB and EZ-ICE are registered trademarks of Analog Devices, Inc. Additional Information This data sheet provides a general overview of TSC2 1020F functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP- 21020 User's Manual. For development system and pro gramming reference informa- tion, refer to the ADSP-21000 Family Development So ftware Manuals and the ADSP- 21020 Programmer's Quick Reference.

4153H–AERO–04/07 Architecture Overview Figure 1 shows a block diagram of the TSC21020F. The processor features:

Three Computation Units (ALU, Multiplier, and Shif ter) with a Shared Data Register File
Two Data Address Generators (DAG 1, DAG 2)
Program Sequencer with Instruction Cache
32-bit Timer
Memory Buses and Interface
JTAG Test Access Port and On-chip Emulation Suppor t Computation Units The TSC21020F contains three independent computatio n units: an ALU, a multiplier with fixed-point accumulator, and a shifter. In ord er to meet a wide variety of processing needs, the computation units process data in three formats: 32-bit fixed-point, 32-bit floating-point and 40-bit floating-point. The float ing-point operations are single-precision IEEE-compatible (IEEE Standard 754/854). The 32-bit floating-point format is the stan- dard IEEE format, whereas the 40-bit IEEE extended- precision format has eight additional LSBs of mantissa for greater accuracy. The multiplier performs floating-point and fixed-po int multiplication as well as fixed-point multiply/add and multiply/subtract operations. Integer products are 64 bits wide, and the accumulator is 80 bits wide. The ALU performs 45 st andard arithmetic and logic opera- tions, supporting both fixed-point and floating-poi nt formats. The shifter performs 19 different operations on 32-bit operands. These oper ations include logical and arithmetic shifts, bit manipulation, field deposit, and extract and derive exponent operations. The computation units perform single-cycle operations; there is no computation pipeline. The three units are connected in parallel rather th an serially, via multiple-bus connec- tions with the 10-port data register file. The outp ut of any computation unit may be used as the input of any unit on the next cycle. In a mu ltifunction computation, the ALU and multiplier perform independent, simultaneous operations. Data Register File The TSC21020F's general-purpose data register file is used for transferring data between the computation units and the data buses, a nd for storing intermediate results. The register file has two sets (primary and alternate) of sixteen 40-bit registers each, for fast context switching.

Figure 1. TSC21020F Block Diagram

Off-chip read/write of two operands to or from the register file
Two operands supplied to the ALU
Two operands supplied to the multiplier
Two results received from the ALU and multiplier ( three, if the ALU operation is a combined addition/subtraction). The processor's 48-bit orthogonal instruction word supports fully parallel data transfer and arithmetic operations in the same instruction. Address Generators and Program Sequencer Two dedicated address generators and a program sequ encer supply addresses for memory accesses. Because of this, the computation u nits need never be used to calcu- late addresses. Because of its instruction cache, t he TSC21020F can simultaneously fetch an instruction and data values from both off- chip program memory and off-chip data memory in a single cycle. The data address generators (DAGs) provide memory a ddresses when external mem- ory data is transferred over the parallel memory po rts to or from internal registers. Dual data address generators enable the processor to output two simultaneous addresses for dual operand reads and writes. DAG 1 supplies 32-bi t addresses to data memory. DAG 2 supplies 24-bit addresses to program memory for program memory data accesses. Each DAG keeps track of up to eight address pointer s, eight modifiers, eight buffer length values and eight base values. A pointer used for indirect addressing can be mod- ified by a value in a specified register, either be fore (premodify) or after (post-modify)

4153H–AERO–04/07 the access. To implement automatic modulo addressin g for circular buffers, the TSC21020F provides buffer length registers that can be associated with each pointer. Base values for pointers allow circular buffers to be placed at arbitrary locations. Each DAG register has an alternate register that can be activated for fast context switching. The program sequencer supplies instruction addresse s to program memory. It controls loop iterations and evaluates conditional instructi ons. To execute looped code with zero overhead, the TSC21020F maintains an internal loop counter and loop stack. No explicit jump or decrement instructions are required to maintain the loop. The TSC21020F derives its high clock rate from pipe lined fetch, decode and execute cycles. Approximately 70% of the machine cycle is available for memory accesses; con- sequently, TSC21020F systems can be built using slo wer and therefore less expensive memory chips. Instruction Cache The program sequencer includes a high performance, selective instruction cache that enables three-bus operation for fetching an instruc tion and two data values. This two- way, set-associative cache holds 32 instructions. T he cache is selective (only the instructions whose fetches conflict with program memory data accesses are cached), so the TSC21020F can perform a program memory data acc ess and can execute the cor- responding instruction in the same cycle. The program sequencer fetches the instruction from the cache instead of from program memory, enab ling the TSC21020F to simulta- neously access data in both program memory and data memory. Context Switching Many of the TSC21020F's registers have alternate re gister sets that can be activated during interrupt servicing to facilitate a fast context switch. The data registers in the reg- ister file, DAG registers and the multiplier result register all have alternate sets. Registers active at reset are called primary registers; the others are called alternate reg- isters. Bits in the MODE1 control register determin e which registers are active at any particular time. The primary/alternate select bits for each half of the register file (top eight or bottom eight registers) are independent. Likewise, the top four and bottom four register sets in each DAG have independent primary/alternate select bits. This scheme allows passing of data between contexts. Interrupts The TSC21020F has four external hardware interrupts , nine internally generated inter- rupts, and eight software interrupts. For the exter nal interrupts and the internal timer interrupt, the TSC21020F automatically stacks the arithmetic status and mode (MODE1) registers when servicing the interrupt, allowing fi ve nesting levels of fast service for these interrupts. An interrupt can occur at any time while the TSC210 20F is executing a program. Inter- nal events that generate interrupts include arithme tic exceptions, which allow for fast trap handling and recovery. Timer The programmable interval timer provides periodic i nterrupt generation. When enabled, the timer decrements a 32-bit count register every cycle. When this count register reaches zero, the TSC21020F generates an interrupt and asserts its TIMEXP output. The count register is automatically reloaded from a 32-bit period register and the count resumes immediately.

System Interface Figure 2 shows an TSC21020F basic system configuration. addressing of page-mode DRAMs. program memory. All banks are independently programmable for 0-7 wait states. between the 40-bit register file and the PMD bus. the lower 16 bits are ignored. Figure 2. Basic System Configuration

4153H–AERO–04/07 program and data memory interfaces in a high impeda nce state. In addition, three-state controls (DTMS and PMTS) allow an external device to place either the program or data memory interface in a high impedance state without affecting the other interface and without halting the TSC21020F unless it requires a memory access from the affected interface. The three-state controls make it easy fo r an external cache controller to hold the TSC21020F off the bus while it updates an external cache memory. JTAG Test and Emulation Support The TSC21020F implements the boundary scan testing provisions specified by IEEE Standard 1149.1 of the Joint Testing Action Group ( JTAG). The TSC21020F's test access port and On-chip JTAG circuitry is fully com pliant with the IEEE 1149.1 specifi- cation. The test access port enables boundary scan testing of circuitry connected to the TSC21020F's I/O pins. The TSC21020F also implements On-chip emulation through the JTAG test access port. The processor's eight sets of breakpoint range regi sters enable program execution at full speed until reaching a desired breakpoint addr ess range. The processor can then halt and allow reading/writing of all the processor 's internal registers and external mem- ories through the JTAG port.

4153H–AERO–04/07 Pin Descriptions This section describes the pins of the TSC21020F. W hen groups of pins are identified with subscripts, e.g. PMD 47-0 , the highest numbered pin is the MSB (in this case , PMD 47 ). Inputs identified as synchronous (S) must meet t iming requirements with respect to CLKIN (or with respect to TCK for TMS, T DI, and TRST). Those that are asynchronous (A) can be asserted asynchronously to CLKIN. Note: O = Output; I = Input; S = Synchronous; A = As ynchronous; P = Power Supply; G = Ground. Pin Name Type Function PMA 23-0 O Program Memory Address. The TSC21020F outputs an address in program memory on these pins. PMD 47-0 I/O Program Memory Data. The TSC21020F inputs and outputs data and instructions on these pins. 32-bit fixed-point data and 32-bit single- precision floating-point data is transferred over bits 47-16 of the PMD bus. PMS 1-0 O Program Memory Select lines. These pins are asserted as chip selects for the corresponding banks of program memory. Memory banks must be defined in the memory control registers. These pins are decoded program memory address lines and provide an early indication of a possible bus cycle. PMRD O Program Memory Read strobe. This pin is asserted when the TSC21020F reads from program memory. PMWR O Program Memory Write strobe. This pin is asserted when the TSC21020F writes to program memory. PMACK I/S Program Memory Acknowledge. An external device de-asserts this input to add wait states to a memory access. PMPAGE O Program Memory Page Boundary. The TSC21020F asserts this pin to signal that a program memory page boundary has been crossed. Memory pages must be defined in the memory control registers. PMTS I/S Program Memory Three-State Control. PMTS places the program memory address, data, selects, and strobes in a high-impedance state. If PMTS is asserted while a PM access is occurring, the processor will halt and the memory access will not be completed. PMACK must be asserted for at least one cycle when PMTS is de-asserted to allow any pending memory access to complete properly. PMTS should only be asserted (low) during an active memory access cycle. DMA 31-0 O Data Memory Address. The TSC21020F outputs an address in data memory on these pins. DMD 39-0 I/O Data Memory Data. The TSC21020F inputs and outputs data on these pins. 32-bit fixed-point data and 32-bit single-precision floating-point data is transferred over bits 39-8 of the DMD bus. DMS 3-0 O Data Memory Select lines. These pins are asserted as chip selects for the corresponding banks of data memory. Memory banks must be defined in the memory control registers. These pins are decoded data memory address lines and provide an early indication of a possible bus cycle.

4153H–AERO–04/07 DMRD O Data Memory Read strobe. This pin is asserted when the TSC21020F reads from data memory. DMWR O Data Memory Write strobe. This pin is asserted when the TSC21020F writes to data memory. DMACK I/S Data Memory Acknowledge. An external device de-asserts this input to add wait states to a memory access. DMPAGE O Data Memory Page Boundary. The TSC21020F asserts this pin to signal that a data memory page boundary has been crossed. Memory pages must be defined in the memory control registers. DMTS I/S Data Memory Three-State Control. DMTS places the data memory address, data, selects, and strobes in a high-impedance state. If DMTS is asserted while à DM access is occurring, the processor will halt and the memory access will not be completed. DMACK must be asserted for at least one cycle when DMTS is de-asserted to allow any pending memory access to complete properly. DMTS should only be asserted (low) during an active memory access cycle. CLKIN I External clock input to the TSC21020F. The instruction cycle rate is equal to CLKIN. CLKIN may not be halted, changed, or operated below the specified frequency. RESET I/A Sets the TSC21020F to a known state and begins execution at the program memory location specified by the hardware reset vector (address). This input must be asserted (low) at power-up. IRQ 3-0 I/A Interrupt request lines; may be either edge-rigg ered or level-sensitive. FLAG 3-0 I/O/A External Flags. Each is configured via control bits as either an input or output. As an input, it can be tested as a condition. As an output, it can be used to signal external peripherals. BR I/A Bus Request. Used by an external device to request control of the memory interface. When BR is asserted, the processor halts execution after completion of the current cycle, places all memory data, addresses, selects, and strobes in a high-impedance state, and asserts BG. The processor continues normal operation when BR is released. BG O Bus Grant. Acknowledges a bus request (BR), indicating that the external device may take control of the memory interface. BG is asserted (held low) until BR is released. TIMEXP O Timer Expired. Asserted for four cycles when the value of TCOUNT is decremented to zero. RCOMP Not available Can be set to any voltage level. EVDD P Power supply (for output drivers), nominally + 5V dc (10 pins). EGND G Power supply return (for output drivers); (16 pins). IVDD P Power supply (for internal circuitry), nominal ly + 5V dc (4 pins). IGND G Power supply return (for internal circuitry); (7 pins). Pin Name Type Function

TCK I Test Clock. Provides an asynchronous clock for JTAG boundary scan. 20 k Ω internal pull-up resistor. has a 20 k Ω internal pull-up resistor. TDO O Test Data Output. Serial scan output of the bou ndary scan path. TSC21020F. TRST has a 20 k Ω internal pull-up resistor. Table 1. PGA Pin Configuration

Table 1. PGA Pin Configuration (Continued)

Table 2. MQFP Pin Configuration

1 IGND 65 IGND 129 IGND 193 IGND

2 IVDD 66 IVDD 130 IVDD 194 IVDD

3 DMD19 67 PMD25 131 PMA19 195 DMA15

4 DMD18 68 PMD26 132 PMA18 196 EGND

5 DMD17 69 PMD27 133 PMA17 197 DMA16

6 DMD16 70 EVDD 134 PMA16 198 DMA17

7 EGND 71 PMD28 135 EGND 199 DMA18

8 DMD15 72 PMD29 136 PMA15 200 DMA19

9 DMD14 73 PMD30 137 PMA14 201 EVDD

10 DMD13 74 PMD31 138 PMA13 202 DMA20

11 DMD12 75 EGND 139 PMA12 203 DMA21

12 EVDD 76 PMD32 140 EVDD 204 DMA22

13 DMD11 77 PMD33 141 PMA11 205 DMA23

14 DMD10 78 PMD34 142 PMA10 206 EGND

15 DMD9 79 PMD35 143 PMA9 207 DMA24

16 DMD8 80 EVDD 144 PMA8 208 DMA25

17 IGND 81 IGND 145 IGND 209 IGND

18 IVDD 82 IVDD 146 IVDD 210 IVDD

19 EGND 83 PMD36 147 EGND 211 DMA26

20 DMD7 84 PMD37 148 PMA7 212 DMA27

21 DMD6 85 PMD38 149 PMA6 213 EVDD

22 DMD5 86 PMD39 150 PMA5 214 DMA28

23 DMD4 87 EGND 151 PMA4 215 DMA29

24 EVDD 88 PMD40 152 EVDD 216 DMA30

25 DMD3 89 PMD41 153 PMA3 217 DMA31

26 DMD2 90 PMD42 154 PMA2 218 EGND

27 DMD1 91 PMD43 155 PMA1 219 DMPAGE

28 DMD0 92 EVDD 156 PMA0 220 BR

29 EGND 93 PMD44 157 EGND 221 BG

30 PMD0 94 PMD45 158 TIMEXP 222 DMS0

31 PMD1 95 PMD46 159 EVDD 223 DMS1

32 PMD2 96 PMD47 160 EGND 224 EVDD

33 IGND 97 IGND 161 IGND 225 IGND

34 IVDD 98 IVDD 162 IVDD 226 IVDD

35 PMD3 99 EGND 163 IRQ3 227 DMS2

The TSC21020F instruction set provides a wide varie ty of programming capabilities.

36 EVDD 100 PMTS 164 IRQ2 228 DMS3

37 PMD4 101 PMWR 165 IRQ1 229 DMD39

38 PMD5 102 PMACK 166 IRQ0 230 DMD38

39 PMD6 103 PMRD 167 EVDD 231 EGND

40 PMD7 104 RCMP 168 FLAG0 232 DMD37

41 EGND 105 EVDD 169 FLAG1 233 DMD36

42 PMD8 106 RESET 170 FLAG2 234 DMD35

43 PMD9 107 CLKIN 171 FLAG3 235 DMD34

44 PMD10 108 DMRD 172 EGND 236 EVDD

45 PMD11 109 DMACK 173 DMA0 237 DMD33

46 EVDD 110 DMWR 174 DMA1 238 DMD32

47 PMD12 111 EVDD 175 DMA2 239 DMD31

48 PMD13 112 DMTS 176 DMA3 240 DMD30

49 IGND 113 IGND 177 IGND 241 IGND

50 IVDD 114 IVDD 178 IVDD 242 IVDD

51 PMD14 115 TCK 179 EVDD 243 EGND

52 PMD15 116 TMS 180 DMA4 244 DMD29

53 EGND 117 TDI 181 DMA5 245 DMD28

54 PMD16 118 TDO 182 DMA6 246 DMD27

55 PMD17 119 TRST 183 DMA7 247 DMD26

56 PMD18 120 PMPAGE 184 EGND 248 EVDD

57 PMD19 121 PMS0 185 DMA8 249 DMD25

58 EVDD 122 PMS1 186 DMA9 250 DMD24

59 PMD20 123 EGND 187 DMA10 251 DMD23

60 PMD21 124 PMA23 188 DMA11 252 EGND

61 PMD22 125 PMA22 189 EVDD 253 DMD22

62 PMD23 126 PMA21 190 DMA12 254 DMD21

63 EGND 127 PMA20 191 DMA13 255 DMD20

64 PMD24 128 EVDD 192 DMA14 256 EVDD

Table 2. MQFP Pin Configuration (Continued)

4153H–AERO–04/07 The instruction types are grouped into four categories:

Compute and Move or Modify
Program Flow Control
Immediate Move
Miscellaneous The instruction types are numbered; there are 22 ty pes. Some instructions have more than one syntactical form; for example, Instruction 4 has four distinct forms. The instruc- tion number itself has no bearing on programming, b ut corresponds to the opcode recognized by the TSC21020F device. Because of the width and orthogonality of the instr uction word, there are many possible instructions. For example, the ALU supports 21 fixe d-point operations and 24 floating- point operations; each of these operations can be the compute portion of an instruction. The following pages provide an overview and summary of the TSC21020F instruction set. For complete information, see the ADSP-21020 U ser's Manual from Analog Devices. For additional reference information, see the ADSP- 21020 Programmer's Quick Reference from Analog Devices. This section also contains several reference tables for using the instruction set.
Table 3 describes the notation and abbreviations u sed.
Table 4 lists all condition and termination code m nemonics.
Table 5 lists all register mnemonics.
Table 6 through 9 list the syntax for all compute (ALU, multiplier, shifter or multifunction) operations.
Table 10 lists interrupts and their vector address es.

Table 3. Syntax Notation Conventions

Table 4. Condition and Termination Codes

Table 5. Universal Registers

Refer to User's Manual for bit-level definitions of each register. Table 6. ALU Compute Operations Table 5. Universal Registers (Continued)

Table 6. ALU Compute Operations (Continued)

4153H–AERO–04/07 Multiplier Compute Operations Rn, Rx, Ry R15-R0; register file location, fixed-poi nt Fn, Fx, Fy F15-F0; register file location, floating-point MRxF MR2F, MR1F, MR0F; multiplier result accumulator s, foreground MRxB MR2B, MR1B, MR0B; multiplier result accumulator s, background |x-input | |y-input | |data format |) | rounding | S Signed input U Unsigned input I Integer input(s) F Fractional input(s) FR Fractional inputs, Rounded output (SF) Default format for 1-input operations (SSF) Default format for 2-input operations Rn MRF MRB = Rx * Ry( S US U F I FR ) Fn = Fx * Fy Rn Rn MRF MRB MR F MR B MR F MR B + Rx * Ry S US U F I FR Rn Rn MR F MRB MR F MR B MR F MR B □ Rx * Ry ( S US U F I FR Rn Rn MRF MRB SAT MRF SAT M RB SAT MRF SAT M RB (SI ) (UI) (SF) (UF) Rn Rn MR F MRB RND MRF RND MRB RND MRF RND MRB (SF) (UF) MRF MRB = 0 MRxF MRxB = Rn Rn = xF MR MRxB

Table 7. Shifter and Shifter Immediate Compute Operations Table 8. Multifunction Compute Operations

Table 9. Multifunction Compute Operations Table 10. Interrupt Vector Addresses and Priorities

Table 10. Interrupt Vector Addresses and Priorities (Continued)

4153H–AERO–04/07

Electrical Characteristics

Recommended Operating Conditions ESD Sensitivity The TSC21020F features proprietary input protection circuitry to dissipate high-energy discharges (Human Body Model). Per method 3015 of M IL-STD-883, the TSC21020F has been classified as a Class 2 devices, with the ability to withstand up to 2000V ESD. Prosper ESD precautions are strongly recommended to avoid functional damage or per- formance degradation. Charges readily accumulate on the human body and test equipment and discharge without detection. Unused d evices must be stored in conduc- tive foam or shunts, and the foam should be discharged to the destination socket before devices are removed. DC Parameters *Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent dam- age to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameter Mil Range Unit Min Max V DD Supply Voltage 4.50 5.50 V TAMB Ambient Operating Temperature -55 +125 °C Parameter Test Conditions Min Max Unit V IH Hi-Level Input Voltage 1 VDD = max 2.0 V VIHCR Hi-Level Input Voltage 2, 12 VDD = max 3.0 V VIL Lo-Level Input Voltage 1, 12 VDD = min 0.8 V VILC Lo-Level Input Voltage 2 VDD = min 0.6 V VOH Hi-Level Output Voltage 3, 11 VDD = min, I OH = -1.0 mA 2.4 V VOL Lo-Level Output Voltage 3, 11 VDD = min, I OL = 4.0 mA 0.4 V IIH Hi-Level Input Current 4, 5 VDD = max, V IN = V DD max 10 µ A IIL Lo-Level Input Current 4 VDD = max, V IN = 0V 10 µ A IILT Lo-Level Input Current 5 VDD = max, V IN = 0V 350 µ A IOZL Tristate Leakage Current 6 VDD = max, V IN = 0V 10 µ A IDDIN Supply Current (Internal) 7 tCK = 50 ns, V DD = max, V IHCR = 3.0V, VIH = 2.4V, V IL = V ILC = 0.4V 430 mA

4153H–AERO–04/07 AC Parameters See Figure 15 for voltage reference levels. Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addi- tion or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variat ions and worst cases. Consequently, you cannot meaningfully add parameters to derive other specifications. IDDIDLE Supply Current (Idle) 8 VDD = max, V IN = 0V or V DD max 150 mA CIN Input Capacitance 9, 10 fIN = 1 MHz, T CASE = 25 5C, V IN = 2.5V 10 pF Notes: 1. Applies to: PMD47-0, PMACK, PMTS, DMD39-0, DMACK, DMTS, IRQ3-0, FLAG3-0, BR, TMS, TDI. 2. Applies to: CLKIN, TCK. 3. Applies to: PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE, DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR, DMPAGE, FLAG3-0, TIMEXP, BG. 4. Applies to: PMACK, PMTS, DMACK, DMTS, IRQ3-0, BR, CLKIN, RESET, TCK. 5. Applies to: TMS, TDI, TRST. 6. Applies to: PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE, DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR, DMPAGE, FLAG3-0, TDO. 7. Applies to IVDD pins. At t CK = 50ns, I DDIN (typical) = 350 mA. See "Power Dissipation" for ca lculation of external (EVDD) supply current for total supply current. 8. Applies to IVDD pins. Idle refers to TSC21020F st ate of operation during execution of the IDLE instruction. 9. Guaranteed but not tested. 10. Applies to all signal pins. 11. Although specified for TTL outputs, all TSC21020F outputs are CMOS-compatible and will drive to V DD and GND assuming no dc loads. 12. Applies to RESET, TRST. Parameter Test Conditions Min Max Unit

Figure 3. Clock

20 MHz

Applies after the power-up sequence is complete. At power up, the Internal Phase

ing stable V DD and CLKIN (not including clock oscillator start-up time).

Specification only applies in cases where multipl e TSC21020F processors are

ADSP-21020 User's Manual from Analog Devices for reset sequence information.

Figure 7. Flags

Flag inputs meeting these setup and hold times wi ll affect conditional operations in

21020 User's Manual from Analog Devices for additional flag servicing information.

Figure 8. Bus Request/Bus Grant DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR, DMPAGE. Buses are not granted until completion of current memory access. Analog Devices for BG, BR cycle relationships.

Figure 9. External Memory Three-State Control

0 DT/4 ns

XTS should only be asserted (low) during an active memory access cycle. DMA31-0, DMD39-0, DMS3-0 , DMRD , DMWR , DMPAGE.

4153H–AERO–04/07 Memory Read Parameter 20 MHz Frequency Dependency (1) Unit Min Max Min Max tDAD Address, Select to Data Valid 37 37 + DT ns tDRLD xRD Low to Data Valid 24 24 + 5DT/8 ns tHDA Data Hold from Address, Select 0 ns tHDRH Data Hold from xRD High -1 ns tDAAK xACK Delay from Address 27 27 + 7DT/8 ns tDRAK xACK Delay from xRD Low 15 15 + DT/2 ns tSAK xACK Setup before CLKIN High 14 14 + DT/4 ns tHAK xACK Hold after CLKIN High 0 ns tDARL Address, Select to xRD Low 8 8 + 3DT/8 ns tDAP xPAGE Delay from Address, Select 1 ns tDCKRL CLKIN High to xRD Low 16 26 16 + DT/4 26 + DT/4 ns tRW xRD Pulse Width 26 26 + 5DT/8 ns tRWR xRD High to xRD , xWR Low 17 17 + 3DT/8 ns Notes: 1. DT = t CK - 50 ns 2. x = PM or DM; Address = PMA23-0, DMA31-0; Data = PMD47-0, DMD39-0; Select = PMS1-0 , DMS3-0 .

Figure 10. Memory Read

Figure 11. Memory Write

0 DT/16 ns

See "System Hold Time Calculation" in "Test Condi tions" section for calculating hold

times given capacitive and DC loads. , DMS3-0 ; guaranteed by design.

Figure 12. IEEE 1149.1 Test Access Port IRQ3-0 , RESET , FLAG3-0, BR . DMA31-0, DMS3-0 , DMRD , DMWR , DMPAGE, FLAG3-0, BG , TIMEXP. from Analog Devices for further detail.

Figure 13. Output Enable/Disable age. t DECAY is calculated with ∆ V equal to 0.5V, and test loads C L and I L. value is that of the first pin to start driving.

4153H–AERO–04/07 4) their voltage swing (V DD ). It is calculated by: P EXT = O x C x V DD 2 x f The load capacitance should include the processor's package capacitance (C IN ). The switching frequency includes driving the load high and then back low. Address and data pins can drive high and low at a maximum rate of 1/ (2t CK ). The write strobes can switch every cycle at a frequency of 1/tCK. Select pins sw itch at 1/(2t CK ), but 2 DM and 2 PM selects can switch on each cycle. If only one bank is accessed, no select line will switch. For instance, the maximum power dissipation will be: PINT Max = I DDINMax x V DD Max = 0,430 x 5,5 = 2,36W PEXT Max = 0 x C x V DD Max 2 x f = 164 x 10 -11 x 5.5 2 x 20.10 6 = 0.99W Pmax = 3.4W Power and Ground Guidelines To achieve its fast cycle time, including instructi on fetch, data access, and execution, the TSC21020F is designed with high speed drivers o n all output pins. Large peak cur- rents may pass through a circuit board's ground and power lines, especially when many output drivers are simultaneously charging or disch arging their load capacitances. These transient currents can cause disturbances on the power and ground lines. To minimize these effects, the TSC21020F provides sepa rate supply pins for its internal logic (IGND and IVDD) and for its external drivers (EGND and EVDD). All GND pins should have a low impedance path to gr ound. A ground plane is required in TSC21020F systems to reduce this impedance, minimizing noise. The EVDD and IVDD pins should be bypassed to the ground plane using approximately 14 high-frequency capacitors (0.1 µ F ceramic). Keep each capacitor's lead and trace length to the pins as short as possible. This low inductive path provides the TSC21020F with the peak currents required when its output dri vers switch. The capacitors' ground leads should also be short and connect directly to the ground plane. This provides a low impedance return path for the load capacitance of the TSC21020F's output drivers. If a V DD plane is not used, the following recommendations a pply. Traces from the + 5V supply to the 10 EVDD pins should be designed to sa tisfy the minimum V DD specifica- tion while carrying average dc currents of [I DDEX /10 x (number of EVDD pins per trace)]. IDDEX is the calculated external supply current. A simil ar calculation should be made for the four IVDD pins using the I DDIN specification. The traces connecting +5V to the IV DD pins should be separate from those connecting to the EVDD pins. Pin Type # Pins % Switch xC xf xV DD

2 PEXT

5 MHz

10 MHz

0.064W 0.000W 0.017W 0.036W 0.045W 0.000W 0.012W 0.036W P EXT = 0.210W

4153H–AERO–04/07 The tip of the pins must be at least 0.10 inch higher than the tallest component under the probe to allow clearance for the bottom of the prob e. Pin strip headers are available from vendors such as 3M, McKenzie, and Samtec. The length of the traces between the EZ-ICE probe c onnector and the TSC21020F test access port pins should be less than 1 inch. Note t hat the EZ-ICE probe adds two TTL loads to the CLKIN pin of the TSC21020F. The BMTS, BTCK, BTRST, and BTDI signals are provide d so that the test access port can also be used for board-level testing. When the connector is not being used for emu- lation, place jumpers between the BXXX pins and the XXX pins as shown in Figure 20. If you are not going to use the test access port for board test, tie BTRST to GND and tie or pull up BTCK to VDD. The TRST pin must be asserted (pulsed low) after power up (through BTRST on the connector) or held low for proper operation of the TSC21020F.

4153H–AERO–04/07

Ordering Information

223-pin Ceramic Pin Grid Array Part Number Temperature Range Speed Package Quality Flo w TSC21020F-20MA-E 25 °C 20 MHz PGA223 Engineering Samples TSC21020F-20MB-E 25 °C 20 MHz MQFP-F256 Engineering Samples 5962-9953901QXC -55 to +125 °C 20 MHz MQFP-F256 QML-Q 5962-9953901VXC -55 to +125 °C 20 MHz MQFP-F256 QML-V 951200201 -55 to +125 °C 20 MHz MQFP-F256 ESCC TSC21020F-20MC-E 25 °C 20 MHz DIE Engineering Samples TSC21020F-20MC-SV -55 to +125 °C 20 MHz DIE QML-V Bottom View Symbol MM Inches Min. Max Min. Max A 2.54 3.30 .100 .130

4153H–AERO–04/07 256-pin MQFP-F Package Top View C 2.54 BSC .100 BSC D 46.74 47.75 1.840 1.880 E 46.74 47.75 1.840 1.880 H 0.41 0.51 0.16 0.20 L 3.05 3.56 .120 .140 Q 1.14 1.40 0.45 .055 Symbol Mils MM Min. Max Min. Max A 0.095 0.125 2.41 3.18 C 0.004 0.008 0.10 0.20 D 2.095 2.195 53.23 55.74 D 1 1.450 1.470 36.83 37.34 E 2.095 2.195 53.23 55.74 E1 1.450 1.470 36.83 37.34 e 0.020 BSC 0.508 BSC f 0.006 0.010 0.15 0.25 A1 0.081 0.101 2.06 2.56 A2 0.002 0.014 0.05 0.36 L 0.323 0.362 8.20 9.20 N1 64 64

4153H–AERO–04/07 N2 64 64

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Product Information

951200201 specifications and overview.

Summary

Rad. Hard 32/40-bit IEEE Floating Point DSP

Description

Rad. Hard 32/40-bit IEEE Floating Point DSP

Source title 951200201 Datasheet(PDF) - ATMEL Corporation

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