M65608E_09 ATMEL | Alldatasheet
Document overview
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Technical content
Features
- Operating Voltage: 5V
- Access Time: 30, 45 ns
- Very Low Power Consumption – Active: 600 mW (Max) – Standby: 1 µW (Typ)
- Wide Temperature Range: -55⋅C to +125⋅C
- 400 Mils Width Packages: FP32 and SB32
- TTL Compatible Inputs and Outputs
- Asynchronous
- No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2
- Tested up to a Total Dose of 30 krads (Si) according to MIL STD 883 Method 1019
- QML Q and V with SMD 5962-89598
- ESCC with Specification 9301/047
Description
The M65608E is a very low power CMOS static RAM organized as 131072 x 8 bits. Utilizing an array of six transistors (6 T) memory cells, the M65608E combines an extremely low standby supply current (Typic al value = 0.2 µA) with a fast access time at 30 ns over the full military temperature range. The high stability of the 6T cell pro- vides excellent protection against soft errors due to noise. The M65608E is processed according to the me thods of the latest revision of the MIL PRF 38535 or ESCC 9000. Rad. Tolerant 128Kx8, 5-Volt Very Low Power CMOS SRAM M65608E
4151N–AERO–04/09 M65608E Block Diagram Pin Configuration 32-lead DIL side-brazed 400 MILS 32-lead Flatpack 400 MILS
Table 1. Pin Names Table 2. Truth Table Note: L = low, H = high, X = H or L, Z = high impedance.
4151N–AERO–04/09 M65608E
Electrical Characteristics
Note: 1. Guaranteed but not tested. (MIL STD 883D method 3015.3) *NOTE: Stresses beyond those listed under "Abso- lute Maximum Ratings” may cause perma- nent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure between recommended DC operating and absolute maximum rating conditions for extended periods may affect device reliability. Operating Voltage Operating Temperature 5V + 10% -55 ⋅C to + 125⋅C Parameter Description Mini mum Typical Maximum Unit VCC Supply voltage 4.5 5.0 5.5 V GND Ground 0.0 0.0 0.0 V VIL Input low voltage GND - 0.5 0.0 0.8 V VIH Input high voltage 2.2 – VCC + 0.5 V Parameter Description Mini mum Typical Maximum Unit Cin(1) Input low voltage ––8 p F Cout(1) Output high voltage ––8 p F
Table 3. DC Test Conditions
- GND < Vin < VCC, GND < Vout < VCC Output Disabled.
- CS1 > VIH or CS2 < VIL and CS1 < VIL.
- F = 1/TAVAV, Iout = 0 mA, W = OE = VIH, Vin = GND or VCC, VCC max.
4151N–AERO–04/09 M65608E AC Parameters AC Test Conditions AC Test Loads Waveforms Data Retention Mode Atmel CMOS RAM’s are designed with battery backup in mind. Data retention voltage and sup- ply current are guaranteed over temperature. The following rules ensure data retention: 1. During data retent ion chip select CS1 must be held high within VCC to VCC -0.2V or, chip select CS2 must be held down within GND to GND +0.2V. 2. Output Enable (OE ) should be held high to keep the RAM outputs high impedance, mini- mizing power dissipation. 3. During power up and power-down transitions CS1 and OE must be kept between VCC + 0.3V and 70% of VCC, or with CS2 between GND and GND -0.3V. 4. The RAM can begin operation > TR ns after VCC reaches the minimum operation volt- ages (4.5V). Timing Output loading IOL/IOH (see Figure 1 and Figure 2)+30 pF Figure 1 Figure 2 Figure 3
4151N–AERO–04/09 M65608E Data Retention Characteristics Notes: 1. TAVAV = Read Cycle Time 2. CS1 = VCC or CS2 = CS1 = GND, Vin = GND/VCC, this parameter is only tested at VCC = 2V. 3. Parameters guaranteed but not tested Write Cycle Note: 1. Parameters guaranteed, not te sted, with output loading 5 pF. Parameter Description Minimum Typical TA = 25 ⋅C Maximum Unit VCCDR VCC for data retention 2.0 – – V TCDR Chip deselect to data retention time 0.0 – – ns TR Operation recovery time TAVAV(1) –– n s ICCDR1 Data retention current at 2.0V –0 . 1 1 5 0 µ A ICCDR2(2) Data retention current at 3.0V –0 . 2 2 0 0 µ A Symbol Parameter 65608-30 65608-45 Unit Value TAVAW Write cycle time 30 45 ns min TAVWL Address set-up time 00 n sm i n TAVWH Address valid to end of write 22 35 ns min TDVWH Data set-up time 18 20 ns min TE1LWH CS1 low to write end 22 35 ns min TE2HWH CS2 high to write end 22 35 ns min TWLQZ Write low to high Z (1) 81 5 n s m a x TWLWH Write pulse width 22 35 ns min TWHAX Address hold from to end of write 00 n sm i n TWHDX Data hold time 00 n sm i n TWHQX Write high to low Z (1) 00 n sm i n
4151N–AERO–04/09 M65608E Read Cycle Note: 1. Parameters Guaranteed, not tested, with output loading 5 pF. Symbol Parameter 65608-30 65608-45 Unit Value TAVAV Read cycle time 30 45 ns min TAVQV Address access time 30 45 ns max TAVQX Address valid to low Z (1) 55 n s m i n TE1LQV Chip-select1 access time 30 45 ns max TE1LQX CS1 low to low Z (1) 33 n s m i n TE1HQZ CS1 high to high Z (1) 15 20 ns max TE2HQV Chip-select2 access time 30 45 ns max TE2HQX CS2 high to low Z (1) 33 n s m i n TE2LQZ CS2 low to high Z (1) 15 20 ns max TGLQV Output Enable access time 12 15 ns max TGLQX OE low to low Z (1) 00 n s m i n TGHQZ OE high to high Z (1) 81 5 n s m a x
4151N–AERO–04/09 M65608E Write Cycle 1 WE Controlled, OE High During Write Write Cycle 2 WE Controlled, OE Low
4151N–AERO–04/09 M65608E Write Cycle 3 CS1 or CS2, Controlled Note: The internal write time of the me mory is defined by the overlap of CS1 Low and CS2 HIGH and W LOW. Both signals must be actived to initiate a write and either signal can terminate a write by going in actived. The data input setup and hold timing should be referenced to the actived edge of the signal that terminates the write. Data out is high impedance if OE = VIH.
4151N–AERO–04/09 M65608E Read Cycle 1 Read Cycle 2 Read Cycle 3
4151N–AERO–04/09 M65608E
Ordering Information
Note: 1. Contact Atmel for availability. Part Number Temperature Range Speed Package Flow MMC9-65608EV-30-E(1) 25⋅C 30 ns SB32.4 Engineering Samples MMDJ-65608EV-30-E 25⋅C 30 ns FP32.4 Engineering Samples 5962-8959847QZC -55⋅ to +125⋅C 30 ns SB32.4 QML Q 5962-8959847QTC -55⋅ to +125⋅C 30 ns FP32.4 QML Q 5962-8959818QZC -55⋅ to +125⋅C 45 ns SB32.4 QML Q 5962-8959818QTC -55⋅ to +125⋅C 45 ns FP32.4 QML Q 5962-8959847VZC -55⋅ to +125⋅C 30 ns SB32.4 QML V 5962-8959847VTC -55⋅ to +125⋅C 30 ns FP32.4 QML V 5962-8959818VZC -55⋅ to +125⋅C 45 ns SB32.4 QML V 5962-8959818VTC -55⋅ to +125⋅C 45 ns FP32.4 QML V 930104703 -55⋅ to +125⋅C 30 ns SB32.4 ESCC 930104704 -55⋅ to +125⋅C 30 ns FP32.4 ESCC 930104701 -55⋅ to +125⋅C 45 ns SB32.4 ESCC 930104702 -55⋅ to +125⋅C1 45 ns FP32.4 ESCC MM065608EV-30-E 25⋅C 30 ns Die Engineering Samples 5962-8959847V6A -55⋅ to +125⋅C 30 ns Die QML V
4151N–AERO–04/09 M65608E Package Drawings 32-lead Flat Pack 400 Mils
4151N–AERO–04/09 M65608E Package Drawings 32-lead Side Braze 400 Mils
4151N–AERO–04/09 M65608E Document Revision History Changes from Rev. L to Rev. M 1. Change in “Consumption” on page 5. ICCOP. Changes from Rev. M to Rev. N 1. Update of footnotes under “Data Retention Characteristics” table 2. Update of Absolute Maximum Ratings section
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