9240LP MAXWELL | Alldatasheet
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All data sheets are subject to change without notice (858) 503-3300- Fax: (858) 503-3301- www.maxwell.com 14-Bit, 10 MSPS Monolithic A/D 9240LP ©2005 Maxwell Technologies All rights reserved.
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FEATURES:
- R AD-PAK® radiation-hardened against natural space radiation Low power dissipation: 295 mW Single 5 V supply Integral nonlinearity error: 2.5 LSB Differential nonlinearity error: 0.6 LSB Input referred noise: 0.36 LSB Complete: On-chip sample-and-hold amplifier and voltage reference Signal-to-noise and distortion ration: 77.5 dB Spurious-free dynamic range: 90 dB Out-of-range indicator Straight binary output data Total dose hardened to 100 Krads (Si), dependent on orbit and mission duration Single Event Latchup (SEL) protected DESCRIPTION: Maxwell Technologies’ 9240LP is a 14-bit, analog-to-digital converter that operates at a 10 MSPS rate. Manufactured with a high speed CMOS process, this ADC contains an on-chip, high performance, low noise, sample-and-hold amplifier and programmable voltage reference. The 9240LP offers single supply operation and dissipates only 295 mW with a 5 volt supply. This device provides no missing codes and excellent temperature drift performance over the full operating temperature range. The 9240LP utilizes Maxwell’s LPT™ Latchup Protection Circuit.Maxwell Technologies' patented R AD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while provid- ing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, R AD-PAK® provides protection to 100 krad (Si) radiation dose tolerance. This product is avail- able with screening up to Maxwell Technologies self-defined Class K. BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 4 BIT 5 BIT 3NC BIAS CAPB CAPT NC CML LPTref VinA VinB LPTDVDD LPTAVDD DVSS AVSS DVDD AVDD NC DRVDD CLK LPTSTATUS LPTBIT NC BIT 14 REFCOM Vref SENSE NC AVSS AVDD NC NC OTC BIT 1 BIT 2 9240LP 9240LP BLOCK DIAGRAM DVDD DRVDD VINA VINB VREF LPTVREF LPTBIT AVDD LPTAVDD LPTDVDD LPTDRVDD LPTVINA LPTVINB LPTVREF LPTSTATUS CROW BAR AVDD DVDD DRVDD VINA VINB VREF CURRENT SENSE 9240 14 Bit A/D Data OutputsControl Signals
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TABLE 1. 9240LP PIN DESCRIPTION
1 DVSS Digital Ground
3 DVDD 5V Digital Supply
5 NC No Connect
6 DRVDD Digital Output Driver Supply
7 CLK Clock Input Pin
8 LPTSTATUS A 0 to 5V square-wave is output during the deci-
sion time and protect time. Normally low.
9 LPTBIT The LPT circuit will crowbar the power supplies
to the 9240 for as long as a logic high is applied. logical low or ground is applied to this input.
10 NC No Connect
11 BIT 14 Least Significant Data Bit (LSB)
24 BIT 1 Most Significant Data Bits (MSB)
25 OTR Out of Range
31 SENSE Reference Select
32 VREF Reference I/O
33 REFCOM Reference Common
35 BIAS
- See Speed/Power programmability section.
36 CAPB Noise Reduction Pin
37 CAPT Noise Reduction Pin
39 CML Common-Mod Level (Midsupply)
40 LPTVREF Protected Reference I/O
41 VINA Analog Input Pin (+)
42 VINB Analog Input Pin (-)
43 LPTDVDD Protected 5V Digital Supply
44 LPTAVDD Protected 5V Analog Supply
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TABLE 2. 9240LP ABSOLUTE MAXIMUM RATINGS 1
- Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
of this specification are not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability.
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TABLE 3. 9240LP DC SPECIFICATIONS
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- Tested using external V REF with servo control
- Including internal reference
- Excluding internal reference
- Load regulkation with 1 mA load current
TABLE 3. 9240LP DC SPECIFICATIONS
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TABLE 4. 9240LP AC SPECIFICATIONS TABLE 5. 9240LP DIGITAL SPECIFICATIONS
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- Due to the voltage drop across the LPT circuiry the CLOCK signal must be no greater than A VDD - 0.5V
TABLE 6. 9240LP SWITCHING CHARACTERISTICS1 TABLE 5. 9240LP DIGITAL SPECIFICATIONS
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FIGURE 1. TIMING DIAGRAM
14 BIT
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FIGURE 2. SINAD VS. INPUT FREQUENCY (INPUT SPACE = 2V, VCM = 2.5V) FIGURE 3. THD VS. INPUT FREQUENCY (INPUT SPAN = 5V, VCM = 2.5V)
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FIGURE 4. TYPICAL FFT, fIN = 1.0 MHZ (INPUT SPACE = 5V, VCM = 2.5V) FIGURE 5. SINAD VS. INPUT FREQUENCY (INPUT SPAN = 2V, VCM = 2.5V) FIGURE 6. THD VS. INPUT FREQUENCY (INPUT SPAN = 2V, VCM = 2.5V)
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FIGURE 7. TYPICAL FFT, fIN = 5.0 MHZ (INPUT SPAN = 2 V, VCM = 2.5 V) FIGURE 9. SINGLE TONE SFDR (fIN = 5.0 MHZ, VCM = 2.5 V)
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FIGURE 10. DUAL TONE SFDR (F1 = 0.95 MHZ, F2 = 1.04 MHZ, VCM = 2.5 V) FIGURE 11. TYPICAL INL (INPUT SPAN = 5 V) FIGURE 12. TYPICAL DNL (INPUT SPAN = 5 V)
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FIGURE 13. “GROUNDED-INPUT” HISTOGRAM (INPUT SPAN = 5 V) FIGURE 14. SINAD VS. INPUT FREQUENCY (INPUT SPAN = 2 V, VCM = 2.5V)
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FIGURE 15. THD VS. INPUT FREQUENCY (INPUT SPAN = 5 V, VCM = 2.5 V) FIGURE 16. CMR VS. INPUT FREQUENCY (INPUT SPAN = 2 V, VCM = 2.5 V)
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FIGURE 17. SINAD VS. INPUT FREQUENCY (INPUT SPAN = 5 V, VCM = 2.5 V) FIGURE 18. THD VS. INPUT FREQUENCY (INPUT SPAN = 5 V, VCM = 2.5 V)
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FIGURE 19. TYPICAL VOLTAGE REFERENCE ERROR VS. TEMPERATURE
44 PIN RAD-PAK® QUAD FLAT PACKAGE
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©2005 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC 9240LP Note: All dimensions in inches Important Notice: These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech- nologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts. D1 0.500 BSC e 0.050 BSC S1 0.005 0.067 -- L 0.260 0.270 0.280 Q 0.020 0.025 0.030 N4 4
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©2005 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC 9240LP Product Ordering Options Model Number Feature Option Details9240LP RP Q X Screening Flow Package Radiation Feature Base Product Nomenclature MCM1 K= Maxwell Self-Defined Class K H= Maxwell Self-Defined Class H I = Industrial (testing @ -55°C, +25°C, +125°C) E = Engineering (testing @ +25°C) Q = Quad Flat Pack RP = R AD-PAK® package 14-Bit, 10MSPS A/D Converter with LPT ASIC 1) Products manufactured and screened to Maxwell Technologies self-defined Calss H and Class K flows.