90S8535

AT90S4434 ATMEL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 10

Technical content

Features

• Utilizes the AVR ® Enhanced RISC Architecture
• AVR - High Performance and Low Power RISC Architecture
• 118 Powerful Instructions - Most Single Clock Cycle Execution
• 8K bytes of In-System Programmable Flash AT90S/LS8535 4K bytes of In-System Programmable Flash AT90S/LS4434 – SPI Serial Interface for In-System Programming – Endurance: 1,000 Write/Erase Cycles
• 512 bytes EEPROM AT90S/LS8535 256 bytes EEPROM AT90S/LS4434 – Endurance: 100,000 Write/Erase Cycles
• 512 bytes Internal SRAM AT90S/LS8535 256 bytes Internal SRAM AT90S/LS4434
• 8-Channel, 10-Bit ADC
• 32 x 8 General Purpose Working Registers
• 32 Programmable I/O Lines
• Programmable Serial UART
• VCC : 4.0 - 6.0V AT90S4434/AT90S8535
• VCC : 2.7 - 6.0V AT90LS4434/AT90LS8535
• Speed Grades: 0 - 8 MHz AT90S4434/AT90S8535, 0 - 4 MHz (AT90LS4434/AT90LS8535
• Power-On Reset Circuit
• Up to 8 MIPS Throughput at 8 MHz
• RTC with Separate Oscillator and Counter Mode
• Two 8-Bit Timer/Counters with Separate Prescaler and Compare Mode
• One 16-Bit Timer/Counter with Separate Prescaler and Compare and Capture Modes
• 3 PWM channels
• External and Internal Interrupt Sources
• Programmable Watchdog Timer with On-Chip Oscillator
• On-Chip Analog Comparator
• Three Sleep Modes: Idle, Power Save, and Power Down
• Programming Lock for Software Security

Description

The AT90S4434/8535 is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S4434/8535 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Rev. 1041AS–05/98 8-Bit Microcontroller with 4K/8K Bytes In-System Programmable Flash AT90S4434 AT90LS4434 AT90S8535 AT90LS8535 Advance Information Pin Configurations (continued) Note: This is a summary document. For the complete 80 page document, please visit our website at www.atmel.com or e-mail at literature@atmel.com and request literature #1041A.

AT90S/LS4434 and AT90S/LS85352 Block Diagram The AVR core combines a rich instruction set with 32 gen- eral purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving through- puts up to ten times faster than conventional CISC micro- controllers. The AT90S4434/8535 provides the following features: 4K/8K bytes of In-System Programmable Flash, 256/512 bytes EEPROM, 256/512 bytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, RTC, three flexible timer/counters with compare modes, internal and external interrupts, a programmable serial UART, 8-chan- nel, 10-bit ADC, programmable Watchdog Timer with inter- nal oscillator, an SPI serial port and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, timer/counters, SPI port and interrupt system to continue functioning. The Power Down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power Save mode, the timer oscillator continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The device is manufactured using Atmel’s high density non-volatile memory technology. The on-chip ISP Flash PROGRAM COUNTER INTERNAL OSCILLATOR WATCHDOG TIMER STACK POINTER PROGRAM FLASH MCU CONTROL REGISTERSRAM GENERAL PURPOSE REGISTERS INSTRUCTION REGISTER TIMER/ COUNTERS INSTRUCTION DECODER DATA DIR. REG. PORTB DATA DIR. REG. PORTA DATA DIR. REG. PORTD DATA DIR. REG. PORTC DATA REGISTER PORTB DATA REGISTER PORTA ANALOG MUX ADC DATA REGISTER PORTD DATA REGISTER PORTC PROGRAMMING LOGIC TIMING AND CONTROL OSCILLATOR OSCILLATOR INTERRUPT UNIT EEPROM SPI UART STATUS REGISTER Z Y X ALU PORTB DRIVERS PORTA DRIVERS PORTD DRIVERS PORTC DRIVERS PB0 - PB7 PA0 - PA7 RESET VCC AVCC AGND AREF GND XTAL2 XTAL1 CONTROL LINES + - ANALOG COMPARATOR PD0 - PD7 PC0 - PC7 8-BIT DATA BUS

tion to many embedded control applications. in-circuit emulators, and evaluation kits. internal pull-up resistors are activated. current if the pull-up resistors are activated. of the AT90S4434/8535 as listed on page 52. current if the pull-up resistors are activated. of the AT90S4434/8535 as listed on page 59. the oscillator is running resets the device. internal clock operating circuit. should be externally connected to VCC via a low-pass filter. See page 47 for details on operation of the ADC. This is the analog reference input for the A/D Converter. must be applied to this pin. plane, this pin should be connected to this ground plane. unconnected while XTAL1 is driven as shown in Figure 2. should therefore be in the interval 0 Hz - 256 kHz. Table 1. Memory Size Summary

following those of the register file, $20 - $5F. gram memory is executed with a single level pipelining. enables instructions to be executed in every clock cycle. gram memory address contains a 16- or 32-bit instruction. accessible in the I/O space. Figure 4. Memory Maps

64 I/O Registers

AT90S4434/8535 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $3F ($5F) SREG I T H S V N Z C 21 $3E ($5E) SPH - - - - - - SP9 SP8 22 $3D ($5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 22 $3C ($5C) Reserved $3B ($5B) GIMSK INT1 INT0 - - - - - -2 8 $3A ($5A) GIFR INTF1 INTF0 28 $39 ($59) TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 -T O I E 0 2 9 $38 ($58) TIFR OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 -T O V 0 3 0 $37 ($57) Reserved $36 ($56) Reserved $35 ($55) MCUCR - SE SM1 SM0 ISC11 ISC10 ISC01 ISC00 31 $34 ($54) MCUSR - - - - - - EXTRF PORF 27 $33 ($53) TCCR0 - - - - - CS02 CS01 CS00 35 $32 ($52) TCNT0 Timer/Counter0 (8 Bits) 36 $31 ($51) Reserved $30 ($50) Reserved $2F ($4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 - -P W M 1 1 P W M 1 0 3 8 $2E ($4E) TCCR1B ICNC1 ICES1 - - CTC1 CS12 CS11 CS10 39 $2D ($4D) TCNT1H Timer/Counter1 - Counter Register High Byte 40 $2C ($4C) TCNT1L Timer/Counter1 - Counter Register Low Byte 40 $2B ($4B) OCR1AH Timer/Counter1 - Output Compare Register A High Byte 41 $2A ($4A) OCR1AL Timer/Counter1 - Output Compare Register A Low Byte 41 $29 ($49) OCR1BH Timer/Counter1 - Output Compare Register B High Byte 41 $28 ($48) OCR1BL Timer/Counter1 - Output Compare Register B Low Byte 41 $27 ($47) ICR1H Timer/Counter1 - Input Capture Register High Byte 41 $26 ($46) ICR1L Timer/Counter1 - Input Capture Register Low Byte 41 $25 ($45) TCCR2 - PWM2 COM21 COM20 CTC2 CS22 CS21 CS20 45 $24 ($44) TCNT2 Timer/Counter2 (8 Bits) 46 $23 ($43) OCR2 Timer/Counter2 Output Compare Register 46 $22 ($42) ASSR - - - - AS2 TCN2UB OCR2UB TCR2UB 48 $21 ($41) WDTCR - - - WDTOE WDE WDP2 WDP1 WDP0 50 $20 ($40) Reserved $1F ($3F) EEARH EEAR9 $1E ($3E) EEARL EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 51 $1D ($3D) EEDR EEPROM Data Register 51 $1C ($3C) EECR - - - - EERIE EEMWE EEWE EERE 52 $1B ($3B) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 70 $1A ($3A) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 70 $19 ($39) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 70 $18 ($38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 72 $17 ($37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 72 $16 ($36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 72 $15 ($35) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 78 $14 ($34) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 78 $13 ($33) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 78 $12 ($32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 81 $11 ($31) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 81 $10 ($30) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 81 $0F ($2F) SPDR SPI Data Register 57 $0E ($2E) SPSR SPIF WCOL - - - - - -5 6 $0D ($2D) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 56 $0C ($2C) UDR UART I/O Data Register 60 $0B ($2B) USR RXC TXC UDRE FE OR - - -6 0 $0A ($2A) UCR RXCIE TXCIE UDRIE RXEN TXEN CHR9 RXB8 TXB8 61 $09 ($29) UBRR UART Baud Rate Register $08 ($28) ACSR ACD - ACO ACI ACIE ACIC ACIS1 ACIS0 67 $07 ($27) ADMUX - - - - - MUX2 MUX1 MUX0 67 $06 ($26) ADCSR ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 67 $05 ($25) ADCH - - - - - - ADC9 ADC8 68 $04 ($24) ADCL ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 68 $03 ($20) Reserved $02 ($22) Reserved $01 ($21) Reserved $00 ($20) Reserved

AT90S/LS4434 and AT90S/LS8535 AT90S4434/8535 Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1 COM Rd One’s Complement Rd ← $FF − Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd ← $00 − Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • ($FF - K) Z,N,V 1 INC Rd Increment Rd ← Rd + 1 Z,N,V 1 DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1 SER Rd Set Register Rd ← $FF None 1 BRANCH INSTRUCTIONS RJMP k Relative Jump PC ← PC + k + 1 None 2 IJMP Indirect Jump to (Z) PC ← Z None 2 RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3 ICALL Indirect Call to (Z) PC ← ZN o n e 3 RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I 4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1 / 2 CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1 / 2 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1 / 2 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1 / 2 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1 / 2 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ← PC+k + 1 None 1 / 2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ← PC+k + 1 None 1 / 2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1 / 2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1 / 2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1 / 2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1 / 2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1 / 2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1 / 2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1 / 2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1 / 2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1 / 2 BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1 / 2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1 / 2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1 / 2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1 / 2 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1 / 2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1 / 2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1 / 2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1 / 2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1 / 2

AT90S/LS4434 and AT90S/LS85358 Mnemonics Operands Description Operation Flags #Clocks DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers Rd ← Rr None 1 LDI Rd, K Load Immediate Rd ← KN o n e 1 LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2 LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd ← (k) None 2 ST X, Rr Store Indirect (X) ← Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2 ST Y, Rr Store Indirect (Y) ← Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2 ST Z, Rr Store Indirect (Z) ← Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2 STS k, Rr Store Direct to SRAM (k) ← Rr None 2 LPM Load Program Memory R0 ← (Z) None 3 IN Rd, P In Port Rd ← PN o n e 1 OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1N o n e 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0N o n e 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0) ← C,Rd(n+1)← Rd(n),C← Rd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7) ← C,Rd(n)← Rd(n+1),C← Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 BSET s Flag Set SREG(s) ← 1 SREG(s) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) ← TN o n e 1 SEC Set Carry C ← 1C 1 CLC Clear Carry C ← 0 C 1 SEN Set Negative Flag N ← 1N 1 CLN Clear Negative Flag N ← 0 N 1 SEZ Set Zero Flag Z ← 1Z 1 CLZ Clear Zero Flag Z ← 0 Z 1 SEI Global Interrupt Enable I ← 1I 1 CLI Global Interrupt Disable I ← 0 I 1 SES Set Signed Test Flag S ← 1S 1 CLS Clear Signed Test Flag S ← 0 S 1 SEV Set Twos Complement Overflow. V ← 1V 1 CLV Clear Twos Complement Overflow V ← 0 V 1 SET Set T in SREG T ← 1T 1 CLT Clear T in SREG T ← 0 T 1 SEH Set Half Carry Flag in SREG H ← 1H 1 CLH Clear Half Carry Flag in SREG H ← 0 H 1 NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 3 WDR Watchdog Reset (see specific descr. for WDR/timer) None 1

AT90S/LS4434 and AT90S/LS8535

Ordering Information

Power Supply Speed (MHz) Ordering Code Package Operation Range 2.7 - 6.0V 4 A T90LS4434-4AC A T90LS4434-4JC A T90LS4434-4PC 44A 44J 40P6 Commercial (0°C to 70°C) A T90LS4434-4AI A T90LS4434-4JI A T90LS4434-4PI 44A 44J 40P6 Industrial (-40 °C to 85°C) 4.0 - 6.0V 8 A T90S4434-8AC A T90S4434-8JC A T90S4434-8JC 44A 44J 40P6 Commercial (0°C to 70°C) A T90S4434-8AI A T90S4434-8JI A T90S4434-8PI 44A 44J 40P6 Industrial (-40°C to 85°C) 2.7 - 6.0V 4 A T90LS8535-4AC A T90LS8535-4JC A T90LS8535-4PC 44A 44J 40P6 Commercial °C to 70°C) A T90LS8535-4AI A T90LS8535-4JI A T90LS8535-4PI 44A 44J 40P6 Industrial (-40°C to 85°C) 4.0 - 6.0V 8 A T90S8535-8AC A T90S8535-8JC A T90S8535-8JC 44A 44J 40P6 Commercial (0°C to 70°C) A T90S8535-8AI A T90S8535-8JI A T90S8535-8PI 44A 44J 40P6 Industrial (-40 °C to 85°C) Package Type 44A 44 Lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 44J 44 Lead, Plastic J-Leaded Chip Carrier (PLCC) 40P6 40 Lead, 0.600" Wide, Plastic Dual in Line Package (PDIP)

AT90S/LS4434 and AT90S/LS8535 *Controlling dimension: millimeters .045(1.14) X 45° PIN NO. 1 IDENTIFY .008(.203) .021(.533) .013(.330) .630(16.0) .590(15.0) .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .500(12.7) REF SQ .032(.813) .026(.660) .050(1.27) TYP .656(16.7) .650(16.5) .695(17.7) .685(17.4)SQ SQ 2.07(52.6) 2.04(51.8) PIN .566(14.4) .530(13.5) .090(2.29) MAX .005(.127) MIN .065(1.65) .015(.381) .022(.559) .041(1.04)

15 REF

.690(17.5) .610(15.5) .630(16.0) .590(15.0) .012(.305) .008(.203) .110(2.79) .090(2.29) .161(4.09) .125(3.18) SEATING PLANE .220(5.59) MAX 1.900(48.26) REF 44A, 44-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) Dimensions in Millimeters and (Inches) 44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) 40P6, 40-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-011 AC