90S1200

AT90S1200 ATMEL | Alldatasheet

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Technical content

Features

• Utilizes the AVR® RISC Architecture  AVR – High-performance and Low-power RISC Architecture – 89 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Up to 12 MIPS Throughput at 12 MHz  Data and Non-volatile Program Memory – 1K Byte of In-System Programmable Flash Endurance: 1,000 Write/Erase Cycles – 64 Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles – Programming Lock for Flash Program and EEPROM Data Security  Peripheral Features – One 8-bit Timer/Counter with Separate Prescaler – On-chip Analog Comparator – Programmable Watchdog Timer with On-chip Oscillator – SPI Serial Interface for In-System Programming  Special Microcontroller Features – Low-power Idle and Power-down Modes – External and Internal Interrupt Sources – Selectable On-chip RC Oscillator for Zero External Components  Specifications – Low-power, High-speed CMOS Process Technology – Fully Static Operation  Power Consumption at 4 MHz, 3V, 25°C – Active: 2.0 mA – Idle Mode: 0.4 mA – Power-down Mode: <1 µA  I/O and Packages – 15 Programmable I/O Lines – 20-pin PDIP, SOIC and SSOP  Operating Voltages  Speed Grades – 0 - 4 MHz, (AT90S1200-4) – 0 - 12 MHz, (AT90S1200-12) Pin Configuration 8-bit Microcontroller with 1K Byte of In-System Programmable Flash AT90S1200 Rev. 0838H–AVR–03/02

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0838H–AVR–03/02 Description The AT90S1200 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S1200 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with the 32 general purpose working reg- isters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. Block Diagram Figure 1. The AT90S1200 Block Diagram The architecture supports high-level languages efficiently as well as extremely dense assembler code programs. The AT90S1200 provides the following features: 1K byte of In-System Programmable Flash, 64 bytes EEPROM, 15 general purpose I/O lines, 32 general purpose working registers, internal and external interrupts, programmable watchdog timer with internal oscillator, an SPI serial port for program downloading and two software selectable power-saving modes. The Idle Mode stops the CPU while allow-

0838H–AVR–03/02 ing the Registers, Timer/Counter, Watchdog and Interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscilla- tor, disabling all other chip functions until the next External Interrupt or hardware Reset. The device is manufactured using Atmel ’s high-density nonvolatile memory technology. The On-chip In-System Programmable Flash allows the program memory to be repro- grammed in-system through an SPI serial interface or by a conventional nonvolatile memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Pro- grammable Flash on a monolithic chip, the Atmel AT90S1200 is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embed- ded control applications. The AT90S1200 AVR is supported with a full suite of program and system development tools including: macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. Pin Descriptions VCC Supply voltage pin. GND Ground pin. Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). PB0 and PB1 also serve as the positive input (AIN0) and the negative input (AIN1), respectively, of the On-chip Analog Comparator. The Port B out- put buffers can sink 20 mA and thus drive LED displays directly. When pins PB0 to PB7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not active. Port B also serves the functions of various special features of the AT90S1200 as listed on page 30. Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not active. Port D also serves the functions of various special features of the AT90S1200 as listed on page 34. RESET Reset input. A low level on this pin for more than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 2 . Either a quartz crystal or a ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3.

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Figure 2. Oscillator Connections connected as indicated in the figure. Figure 3. External Clock Drive Configuration programmed in Parallel Programming mode first.

Figure 4. The AT90S1200 AVR RISC Architecture tion is being executed, the next instruction is pre-fetched from the program memory. memory is In-System Programmable Flash memory. every program memory address contains a single 16-bit instruction.

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ory spaces in the AVR architecture are all linear and regular memory maps. vector position. The lower the interrupt vector address, the higher the priority. Figure 5 shows the structure of the 32 general purpose registers in the CPU. Figure 5. AVR CPU General Purpose Working Registers Register 30 also serves as an 8-bit pointer for indirect address of the register file. categories – arithmetic, logic and bit-functions. 512 x 16. The Flash memory has an endurance of at least 1000 write/erase cycles. See page 37 for a detailed description on Flash data downloading.

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Figure 10. Relative Program Memory Addressing subroutines and interrupts are executed. the data in the other stack levels 1 - 2 are popped one level in the stack. ues written to the stack are overwritten.

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I/O Memory The I/O space definition of the AT90S1200 is shown in the following table. Note: Reserved and unused locations are not shown in the table. tions. Refer to the instruction set chapter for more details. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Table 1. The AT90S1200 I/O Space

0838H–AVR–03/02 Status Register – SREG The AVR status register (SREG) at I/O space location $3F is defined as:  Bit 7 – I: Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled indepen- dent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.  Bit 6 – T: Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.  Bit 5 – H: Half-carry Flag The half-carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set description for detailed information.  Bit 4 – S: Sign Bit, S = N The S-bit is always an exclusive or between the negative flag N and the two ’s comple- ment overflow flag V. See the Instruction Set description for detailed information.  Bit 3 – V: Two’s Complement Overflow Flag The two’s complement overflow flag V supports two ’s complement arithmetics. See the Instruction Set description for detailed information.  Bit 2 – N: Negative Flag The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set description for detailed information.  Bit 1 – Z: Zero Flag The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set description for detailed information.  Bit 0 – C: Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set description for detailed information. Note that the status register is not automatically stored when entering an interrupt rou- tine and restored when returning from an interrupt routine. This must be handled by software. B i t 76543210 $3F I T H S V N Z C SREG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000

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together with the I-bit in the Status Register in order to enable the interrupt. Table 2. Reset and Interrupt Vectors

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Figure 15. MCU Start-up, RESET Controlled Externally Figure 16. External Reset during Operation TOUT. Refer to page 23 for details on operation of the Watchdog.

Figure 17. Watchdog Reset during Operation Mask Register) at I/O address $39. bit is set (one) when a Return from Interrupt instruction (RETI) is executed. bit position(s) to be cleared. flag is cleared by software. interrupt enable bit is set (one), and will be executed by order of priority. as long as the interrupt condition is active. This bit is a reserved bit in the AT90S1200 and always reads as zero.

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0838H–AVR–03/02  Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bit 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or low level sensed. INT0 can be activated even if the pin is configured as an output. See also page 17.  Bits 5..0 – Res: Reserved Bits These bits are reserved bits in the AT90S1200 and always read as zero. Timer/Counter Interrupt Mask Register – TIMSK  Bits 7..2 – Res: Reserved Bits These bits are reserved bits in the AT90S1200 and always read as zero.  Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $002) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).  Bit 0 – Res: Reserved Bit This bit is a reserved bit in the AT90S1200 and always reads as zero. Timer/Counter Interrupt FLAG Register – TIFR  Bits 7..2 – Res: Reserved Bits These bits are reserved bits in the AT90S1200 and always read as zero.  Bit 1 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.  Bit 0 – Res: Reserved Bit This bit is a reserved bit in the AT90S1200 and always reads as zero. Bit 7 6 5 4 3 2 1 0 $39 - - - - - - TOIE0 - TIMSK Read/Write R R R R R R R/W R Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Read/Write R R R R R R R/W R Initial Value 0 0 0 0 0 0 0 0

0838H–AVR–03/02 External Interrupts The External Interrupt is triggered by the INT0 pin. The interrupt can trigger on rising edge, falling edge or low level. This is set up as described in the specification for the MCU Control Register (MCUCR). When INT0 is level triggered, the interrupt is pending as long as INT0 is held low. The interrupt is triggered even if INT0 is configured as an output. This provides a way to generate a software interrupt. The interrupt flag can not be directly accessed by the user. If an external edge-triggered interrupt is suspected to be pending, the flag can be cleared as follows. 1. Disable the External Interrupt by clearing the INT0 flag in GIMSK. 2. Select level triggered interrupt. 3. Select desired interrupt edge. 4. Re-enable the external interrupt by setting INT0 in GIMSK. Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. Four clock cycles after the interrupt flag has been set, the program vector address for the actual interrupt handling routine is executed. During this 4-clock-cycle period, the Program Counter (9 bits) is pushed onto the Stack. The vector is normally a relative jump to the interrupt routine, and this jump takes two clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (9 bits) is popped back from the Stack and the I-flag in SREG is set. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Subroutine and Interrupt Stack is a 3-level true hardware stack, and if more than three nested subroutines and interrupts are executed, only the most recent three return addresses are stored.

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These bits are reserved bits in the AT90S1200 and always read as zero. execution of the SLEEP instruction. as sleep mode. For details, refer to the paragraph “Sleep Modes” on the following page. These bits are reserved bits in the AT90S1200 and always read as zero. external INT0 pin that activate the interrupt are defined in Table 4. interrupt request as long as the pin is held low. Table 4. Interrupt 0 Sense Control 0 0 The low level of INT0 generates an interrupt request.

01 R e s e r v e d

1 0 The falling edge of INT0 generates an interrupt request. 1 1 The rising edge of INT0 generates an interrupt request.

0838H–AVR–03/02 Sleep Modes To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruc- tion must be executed. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the register file and the I/O memory are unaltered. If a Reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Idle Mode When the SM bit is cleared (zero), the SLEEP instruction makes the MCU enter the Idle mode, stopping the CPU but allowing Timer/Counters, Watchdog and the interrupt sys- tem to continue operating. This enables the MCU to wake up from external triggered interrupts as well as internal ones like Timer Overflow interrupt and Watchdog Reset. If wakeup from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD-bit in the Analog Comparator Control and Sta- tus Register (ACSR). This will reduce power consumption in Idle mode. When the MCU wakes up from Idle mode, the CPU starts program execution immediately. Power-down Mode When the SM bit is set (one), the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the External Oscillator is stopped while the External Interrupts and the Watchdog (if enabled) continue operating. Only an External Reset, a Watchdog Reset (if enabled), an external level interrupt on INT0 can wake up the MCU. Note that when a level triggered interrupt is used for wake-up from Power-down, the low level must be held for a time longer than the reset delay time-out period t TOUT. Other- wise, the device will not wake up.

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Counter with an external pin connection, which triggers the counting. Figure 18 shows the general Timer/Counter0 prescaler. Figure 18. Timer/Counter0 Prescaler

Figure 19. Timer/Counter0 Block Diagram Timer/Counter0 are found in the Timer/Counter Interrupt Mask Register (TIMSK). These bits are reserved bits in the AT90S1200 and always read as zero.

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The Clock Select0 bits 2, 1 and 0 define the prescaling source of Timer/Counter0. configured as an output. This feature can give the user SW control of the counting. counting in the timer clock cycle following the write operation. Table 5. Clock 0 Prescale Select 0 0 0 Stop, the Timer/Counter0 is stopped.

001 C K

010 C K / 8

011 C K / 6 4

Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator that runs at 1 MHz. details on the Watchdog Reset, refer to page 14. Figure 20. Watchdog Timer These bits are reserved bits in the AT90S1200 and will always read as zero. (zero) the Watchdog Timer function is disabled.

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Characteristics” on page 51. Watchdog Timer may not start to count from zero. before changing the Watchdog Timer Prescale Select. Table 6. Watchdog Timer Prescale Select

0838H–AVR–03/02 EEPROM Read/Write Access The EEPROM access registers are accessible in the I/O space. The write access time is in the range of 2.5 - 4 ms, depending on the V CC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some precaution must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on Power- up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. CPU operation under these condi- tions is likely cause the program counter to perform unintentional jumps and eventually execute the EEPROM write code. To secure EEPROM integrity, the user is advised to use an external under-voltage reset circuit in this case. In order to prevent unintentional EEPROM writes, a specific write procedure must be fol- lowed. Refer to “EEPROM Control Register – EECR” on page 25 for details on this. When the EEPROM is read or written, the CPU is halted for two clock cycles before the next instruction is executed. EEPROM Address Register – EEAR  Bit 7, 6 – Res: Reserved Bits These bits are reserved bits in the AT90S1200 and will always read as zero.  Bits 5..0 – EEAR5..0: EEPROM Address The EEPROM Address Register (EEAR5..0) specifies the EEPROM address in the 64- byte EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 63. EEPROM Data Register – EEDR  Bits 7..0 – EEDR7..0: EEPROM Data For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read opera- tion, the EEDR contains the data read out from the EEPROM at the address given by EEAR. EEPROM Control Register – EECR  Bits 7..2 – Res: Reserved Bits These bits are reserved bits in the AT90S1200 and will always be read as zero. B i t 76543210 $1E –– EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEAR Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 B i t 76543210 $1D MSB LSB EEDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 B i t 76543210 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0

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0838H–AVR–03/02  Bit 1 – EEWE: EEPROM Write Enable The EEPROM Write Enable Signal (EEWE) is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. When the write access time (typically 2.5 ms at V CC = 5V and 4 ms at VCC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user soft- ware can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed.  Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal (EERE) is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruc- tion is executed. Caution: If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during EEPROM write operation to avoid these problems. Prevent EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply volt- age is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board-level systems using the EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low. EEPROM data corruption can easily be avoided by following these design recommen- dations (one is sufficient): 1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This is best done by an external low V CC Reset Protection circuit, often referred to as a Brown-out Detector (BOD). Please refer to application note AVR 180 for design considerations regarding power-on reset and low-voltage detection. 2. Keep the AVR core in Power-down Sleep mode during periods of low V CC. This will prevent the CPU from attempting to decode and execute instructions, effec- tively protecting the EEPROM registers from unintentional writes. 3. Store constants in Flash memory if the ability to change memory contents from software is not required. Flash memory cannot be updated by the CPU, and will not be subject to corruption.

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log Comparator Interrupt is activated. When cleared (zero), the interrupt is disabled. This bit is a reserved bit in the AT90S1200 and will always read as zero. These bits determine which comparator events trigger the Analog Comparator Interrupt. The different settings are shown in Table 7. can occur when the bits are changed. Table 7. ACIS1/ACIS0 Settings

pull-up resistors (if configured as input). Port B Port B is an 8-bit bi-directional I/O port. and the Data Direction Register are read/write. The Port B pins with alternate functions are shown in Table 8. be set according to the alternate function description. is read, and when reading PINB, the logical values present on the pins are read. Table 8. Port B Pin Alternate Functions

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Port B as General Digital I/O All eight pins in Port B have equal functionality when used as digital I/O pins. Note: n: 7,6...0, pin number. SCK, Clock Input pin for memory up/downloading. MISO, Data Output pin for memory uploading. MOSI, Data Input pin for memory downloading. [zero]), this pin also serves as the negative input of the On-chip Analog Comparator. this pin also serves as the positive input of the On-chip Analog Comparator. Table 9. DDBn Effect on Port B Pins 0 1 Input Y es PBn will source current if ext. pulled low.

Figure 22. Port B Schematic Diagram (Pins PB0 and PB1)

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Figure 23. Port B Schematic Diagram (Pins PB2, PB3, and PB4) Figure 24. Port B Schematic Diagram (Pin PB5)

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and the Data Direction Register are read/write. low will source current if the pull-up resistors are activated. Some Port D pins have alternate functions as shown in Table 10. is read; and when reading PIND, the logical values present on the pins are read. PORTDn bit has to be cleared (zero) or the pin has to be configured as an output pin. Table 10. Port D Pin Alternate Functions

T0, Timer/Counter0 clock source. See the timer description for further details. INT0, External Interrupt source 0. See the interrupt description for further details. Figure 27. Port D Schematic Diagram (Pins PD0, PD1, PD3, PD5, and PD6) Table 11. DDDn Bits’ Effect on Port D Pins 0 1 Input Y es PDn will source current if ext. pulled low.

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Figure 28. Port D Schematic Diagram (Pin PD2) Figure 29. Port D Schematic Diagram (Pin PD4)

can only be erased with the Chip Erase command. the Fuse bits before programming the Lock bits. Fuse Bits The AT90S1200 has two Fuse bits: SPIEN and RCEN. enabled. Default value is programmed (“0”). programmed (“0”) can be delivered on demand. Fuse bits is not affected by Chip Erase.

1. $00: $1E (indicates manufactured by Atmel)
2. $01: $90 (indicates 1 Kb Flash memory)

in Serial mode. Reading the signature bytes will return: $00, $01 and $02. ory and 64 bytes of EEPROM data memory. Table 12. Lock Bit Protection Modes 1 1 1 No memory lock features enabled. 3 0 0 Same as mode 2, and verify is also disabled.

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the supply voltage must be in accordance with Table 13. EEPROM data memory, Lock bits and Fuse bits in the AT90S1200. Figure 30. Parallel Programming and Table 14. Pins not described in Table 14 are referenced by pin names. tive pulse. The coding is shown in Table 15. command is a byte where the different bits are assigned functions as shown in Table 16. Table 13. Supply Voltage during Programming Table 14. Pin Name Mapping

1. Apply supply voltage according to Table 13, between V CC and GND.
2. Set the RESET and BS pin to “0” and wait at least 100 ns.
3. Apply 11.5 - 12.5V to RESET . Any activity on BS within 100 ns after +12V has
4. Set XA1, XA0 to “10”. This enables command loading.
5. Set DATA to “1000 0000”. This is the command for Chip Erase.
6. Give XTAL1 a positive pulse. This loads the command.

in Table 17. Chip Erase does not generate any activity on the RDY/BSY pin.

1. Set XA1, XA0 to “10”. This enables command loading.
2. Set DATA to “0001 0000”. This is the command for Write Flash.

Table 15. XA1 and XA0 Coding 0 1 Load Data (High or low data byte for Flash determined by BS). Table 16. Command Byte Coding

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0838H–AVR–03/02 4. Give XTAL1 a positive pulse. This loads the command. B: Load Address High Byte 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS to “1”. This selects high byte. 3. Set DATA = Address high byte ($00 - $01). 4. Give XTAL1 a positive pulse. This loads the address high byte. C: Load Address Low Byte 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS to “0”. This selects low byte. 3. Set DATA = Address low byte ($00 - $FF). 4. Give XTAL1 a positive pulse. This loads the address low byte. D: Load Data Low Byte 1. Set XA1, XA0 to “01”. This enables data loading. 2. Set DATA = Data low byte ($00 - $FF). 3. Give XTAL1 a positive pulse. This loads the data low byte. E: Write Data Low Byte 1. Set BS to “0”. This selects low data. 2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low. 3. Wait until RDY/BSY goes high to program the next byte. (See Figure 31 for signal waveforms.) F: Load Data High Byte 1. Set XA1, XA0 to “01”. This enables data loading. 2. Set DATA = Data high byte ($00 - $FF). 3. Give XTAL1 a positive pulse. This loads the data high byte. G: Write Data High Byte 1. Set BS to “1”. This selects high data. 2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low. 3. Wait until RDY/BSY goes high to program the next byte. (See Figure 32 for signal waveforms.) The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered:  The command needs only be loaded once when writing or reading multiple memory locations.  Address high byte needs only be loaded before programming a new 256-word page in the Flash.  Skip writing the data value $FF; that is, the contents of the entire Flash and EEPROM after a Chip Erase. These considerations also apply to EEPROM programming and Flash, EEPROM and signature byte reading.

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0838H–AVR–03/02 Programming the EEPROM The programming algorithm for the EEPROM data memory is as follows (refer to “Pro- gramming the Flash” for details on command, address and data loading): 1. A: Load Command “0001 0001”. 2. C: Load Address Low Byte ($00 - $3F). 3. D: Load Data Low Byte ($00 - $FF). 4. E: Write Data Low Byte. Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash” for details on command and address loading): 1. A: Load Command “0000 0011”. 2. C: Load Address Low Byte ($00 - $3F). 3. Set OE to “0”, and BS to “0”. The EEPROM data byte can now be read at DATA. 4. Set OE to “1”. Programming the Fuse Bits The algorithm for programming the Fuse bits is as follows (refer to “Programming the Flash” for details on command and data loading): 1. A: Load Command “0100 0000”. 2. D: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. Bit 5 = SPIEN Fuse Bit 0 = RCEN Fuse Bit 7 - 6, 4 - 1 = “1”. These bits are reserved and should be left unprogrammed (“1”). 3. Give WR a tWLWH_PFB wide negative pulse to execute the programming; tWLWH_PFB is found in Table 17. Programming the Fuse bits does not generate any activity on the RDY/BSY pin. Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” for details on command and data loading): 1. A: Load Command “0010 0000”. 2. D: Load Data Low Byte. Bit n = “0” programs the Lock bit. Bit 2 = Lock Bit2 Bit 1 = Lock Bit1 Bit 7 - 3, 0 = “1”. These bits are reserved and should be left unprogrammed (“1”). 3. E: Write Data Low Byte. The Lock bits can only be cleared by executing Chip Erase. Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash” on page 39 for details on command loading): 1. A: Load Command “0000 0100”. 2. Set OE to “0”, and BS to “1”. The status of Fuse and Lock bits can now be read at DA TA (“0” means programmed). Bit 7 = Lock Bit1 Bit 6 = Lock Bit2 Bit 5 = SPIEN Fuse Bit 0 = RCEN Fuse 3. Set OE to “1”. Observe especially that BS needs to be set to “1”.

1. C: Load Address Low Byte ($00 - $02).

Set OE to “0”, and BS to “0”. The selected signature byte can now be read at DATA. Figure 33. Parallel Programming Timing Notes: 1. Use t WLWH_CE for chip erase and tWLWH_PFB for programming the Fuse bits.

1. If t WLWH is held longer than tWLRH, no RDY/BSY pulse will be seen.

Table 17. Parallel Programming Characteristics, TA = 25°C ± 10%, VCC = 5V ± 10%

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Figure 34. Serial Programming and Verify $01FF for Flash program memory and $000 to $03F for EEPROM data memory. When writing serial data to the AT90S1200, data is clocked on the rising edge of SCK. When reading data from the AT90S1200, data is clocked on the falling edge of SCK. See Figure 35 and Table 20 for timing details. positive pulse after SCK has been set to “0”.

1. Wait for at least 20 ms and enable serial programming by sending the Program-

ming Enable serial instruction to the MOSI (PB5) pin.

1. If a Chip Erase is performed (must be done to erase the Flash), wait t WD_ERASE

after the instruction, give RESET a positive pulse, and start over from step 2. See Table 21 on page 47 for tWD_ERASE value.

1. The Flash or EEPROM array is programmed one byte at a time by supplying the
2. Any memory location can be verified by using the Read instruction which returns

the content at the selected address at the serial output MISO (PB6) pin.

1. Power-off sequence (if needed):

value P2. See Table 18 for P1 and P2 values. EEPROM is reprogrammed without first chip-erasing the device. to contain $FF, can be skipped. Table 18. Read Back Value during EEPROM Polling

46 AT90S1200

Figure 35. Serial Programming Waveforms Note: 1. The signature bytes are not readable in lock mode 3 (i.e., both Lock bits programmed). Table 19. Serial Programming Instruction Set for AT90S1200 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable serial programming while RESET is low.

0010 H000 0000 000 a bbbb bbbb oooo oooo Read H (high or low) byte o from program memory at

0100 H000 0000 000 a bbbb bbbb iiii iiii Write H (high or low) byte i to program memory at

1010 0000 0000 0000 00 bb bbbb oooo oooo Read data o from EEPROM memory at address b. 1100 0000 0000 0000 00 bb bbbb iiii iiii Write data i to EEPROM memory at address b.

Figure 36. Serial Programming Timing Table 20. Serial Programming Characteristics, T A = -40 °C to 85 °C, VCC = 2.7 - 6.0V Table 21. Minimum Wait Delay after the Chip Erase Instruction Table 22. Minimum Wait Delay after Writing a Flash or EEPROM Location

48 AT90S1200

0838H–AVR–03/02

Electrical Characteristics

Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Any Pin Except RESET DC Current DC Characteristics TA = -40×C to 85×C, VCC = 2.7V to 6.0V (unless otherwise noted) Symbol Parameter Condition Min Typ Max Units VIL Input Low Voltage (Except XT AL1) -0.5 0.3 V CC (1) V VIL1 Input Low Voltage (XT AL1) -0.5 0.3 V CC (1) V VIH Input High Voltage (Except XT AL1, RESET ) 0.6 V CC (2) V CC + 0.5 V VIH1 Input High Voltage (XT AL1) 0.7 V CC (2) VCC + 0.5 V VIH2 Input High Voltage (RESET ) 0.85 V CC (2) VCC + 0.5 V VOL Output Low Voltage(3) (Ports B, D) IOL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 3V 0.6 0.5 V V VOH Output High Voltage(4) (Ports B, D) IOH = -3 mA, VCC = 5V IOH = -1.5 mA, VCC = 3V 4.3 2.3 V V IIL Input Leakage Current I/O pin VCC = 6V, pin low (absolute value) 8.0 µA IIH Input Leakage Current I/O pin VCC = 6V, pin high (absolute value) 980.0 nA RRST Reset Pull-up Resistor 100.0 500.0 k Ω RI/O I/O Pin Pull-up Resistor 35.0 120.0 k Ω ICC Power Supply Current Active Mode, V CC = 3V, 4M H z 3.0 mA Idle Mode VCC = 3V, 4 MHz 1.0 mA ICC Power-down mode(5) WDT enabled, VCC = 3V 9.0 15.0 µA WDT disabled, VCC = 3V <1.0 2.0 µA

0838H–AVR–03/02 Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low. 2. “Min” means the lowest value where the pin is guaranteed to be read as high. 3. Although each I/O port can sink more than the test conditions (20 mA at V CC = 5V, 10 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 1] The sum of all I OL, for all ports, should not exceed 200 mA. 2] The sum of all IOL, for port D0 - D5 and XTAL2, should not exceed 100 mA. 3] The sum of all IOL, for ports B0 - B7 and D6, should not exceed 100 mA. If IOL exceeds the test condition, V OL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (3 mA at V CC = 5V, 1.5 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 1] The sum of all IOH, for all ports, should not exceed 200 mA. 2] The sum of all IOH, for port D0 - D5 and XTAL2, should not exceed 100 mA. 3] The sum of all IOH, for ports B0 - B7 and D6, should not exceed 100 mA. If I OH exceeds the test condition, V OH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. Minimum V CC for power-down is 2V. VACIO Analog Comparator Input Offset Voltage VCC = 5V Vin = VCC/ 2 40.0 mV IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/ 2 -50.0 50.0 nA tACPD Analog Comparator Propagation Delay VCC = 2.7V VCC = 4.0V 750.0 500.0 ns DC Characteristics TA = -40×C to 85×C, VCC = 2.7V to 6.0V (unless otherwise noted) (Continued) Symbol Parameter Condition Min Typ Max Units

50 AT90S1200

Figure 37. External Clock Drive Table 23. External Clock Drive

to-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection. ambient temperature. The dominating factors are operating voltage and frequency. switching frequency of I/O pin. teed to function properly at frequencies higher than the ordering code indicates. ferential current drawn by the Watchdog Timer. Figure 38. Active Supply Current vs. Frequency

52 AT90S1200

Figure 39. Active Supply Current vs. VCC Figure 40. Active Supply Current vs. VCC, Device Clocked by Internal Oscillator

54 AT90S1200

Figure 43. Idle Supply Current vs. VCC, Device Clocked by Internal Oscillator Figure 44. Power-down Supply Current vs. VCC, Watchdog Timer Disabled

56 AT90S1200

Figure 47. Analog Comparator Current vs. VCC Note: Analog comparator offset voltage is measured as absolute offset. Figure 48. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs.

58 AT90S1200

Note: Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 51. Pull-up Resistor Current vs. Input Voltage Figure 52. Pull-up Resistor Current vs. Input Voltage

60 AT90S1200

Figure 55. I/O Pin Sink Current vs. Output Voltage Figure 56. I/O Pin Source Current vs. Output Voltage

62 AT90S1200

0838H–AVR–03/02 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory address es should never be written. 2. Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a “1” back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. AT90S1200 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $3F SREG I T H S V N Z C page 11 $3E Reserved $3D Reserved $3C Reserved $3B GIMSK -I N T 0 - - - - - - page 15 $3A Reserved $39 TIMSK - - - - - - TOIE0 - page 16 $38 TIFR - - - - - -T O V 0 - page 16 $37 Reserved $36 Reserved $35 MCUCR - -S E S M - - ISC01 ISC00 page 18 $34 Reserved $33 TCCR0 - - - - - CS02 CS01 CS00 page 21 $32 TCNT0 Timer/Counter0 (8 Bits) page 22 $31 Reserved $30 Reserved $2F Reserved $2E Reserved $2D Reserved $2C Reserved $2B Reserved $2A Reserved $29 Reserved $28 Reserved $27 Reserved $26 Reserved $25 Reserved $24 Reserved $23 Reserved $22 Reserved $21 WDTCR - - - - WDE WDP2 WDP1 WDP0 page 23 $20 Reserved $1F Reserved $1E EEAR - EEPROM Address Register page 25 $1D EEDR EEPROM Data Register page 25 $1C EECR - - - - - - EEWE EERE page 25 $1B Reserved $1A Reserved $19 Reserved $18 PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 page 29 $17 DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 page 29 $16 PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 page 29 $15 Reserved $14 Reserved $13 Reserved $12 PORTD - PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 page 34 $11 DDRD - DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 page 34 $10 PIND - PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 page 34 $0F Reserved ... Reserved $09 Reserved $08 ACSR ACD - ACO ACI ACIE - ACIS1 ACIS0 page 27 … Reserved $00 Reserved

0838H–AVR–03/02 Instruction Set Summary Mnemonic Operands Description Operation Flags # Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add Two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry Two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 SUB Rd, Rr Subtract Two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry Two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1 AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1 COM Rd One ’s Complement Rd ← $FF - Rd Z,C,N,V 1 NEG Rd Two ’s Complement Rd ← $00 - Rd Z,C,N,V,H 1 SBR Rd, K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1 CBR Rd, K Clear Bit(s) in Register Rd ← Rd • (FFh - K) Z,N,V 1 INC Rd Increment Rd ← Rd + 1 Z,N,V 1 DEC Rd Decrement Rd ← Rd - 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1 SER Rd Set Register Rd ← $FF None 1 BRANCH INSTRUCTIONS RJMP k Relative Jump PC ← PC + k + 1 None 2 RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3 RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I 4 CPSE Rd, Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2 CP Rd, Rr Compare Rd - Rr Z,N,V,C,H 1 CPC Rd, Rr Compare with Carry Rd - Rr - C Z,N,V,C,H 1 CPI Rd, K Compare Register with Immediate Rd - K Z,N,V,C,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC ← PC + 2 or 3 None 1/2 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b) = 1) PC ← PC + 2 or 3 None 1/2 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)= 0) PC ← PC + 2 or 3 None 1/2 SBIS P, b Skip if Bit in I/O Register is Set if (P(b) = 1) PC ← PC + 2 or 3 None 1/2 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ← PC + k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ← PC + k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V = 0) then PC ← PC + k + 1 None 1/2 BRLT k Branch if Less than Zero, Signed if (N ⊕ V = 1) then PC ← PC + k + 1 None 1/2 BRHS k Branch if Half-carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2 BRHC k Branch if Half-carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2 BRTS k Branch if T-Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2 BRTC k Branch if T-Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if (I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if (I = 0) then PC ← PC + k + 1 None 1/2 DATA TRANSFER INSTRUCTIONS LD Rd, Z Load Register Indirect Rd ← (Z) None 2 ST Z, Rr Store Register Indirect (Z) ← Rr None 2 MOV Rd, Rr Move between Registers Rd ← Rr None 1 LDI Rd, K Load Immediate Rd ← K None 1 IN Rd, P In Port Rd ← P None 1 OUT P, Rr Out Port P ← Rr None 1

64 AT90S1200

0838H–AVR–03/02 BIT AND BIT-TEST INSTRUCTIONS SBI P, b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P, b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left through Carry Rd(0) ← C,Rd(n+1) ← Rd(n),C ← Rd(7) Z,C,N,V 1 ROR Rd Rotate Right through Carry Rd(7) ← C,Rd(n) ← Rd(n+1),C ← Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n = 0..6 Z,C,N,V 1 BSET s Flag Set SREG(s) ← 1 SREG(s) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit Load from T to Register Rd(b) ← T None 1 SEC Set Carry C ← 1C 1 CLC Clear Carry C ← 0C 1 SEN Set Negative Flag N ← 1N 1 CLN Clear Negative Flag N ← 0N 1 SEZ Set Zero Flag Z ← 1Z 1 CLZ Clear Zero Flag Z ← 0Z 1 SEI Global Interrupt Enable I ← 1I 1 CLI Global Interrupt Disable I ← 0I 1 SES Set Signed Test Flag S ← 1S 1 CLS Clear Signed Test Flag S ← 0S 1 SEV Set Two ’s Complement Overflow V ← 1V 1 CLV Clear Two ’s Complement Overflow V ← 0V 1 SET Set T in SREG T ← 1T 1 CLT Clear T in SREG T ← 0T 1 SEH Set Half-carry Flag in SREG H ← 1H 1 CLH Clear Half-carry Flag in SREG H ← 0H 1 NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 Instruction Set Summary (Continued) Mnemonic Operands Description Operation Flags # Clocks

0838H–AVR–03/02 Note: 1. Order AT90S1200A-XXX for devices with the RCEN Fuse programmed. Ordering Information(1) Speed (MHz) Power Supply Ordering Code Package Operation Range 4 2.7 - 6.0V AT90S1200-4PC AT90S1200-4SC AT90S1200-4YC 20P3 20S 20Y Commercial (0°C to 70°C) AT90S1200-4PI AT90S1200-4SI AT90S1200-4YI 20P3 20S 20Y Industrial (-40°C to 85°C) 12 4.0 - 6.0V AT90S1200-12PC AT90S1200-12SC AT90S1200-12YC 20P3 20S 20Y Commercial (0°C to 70°C) AT90S1200-12PI AT90S1200-12SI AT90S1200-12YI 20P3 20S 20Y Industrial (-40°C to 85°C) Package Type 20P3 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20S 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 20Y 20-lead, 5.3 mm Wide, Plastic Shrink Small Outline Package (SSOP)

66 AT90S1200

0838H–AVR–03/02 Packaging Information 20P3

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) B20P3 09/28/01 PIN B E C L SEATING PLANE A D e eB eC COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 5.334 A1 0.381 – – D 25.984 – 25.493 Note 2 E 7.620 – 8.255 E1 6.096 – 7.112 Note 2 B 0.356 – 0.559 B1 1.270 – 1.551 L 2.921 – 3.810 C 0.203 – 0.356 eB – – 10.922 eC 0.000 – 1.524 e 2.540 TYP Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

0838H–AVR–03/02 20S 7.60 (0.2992) 7.40 (0.2914) 0.51(0.020) 0.33(0.013) 10.65 (0.419) 10.00 (0.394) PIN 1 ID 1.27 (0.050) BSC 13.00 (0.5118) 12.60 (0.4961) 0.30(0.0118) 0.10 (0.0040) 2.65 (0.1043) 2.35 (0.0926) 0º ~ 8º 1.27 (0.050) 0.40 (0.016) 0.32 (0.0125) 0.23 (0.0091) *Controlling dimension: Inches 20S, 20-lead, Plastic Gull Wing Small Outline (SOIC), 0.300" body. Dimensions in Millineters and (Inches)* JEDEC STANDARD MS-013 PIN 1 REV. A 04/11/2001

68 AT90S1200

0838H–AVR–03/02 20Y 5.38 (0.212) 5.20 (0.205) 7.90 (0.311) 7.65 (0.301) 0.65 (0.0256) BSC 0.38 (0.015) 0.25 (0.010) PIN 1 ID 7.33 (0.289) 7.07 (0.278) 0.21 (0.008) 0.05 (0.002) 1.99 (0.078) 1.73 (0.068) 0.20 (0.008) 0.09 (0.004) 0.95 (0.037) 0.63 (0.025) 0º ~ 8º PIN 1 20Y, 20-lead Plastic Shrink Small Outline (SSOP), 5.3mm body Width. Dimensions in Millimeters and (inches)* *Controlling dimension: millimeters REV. A 04/11/2001

i AT90S1200 0838H–AVR–03/02

0838H–AVR–03/02

Ordering Information

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