9042 MAXWELL | Alldatasheet
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All data sheets are subject to change without notice (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com 12-Bit, 41 MSPS A/D Converter 9042 ©2007 Maxwell Technologies All rights reserved.
01.07.05 REV 7
FEATURES:
- Total dose hardness: - > 300 krad (Si) SEL > 120 MeV-cm2/mg 41 MSPS minimum sampling rate 80 dB Spurious-Free Dynamic Range (SFDR) Package: - 28 pin R AD-PAK® flat pack 595 mW power dissipation Single 5 volt power supply On-chip T/H and reference Two’s complement output format CMOS compatible output levels DESCRIPTION: Maxwell Technologies’ 9042 12-Bit analog-to-digital converter features a greater than 300 krad (Si) total dose tolerance. Using Maxwell’s radiation-hardened R AD-PAK® packaging technology, the 9042 realizes a higher performance, and low power consumption. All necessary functions, including track- and-hold (T/H) and reference are included on chip to provide a complete conversion solution. The 9042 runs off of a single +5V supply and provides CMOS-compatible digital outputs at 41 MSPS. Designed specifically to address the needs of wide- band, multichannel receivers, the 9042 maintains 80 dB spuri- ous-free dynamic range (SFDR) over a bandwidth of 20 MHz. Noise performance is also exceptional; typical signal to noise ratio is 68 dB. Maxwell Technologies' patented R AD-PAK® packaging technol- ogy incorporates radiation shielding in the microcircuit pack- age. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in an orbit or space mission. This product is available with screening up to Maxwell Technologies self-defined Class K.
TABLE 1. 9042 PIN DESCRIPTION
1 GND Ground
3 GND Ground
4 ENCODE Encode Input. Data conversion initiated on rising edge.
5 ENCODE
to Ground for single-ended clock mode.
6 GND Ground
7 GND Ground
tied to VREF through 50 Ohm resistor. through 50 Ohm resistor. Bypass to Ground with 0.01 µ F capacitor.
11 GND Ground
12 AV CC 5V Power Supply (Analog)
13 GND Ground
17 D0 (LSB) Digital Output Bit (Least Significant Bit). 18 - 27 D1 - D10 Digital Output Bits.
28 D11 (MSB)
- Output coded as twos compliment
Digital Output Bit (Most Significant Bit).
TABLE 2. 9042 ABSOLUTE MAXIMUM RATINGS1
- A bsolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily
implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. TABLE 3. DELTA LIMITS TABLE 4. 9042 DC ELECTRICAL CHARACTERISTICS
- V REF is normally tied to VOFFSET through 50 ohms. If VREF is used to provide dc offset to other circuits, it should first be buffered
- ENCODE driven by single-ended source; ENCODE bypassed to ground through 0.01 µF capacitor.
- ENCODE may also be driven differently in conjunction with ENCODE .
TABLE 4. 9042 DC ELECTRICAL CHARACTERISTICS
TABLE 5. 9042 AC ELECTRICAL CHARACTERISTICS1
19.5 MHz 25°C 4 64 67 --
19.5 MHz 25°C 4 73 80 --
1.2 MHz -55 to 125°C 4, 5, 6 -- 90 --
9.6 MHz -- 90 --
19.5 MHz -- 90 --
FIGURE 1. TIMING DIAGRAM
- All AC specifications tested by driving ENCODE and ENCODE differentially.
- Analog input signal power at -1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five har monics removed).
- Analog input signal power at -1 dBFS; signal-to-noise and distorsion (SINAD) is the ratio of signal level to total noise + ha rmonics.
- Analog input signal power at -1 dBFS; worst spur is the ratio of signal level to worst spur, usually limited by harmonics.
- Analog input signal power swept from -20 dBFS to -95 dBFS; dither power = -32.5 dBm; dither circuit used on input signal SFDR is ratio of converter full scale to worst spur.
- Tones at -7dBFS (F1 = 15.3 MHz, F2 = 19.5 MHz); two tone intermodualtion distortion (IMD) rejection is ratio or either tone t o worst third order intermod product.
- Both input tones swept from -20 to -95 dBFS; dither power = -32.5 dBm; dither circuit used on input signal two-tone spurious- free dynamic range (SFDR) is the ratio of converter full
TABLE 5. 9042 AC ELECTRICAL CHARACTERISTICS1
FIGURE 2. ANALOG INPUT STAGE EQUIVALENT CIRCUIT FIGURE 3. ENCODE INPUTS EQUIVALENT CIRCUIT
FIGURE 4. COMPENSATION PIN, C1 EQUIVALENT CIRCUIT
FIGURE 5. DIGITAL OUTPUT STAGE EQUIVALENT CIRCUIT FIGURE 6. 2.4 V REFERENCE EQUIVALENT CIRCUIT
FIGURE 7. SINGLE TONE AT 1.2 MHZ FIGURE 8. SINGLE TONE AT 9.6 MHZ
FIGURE 9. SINGLE TONE AT 19.5 MHZ FIGURE 10. HARMONICS VS. AIN
FIGURE 11. NOISE VS. AIN FIGURE 12. HARMONICS VS. AIN
FIGURE 13. TWO TONES AT 15.3 MHZ AND 19.5 MHZ FIGURE 14. SINGLE TONE SFDR
FIGURE 15. TWO TONES SFDR FIGURE 16. SNR WORST HARMONIC VS. ENCODE
FIGURE 17. SNR WORST CASE SPURIOUS VS. DUTY CYCLE FIGURE 18. NPR OUTPUT SPECTRUM
Figure 19. Single-Ended TTL/CMOS Encode
to ground. Devices such as AVX 05085C103MA15, a 0.01 mF capacitor, work well. tor, RX, to raise or lower the trip point (See Figure 3; R1 = 17k, R2 = 8k). Figure 20. Lower Logic Threshold for Encode
Figure 21. Raise Logic Threshold for Encode encode inputs are self biased, no additional components are required. Figure 22. TTL Source – Differential Encode
selected to match the source impedance. The input impedance of the 9042 is negligible in most cases. Figure 23. Sine Source – Differential Encode Figure 24. Differential ECL for Encode
a logic signal or a sine signal. Figure 25. ECL Comparator for Encode designed to track internal circuit shifts over temperature.
Figure 26. Analog Input Offset by +2.4 V Reference mF chip capacitor will work well. Figure 27. AC-Coupled Analog Input Signal
from flowing through the transformer. Figure 28. Transformer-Coupled Analog Input Signal where Z is desired impedance. dB–80 dB of dynamic performance depending on which drive amplifier is used. The AD9631 and OP279 run off ±5 V. Figure 29. DC-Coupled Analog Input Circuit
23All data sheets are subject to change without notice ©2005 Maxwell Technologies All rights reserved. 12-Bit, 41 MSPS A/D Converter 9042 Care should be taken when selecting a power source. Linear supplies are strongly recommended as switching sup- plies tend to have radiated components that may be “received” by the 9042. Each of the power supply pins should be decoupled as closely to the package as possible using 0.1 mF chip capacitors. The 9042 has separate digital and ana- log +5 V pins. The analog supplies and the denoted A VCC digital supply pins are denoted D VCC. Although analog and digital supplies may be tied together, best performance is achieved when the supplies are separate. This is because the fast digital output swings can couple switching noise back into the analog supplies. Note that A VCC must be held within 5% of 5 volts, however the D VCC supply may be varied according to output digital logic family (i.e., D VCC should be connected to the supply for the digital circuitry). Output Loading Care must be taken when designing the data receivers for the AD9042. It is recommended that the digital outputs drive a series resistor of 499 ohms followed by a CMOS gate like the 74AC574. To minimize capacitive loading, there should only be one gate on each output pin. The digital outputs of the 9042 have a unique constant slew rate output stage. The output slew rate is about 1 V/ns independent of output loading. A typical CMOS gate combined with PCB trace and through hole will have a load of approximately 10 pF. Therefore as each bit switches, 10 mA of dynamic current per bit will flow in or out of the device. A full- scale transition can cause up to 120 mA (12bits ´ 10 mA/bit) of current to flow through the digital output stage. The series resistor will minimize the output currents that can flow in the output stage. These switching currents are confined between ground and the D VCC pin. Standard TTL gates should be avoided since they can appreciably add to the dynamic switching currents of the 9042.
24All data sheets are subject to change without notice ©2005 Maxwell Technologies All rights reserved. 12-Bit, 41 MSPS A/D Converter 9042 Note: All dimensions in inches 28-PIN RAD-PAK® FLAT PACKAGE SYMBOL DIMENSION MIN NOM MAX A 0.129 0.142 0.155 b 0.015 0.017 0.022 c 0.004 0.005 0.009 D -- 0.820 0.828 E 0.474 0.480 0.486 E1 -- -- 0.506 E2 0.255 0.260 -- E3 0.000 0.110 -- e 0.050 BSC L 0.375 0.385 0.395 Q 0.021 0.025 0.029 S1 0.000 0.077 -- N2 8
25All data sheets are subject to change without notice ©2005 Maxwell Technologies All rights reserved. 12-Bit, 41 MSPS A/D Converter 9042 Important Notice: These data sheets are created using the chip manufacturer’s published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech- nologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.
26All data sheets are subject to change without notice ©2005 Maxwell Technologies All rights reserved. 12-Bit, 41 MSPS A/D Converter 9042 Feature Option Details9042 RP F X Screening Flow Package Radiation Feature Base Product Nomenclature MCM1 K= Maxwell Self-Defined Class K H= Maxwell Self-Defined Class H I = Industrial (testing @ -55°C, +25°C, +125°C) E = Engineering (testing @ +25°C) F = Flat Pack RP = R AD-PAK® package 12-Bit, 41 MSPS A/D Converter 1) Products are manufactured and screened to Maxwell Technologies self-defined Class H and Class K flows.