AT89S8252 ATMEL | Alldatasheet
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Technical content
Features
Compatible with MCS® 51 Products 8K Bytes of In-System Reprogrammable Downloadable Flash Memory – SPI Serial Interface for Program Downloading – Endurance: 1,000 Write/Erase Cycles 2K Bytes EEPROM – Endurance: 100,000 Write/Erase Cycles 4V to 6V Operating Range Fully Static Operation: 0 Hz to 24 MHz Three-level Program Memory Lock 256 x 8-bit Internal RAM 32 Programmable I/O Lines Three 16-bit Timer/Counters Nine Interrupt Sources Programmable UART Serial Channel SPI Serial Interface Low-power Idle and Power-down Modes Interrupt Recovery from Power-down Programmable Watchdog Timer Dual Data Pointer Power-off Flag
Description
The AT89S8252 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of downloadable Flash programmable and erasable read-only memory and 2K bytes of EEPROM. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip downloadable Flash allows the program memory to be reprogrammed In-System through an SPI serial interface or by a conventional nonvol- atile memory programmer. By combining a versatile 8-bit CPU with downloadable Flash on a monolithic chip, the Atmel AT89S8252 is a powerful microcontroller, which provides a highly-flexible and cost-effective solution to many embedded control applications. The AT89S8252 provides the following standard features: 8K bytes of downloadable Flash, 2K bytes of EEPROM, 256 bytes of RAM, 32 I/O lines, programmable watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S8252 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset. The downloadable Flash can be changed a single byte at a time and is accessible through the SPI serial interface. Holding RESET active forces the SPI bus into a serial programming interface and allows the program memory to be written to or read from unless lock bits have been activated. 8-bit Microcontroller with 8K Bytes Flash AT89S8252
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0401F–MICRO–11/03 Pin Configurations PDIP (T2) P1.0 (T2 EX) P1.1 P1.2 P1.3 (SS) P1.4 (MOSI) P1.5 (MISO) P1.6 (SCK) P1.7 RST (RXD) P3.0 (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 (WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8) TQFP (MOSI) P1.5 (MISO) P1.6 (SCK) P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P1.4 (SS) P1.3 P1.2 P1.1 (T2 EX) P1.0 (T2) NC VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) (WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND GND (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4 PLCC Pin Description VCC Supply voltage. GND Ground. Port 0 Port 0 is an 8-bit open drain bi-didirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high- impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification. Port 1 Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are exter- nally being pulled low will source current (I IL) because of the internal pull-ups. (MOSI) P1.5 (MISO) P1.6 (SCK) P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) (WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND NC (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4 P1.4 (SS) P1.3 P1.2 P1.1 (T2 EX) P1.0 (T2) NC VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3)
0401F–MICRO–11/03 Block Diagram PORT 2 DRIVERS PORT 2 LATCH P2.0 - P2.7 FLASHPORT 0 LATCHRAMEEPROM PROGRAM ADDRESS REGISTER BUFFER PC INCREMENTER PROGRAM COUNTER DUAL DPTR INSTRUCTION REGISTER B REGISTER INTERRUPT, SERIAL PORT, AND TIMER BLOCKS STACK POINTERACC TMP2 TMP1 ALU PSW TIMING AND CONTROL PORT 1 DRIVERS P1.0 - P1.7 PORT 3 LATCH PORT 3 DRIVERS P3.0 - P3.7 OSC GND VCC PSEN ALE/PROG EA / V PP RST RAM ADDR. REGISTER PORT 0 DRIVERS P0.0 - P0.7 PORT 1 LATCH WATCH DOG SPI PORT PROGRAM LOGIC
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0401F–MICRO–11/03 Some Port 1 pins provide additional functions. P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively. Furthermore, P1.4, P1.5, P1.6, and P1.7 can be configured as the SPI slave port select, data input/output and shift clock input/output pins as shown in the following table. Port 1 also receives the low-order address bytes during Flash programming and verification. Port 2 Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are exter- nally being pulled low will source current (I IL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are exter- nally being pulled low will source current (I IL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S8252, as shown in the following table. Port Pin Alternate Functions P1.0 T2 (external count input to Timer/Counter 2), clock-out P1.1 T2EX (Timer/Counter 2 capture/reload trigger and direction control) P1.4 SS (Slave port select input) P1.5 MOSI (Master data output, slave data input pin for SPI channel) P1.6 MISO (Master data input, slave data output pin for SPI channel) P1.7 SCK (Master clock output, slave clock input pin for SPI channel)
0401F–MICRO–11/03 RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE/PROG Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG ) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. PSEN Program Store Enable is the read strobe to external program memory. When the AT89S8252 is executing code from external program memory, PSEN is acti- vated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA /VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP ) during Flash programming when 12-volt pro- gramming is selected. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. Port Pin Alternate Functions P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2 INT0 (external interrupt 0) P3.3 INT1 (external interrupt 1) P3.4 T0 (timer 0 external input) P3.5 T1 (timer 1 external input) P3.6 WR (external data memory write strobe) P3.7 RD (external data memory read strobe)
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dom data, and write accesses will have an indeterminate effect. Table 1. AT89S8252 SFR Map and Reset Values
Table 2. T2CON – Timer/Counter 2 Control Register EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1). Modes 1 and 3. RCLK = 0 causes Timer 1 overflows to be used for the receive clock. Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer. either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
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DPS bit selects one of two DPTR registers available. Table 3. WMCON—Watchdog and Memory Control Register 16 ms. When all three bits are set to “1”, the nominal period is 2048 ms. MOVX instruction. User software should set this bit to “0” after EEPROM write is completed. instead of external data memory. When EEMEN = 0, MOVX with DPTR accesses external data memory. generated to reset the watchdog timer. The WDTRST bit is then automatically reset to “0” in the next instruction cycle. The WDTRST bit is Write-Only. This bit also serves as the RDY/BSY flag in a Read-Only mode during EEPROM write. the RDY/BSY bit equals “0” and is automatically reset to “1” when programming is completed. WDTEN Watchdog Timer Enable Bit. WDTEN = 1 enables the watchdog timer and WDTEN = 0 disables the watchdog timer.
for writing and the values in SPDR are not changed by Reset. appropriate value before accessing the respective Data Pointer Register. and is not affected by RESET. Table 4. SPCR – SPI Control Register 1 enable SPI interrupts. SPIE = 0 disables SPI interrupts. SPI = 0 disables the SPI channel. DORD Data Order. DORD = 1 selects LSB first data transmission. DORD = 0 selects MSB first data transmission. MSTR Master/Slave Select. MSTR = 1 selects Master SPI mode. MSTR = 0 selects Slave SPI mode. transmitting. Please refer to figure on SPI Clock Phase and Polarity Control. slave. Please refer to figure on SPI Clock Phase and Polarity Control.
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SFR space but are physically separate from SFR space. of RAM or the SFR space. Instructions that use direct addressing access SFR space. data byte at address 0A0H, rather than P2 (whose address is 0A0H). of data RAM are available as stack space. chip data memory with the MOVX instructions, the EEMEN bit needs to be set to “0”. Table 5. SPSR – SPI Status Register cleared by reading the SPI status register with SPIF and WCOL set, and then accessing the SPI data register. Table 6. SPDR – SPI Data Register
pleted and another write cycle can be initiated. pleted, true data are valid at all bit locations. Documents”. Open the document “AT89 Series Hardware Description”. Timer 2 Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. in the SFR T2CON (shown in Table 2). baud rate generator. The modes are selected by bits in T2CON, as shown in Table 8. oscillator periods, the count rate is 1/12 of the oscillator frequency. ister during S3P1 of the cycle following the one in which the transition was detected. Table 7. Watchdog Timer Period Selection
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generate an interrupt. The capture mode is illustrated in Figure 1. Figure 1. Timer 2 in Capture Mode Table 8. Timer 2 Operating Modes
1 X 1 Baud Rate Generator
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Figure 3. Timer 2 Auto Reload Mode (DCEN = 1) Table 9. T2MOD – Timer 2 Mode Control Register – Not implemented, reserved for future use. T2OE Timer 2 Output Enable bit. DCEN When set, this bit allows Timer 2 to be configured as an up/down counter.
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0401F–MICRO–11/03 Timer 2 as a baud rate generator is shown in Figure 4. This figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not gener- ate an interrupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt. Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. Programmable Clock Out A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 5. This pin, besides being a regular I/0 pin, has two alternate functions. It can be pro- grammed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz (for a 16-MHz operating frequency). To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer. The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equation. In the clock-out mode, Timer 2 rollovers will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L. Clock Out Frequency Oscillator Frequency
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the document “AT89 Series Hardware Description”. enable bit (ES) are set, an interrupt is requested. /P1.4, is set low to select an individual SPI device as a slave. are shown in Figure 8 and Figure 9. Figure 7. SPI Master-slave Interconnection
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Figure 10. Interrupt Sources Table 10. Interrupt Enable (IE) Register Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables the interrupt. source is individually enabled or disabled by setting or clearing its enable bit. ET2 IE.5 Timer 2 interrupt enable bit. ES IE.4 SPI and UART interrupt enable bit. ET1 IE.3 Timer 1 interrupt enable bit. EX1 IE.2 External interrupt 1 enable bit. ET0 IE.1 Timer 0 interrupt enable bit. EX0 IE.0 External interrupt 0 enable bit. User software should never write 1s to unimplemented bits, because they may be used in future AT89 products.
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0401F–MICRO–11/03 Idle Mode In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be termi- nated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes program execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory. Power-down Mode In the power-down mode, the oscillator is stopped and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. Exit from power- down can be initiated either by a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before V CC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. To exit power-down via an interrupt, the external interrupt must be enabled as level sen- sitive before entering power-down. The interrupt service routine starts at 16 ms (nominal) after the enabled interrupt pin is activated. Program Memory Lock Bits The AT89S8252 has three lock bits that can be left unprogrammed (U) or can be pro- grammed (P) to obtain the additional features listed in the following table. When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched dur- ing reset. If the device is powered up without a reset, the latch initializes to a random value and holds that value until reset is activated. The latched value of EA must agree with the current logic level at that pin in order for the device to function properly. Once programmed, the lock bits can only be unprogrammed with the Chip Erase opera- tions in either the parallel or serial modes. Notes: 1. U = Unprogrammed 2. P = Programmed Status of External Pins During Idle and Power-down Modes Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3 Idle Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power-down Internal 0 0 Data Data Data Data Power-down External 0 0 Float Data Data Data Lock Bit Protection Modes(1)(2) Program Lock Bits Protection TypeLB1 LB2 LB3 1 U U U No internal memory lock feature. 2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. EA is sampled and latched on reset and further programming of the Flash memory (parallel or serial mode) is disabled. 3 P P U Same as Mode 2, but parallel or serial verify are also disabled. 4 P P P Same as Mode 3, but external execution is also disabled.
0401F–MICRO–11/03 Programming the Flash and EEPROM Atmel’s AT89S8252 Flash Microcontroller offers 8K bytes of in-system reprogrammable Flash Code memory and 2K bytes of EEPROM Data memory. The AT89S8252 is normally shipped with the on-chip Flash Code and EEPROM Data memory arrays in the erased state (i.e. contents = FFH) and ready to be programmed. This device supports a High-voltage (12-V V PP ) Parallel programming mode and a Low- voltage (5-V VCC ) Serial programming mode. The serial programming mode provides a convenient way to reprogram the AT89S8252 inside the user’s system. The parallel pro- gramming mode is compatible with conventional third party Flash or EPROM programmers. The Code and Data memory arrays are mapped via separate address spaces in the serial programming mode. In the parallel programming mode, the two arrays occupy one contiguous address space: 0000H to 1FFFH for the Code array and 2000H to 27FFH for the Data array. The Code and Data memory arrays on the AT89S8252 are programmed byte-by-byte in either programming mode. An auto-erase cycle is provided with the self-timed program- ming operation in the serial programming mode. There is no need to perform the Chip Erase operation to reprogram any memory location in the serial programming mode unless any of the lock bits have been programmed. In the parallel programming mode, there is no auto-erase cycle. To reprogram any non- blank byte, the user needs to use the Chip Erase operation first to erase both arrays. Parallel Programming Algorithm: To program and verify the AT89S8252 in the paral- lel programming mode, the following sequence is recommended: 1. Power-up sequence: Apply power between V CC and GND pins. Set RST pin to “H”. Apply a 3 MHz to 24 MHz clock to XTAL1 pin and wait for at least 10 milliseconds. 2. Set PSEN pin to “L” ALE pin to “H” EA pin to “H” and all other pins to “H”. 3. Apply the appropriate combination of “H” or “L” logic levels to pins P2.6, P2.7, P3.6, P3.7 to select one of the programming operations shown in the Flash Programming Modes table. Apply data to pins P0.0 to P0.7 for Write Code operation. 5. Raise EA /VPP to 12V to enable Flash programming, erase or verification. 6. Pulse ALE/PROG once to program a byte in the Code memory array, the Data mem- ory array or the lock bits. The byte-write cycle is self-timed and typically takes 1.5 ms. 7. To verify the byte just programmed, bring pin P2.7 to “L” and read the programmed data at pins P0.0 to P0.7. 8. Repeat steps 3 through 7 changing the address and data for the entire 2K or 8K bytes array or until the end of the object file is reached. 9. Power-off sequence: Set XTAL1 to “L”. Set RST and EA pins to “L”. Turn VCC power off.
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0401F–MICRO–11/03 In the parallel programming mode, there is no auto-erase cycle and to reprogram any non-blank byte, the user needs to use the Chip Erase operation first to erase both arrays. Data Polling: The AT89S8252 features DATA Polling to indicate the end of a byte write cycle. During a byte write cycle in the parallel or serial programming mode, an attempted read of the last byte written will result in the complement of the written datum on P0.7 (parallel mode), and on the MSB of the serial output byte on MISO (serial mode). Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. DATA Polling may begin any time after a write cycle has been initiated. Ready/Busy : The progress of byte programming in the parallel programming mode can also be monitored by the RDY/BSY output signal. Pin P3.4 is pulled Low after ALE goes High during programming to indicate BUSY. P3.4 is pulled High again when program- ming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed Code or Data byte can be read back via the address and data lines for verification. The state of the lock bits can also be verified directly in the parallel programming mode. In the serial programming mode, the state of the lock bits can only be verified indirectly by observing that the lock bit features are enabled. Chip Erase: Both Flash and EEPROM arrays are erased electrically at the same time. In the parallel programming mode, chip erase is initiated by using the proper combina- tion of control signals and by holding ALE/PROG low for 10 ms. The Code and Data arrays are written with all “1”s in the Chip Erase operation. In the serial programming mode, a chip erase operation is initiated by issuing the Chip Erase instruction. In this mode, chip erase is self-timed and takes about 16 ms. During chip erase, a serial read from any address location will return 00H at the data outputs. Serial Programming Fuse: A programmable fuse is available to disable Serial Pro- gramming if the user needs maximum system security. The Serial Programming Fuse can only be programmed or erased in the Parallel Programming Mode. The AT89S8252 is shipped with the Serial Programming Mode enabled. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows: (030H) = 1EH indicates manufactured by Atmel (031H) = 72H indicates 89S8252 Programming Interface Every code byte in the Flash and EEPROM arrays can be written, and the entire array can be erased, by using the appropriate combination of control signals. The write opera- tion cycle is self-timed and once initiated, will automatically time itself to completion. Most worldwide major programming vendors offer support for the Atmel AT89 microcon- troller series. Please contact your local programming vendor for the appropriate software revision.
0401F–MICRO–11/03 Serial Downloading Both the Code and Data memory arrays can be programmed using the serial SPI bus while RST is pulled to VCC . The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RST is set high, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. An auto-erase cycle is built into the self-timed programming operation (in the serial mode ONLY) and there is no need to first execute the Chip Erase instruction unless any of the lock bits have been programmed. The Chip Erase operation turns the content of every memory location in both the Code and Data arrays into FFH. The Code and Data memory arrays have separate address spaces: 0000H to 1FFFH for Code memory and 000H to 7FFH for Data memory. Either an external system clock is supplied at pin XTAL1 or a crystal needs to be con- nected across pins XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be less than 1/40 of the crystal frequency. With a 24 MHz oscillator clock, the maximum SCK frequency is 600 kHz. Serial Programming Algorithm To program and verify the AT89S8252 in the serial programming mode, the following sequence is recommended: 1. Power-up sequence: Apply power between VCC and GND pins. Set RST pin to “H”. If a crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 24 MHz clock to XTAL1 pin and wait for at least 10 milliseconds. 2. Enable serial programming by sending the Programming Enable serial instruction to pin MOSI/P1.5. The frequency of the shift clock supplied at pin SCK/P1.7 needs to be less than the CPU clock at XTAL1 divided by 40. 3. The Code or Data array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. The selected memory loca- tion is first automatically erased before new data is written. The write cycle is self- timed and typically takes less than 2.5 ms at 5V. 4. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO/P1.6. 5. At the end of a programming session, RST can be set low to commence normal operation. 6. Power-off sequence (if needed): Set XTAL1 to “L” (if a crystal is not used). Set RST to “L”. Turn V CC power off.
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0401F–MICRO–11/03 Serial Programming Instruction The Instruction Set for Serial Programming follows a 3-byte protocol and is shown in the following table: Notes: 1. DATA polling is used to indicate the end of a byte write cycle which typically takes less than 2.5 ms at 5V . 2. “aaaaa” = high order address. 3. “x” = don’t care. Instruction Set Instruction Input Format OperationByte 1 Byte 2 Byte 3 Programming Enable 1010 1100 0101 0011 xxxx xxxx Enable serial programming interface after RST goes high. Chip Erase 1010 1100 xxxx x100 xxxx xxxx Chip erase both 8K & 2K memory arrays. Read Code Memory aaaa a001 low addr xxxx xxxx Read data from Code memory array at the selected address. The 5 MSBs of the first byte are the high order address bits. The low order address bits are in the second byte. Data are available at pin MISO during the third byte. Write Code Memory aaaa a010 low addr data in Write data to Code memory location at selected address. The address bits are the 5 MSBs of the first byte together with the second byte. Read Data Memory 00aa a101 low addr xxxx xxxx Read data from Data memory array at selected address. Data are available at pin MISO during the third byte. Write Data Memory 00aa a110 low addr data in Write data to Data memory location at selected address. Write Lock Bits 1010 1100 x x111 xxxx xxxx Write lock bits. Set LB1, LB2 or LB3 = “0” to program lock bits. LB1 LB2 LB3
0401F–MICRO–11/03 Notes: 1. “h” = weakly pulled “High” internally. 2. Chip Erase and Serial Programming Fuse require a 10 ms PROG pulse. Chip Erase needs to be performed first before reprogramming any byte with a content other than FFH. 3. P3.4 is pulled Low during programming to indicate RDY/BSY . 4. “X” = don’t care Flash and EEPROM Parallel Programming Modes Mode RST PSEN ALE/PROG EA /VPP P2.6 P2.7 P3.6 P3.7 Data I/O P0.7:0 Address P2.5:0 P1.7:0 Serial Prog. Modes H h (1) h(1) x Chip Erase H L 12V H L L L X X Write (10K bytes) Memory H L 12V L H H H DIN ADDR Read (10K bytes) Memory H L H 12V L L H H DOUT ADDR Write Lock Bits: H L 12V H L H L DIN X Bit - 1 P0.7 = 0 X Bit - 2 P0.6 = 0 X Bit - 3 P0.5 = 0 X Read Lock Bits: H L H 12V H H L L DOUT X Bit - 1 @P0.2 X Bit - 2 @P0.1 X Bit - 3 @P0.0 X Read Atmel Code H L H 12V L L L L DOUT 30H Read Device Code H L H 12V L L L L DOUT 31H Serial Prog. Enable H L 12V L H L H P0.0 = 0 X Serial Prog. Disable H L 12V L H L H P0.0 = 1 X Read Serial Prog. Fuse H L H 12V H H L H @P0.0 X (2) (2) (2)
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Figure 13. Programming the Flash/EEPROM Memory Figure 14. Verifying the Flash/EEPROM Memory Figure 15. Flash/EEPROM Serial Downloading
0401F–MICRO–11/03 Flash/EEPROM Programming and Verification Waveforms – Parallel Mode Flash Programming and Verification Characteristics – Parallel Mode TA = 0°C to 70°C, VCC = 5.0V ± 10% Symbol Parameter Min Max Units VPP Programming Enable Voltage 11.5 12.5 V IPP Programming Enable Current 1.0 mA 1/tCLCL Oscillator Frequency 3 24 MHz tAVGL Address Setup to PROG Low 48t CLCL tGHAX Address Hold after PROG 48tCLCL tDVGL Data Setup to PROG Low 48t CLCL tGHDX Data Hold after PROG 48tCLCL tEHSH P2.7 (ENABLE) High to VPP 48tCLCL tSHGL VPP Setup to PROG Low 10 µs tGLGH PROG Width 1 110 µs tAVQV Address to Data Valid 48tCLCL tELQV ENABLE Low to Data Valid 48tCLCL tEHQZ Data Float after ENABLE 04 8 t CLCL tGHBL PROG High to BUSY Low 1.0 µs tWC Byte Write Cycle Time 2.0 ms
30 AT89S8252
Figure 16. Serial Programming Timing Table 11. Serial Programming Characteristics, TA = -40° C to 85° C, VCC = 4.0 - 6.0V (Unless Otherwise Noted)
0401F–MICRO–11/03 Z Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA; Ports 1, 2, 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum VCC for Power-down is 2V Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Any Pin DC Characteristics The values shown in this table are valid for TA = -40°C to 85°C and VCC = 5.0V ± 20%, unless otherwise noted. Symbol Parameter Condition Min Max Units VIL Input Low-voltage (Except EA )- 0 . 5 0 . 2 V CC - 0.1 V VIL1 Input Low-voltage (EA) -0.5 0.2 V CC - 0.3 V VIH Input High-voltage (Except XTAL1, RST) 0.2 V CC + 0.9 V CC + 0.5 V VIH1 Input High-voltage (XTAL1, RST) 0.7 V CC VCC + 0.5 V VOL Output Low-voltage (1) (Ports 1,2,3) IOL = 1.6 mA 0.5 V VOL1 Output Low-voltage (1) (Port 0, ALE, PSEN) IOL = 3.2 mA 0.5 V VOH Output High-voltage (Ports 1,2,3, ALE, PSEN) IOH = -60 µA, VCC = 5V ± 10% 2.4 V IOH = -25 µA 0.75 V CC V IOH = -10 µA0 . 9 V CC V VOH1 Output High-voltage (Port 0 in External Bus Mode) IOH = -800 µA, VCC = 5V ± 10% 2.4 V IOH = -300 µA 0.75 V CC V IOH = -80 µA0 . 9 V CC V IIL Logical 0 Input Current (Ports 1,2,3) V IN = 0.45V -50 µA ITL Logical 1 to 0 Transition Current (Ports 1,2,3) VIN = 2V, VCC = 5V ± 10% -650 µA ILI Input Leakage Current (Port 0, EA) 0.45 < VIN < VCC ±10 µA RRST Reset Pull-down Resistor 50 300 K Ω C IO Pin Capacitance Test Freq. = 1 MHz, T A = 25°C 10 pF ICC Power Supply Current Active Mode, 12 MHz 25 mA Idle Mode, 12 MHz 6.5 mA Power-down Mode (2) VCC = 6V 100 µA VCC = 3V 40 µA
32 AT89S8252
0401F–MICRO–11/03 AC Characteristics Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF . External Program and Data Memory Characteristics Symbol Parameter Variable Oscillator UnitsMin Max 1/tCLCL Oscillator Frequency 0 24 MHz tLHLL ALE Pulse Width 2t CLCL - 40 ns tAVLL Address Valid to ALE Low t CLCL - 13 ns tLLAX Address Hold after ALE Low t CLCL - 20 ns tLLIV ALE Low to Valid Instruction In 4t CLCL - 65 ns tLLPL ALE Low to PSEN Low t CLCL - 13 ns tPLPH PSEN Pulse Width 3t CLCL - 20 ns tPLIV PSEN Low to Valid Instruction In 3t CLCL - 45 ns tPXIX Input Instruction Hold after PSEN 0n s tPXIZ Input Instruction Float after PSEN tCLCL - 10 ns tPXAV PSEN to Address Valid t CLCL - 8 ns tAVIV Address to Valid Instruction In 5t CLCL - 55 ns tPLAZ PSEN Low to Address Float 10 ns tRLRH RD Pulse Width 6t CLCL - 100 ns tWLWH WR Pulse Width 6t CLCL - 100 ns tRLDV RD Low to Valid Data In 5t CLCL - 90 ns tRHDX Data Hold after RD 0n s tRHDZ Data Float after RD 2tCLCL - 28 ns tLLDV ALE Low to Valid Data In 8t CLCL - 150 ns tAVDV Address to Valid Data In 9t CLCL - 165 ns tLLWL ALE Low to RD or WR Low 3t CLCL - 50 3t CLCL + 50 ns tAVWL Address to RD or WR Low 4t CLCL - 75 ns tQVWX Data Valid to WR Transition t CLCL - 20 ns tQVWH Data Valid to WR High 7t CLCL - 120 ns tWHQX Data Hold after WR tCLCL - 20 ns tRLAZ RD Low to Address Float 0 ns tWHLH RD or WR High to ALE High t CLCL - 20 t CLCL + 25 ns
0401F–MICRO–11/03 External Program Memory Read Cycle External Data Memory Read Cycle
34 AT89S8252
0401F–MICRO–11/03 External Data Memory Write Cycle External Clock Drive Waveforms External Clock Drive Symbol Parameter VCC = 4.0V to 6.0V UnitsMin Max 1/tCLCL Oscillator Frequency 0 24 MHz tCLCL Clock Period 41.6 ns tCHCX High Time 15 ns tCLCX Low Time 15 ns tCLCH Rise Time 20 ns tCHCL Fall Time 20 ns
0401F–MICRO–11/03 Shift Register Mode Timing Waveforms AC Testing Input/Output Waveforms(1) Note: 1. AC Inputs during testing are driven at VCC - 0.5V Float Waveforms(1) Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VOH /VOL level occurs. Serial Port Timing: Shift Register Mode Test Conditions The values in this table are valid for VCC = 4.0V to 6V and Load Capacitance = 80 pF. Symbol Parameter Variable Oscillator UnitsMin Max tXLXL Serial Port Clock Cycle Time 12t CLCL µs tQVXH Output Data Setup to Clock Rising Edge 10t CLCL - 133 ns tXHQX Output Data Hold after Clock Rising Edge 2t CLCL - 117 ns tXHDX Input Data Hold after Clock Rising Edge 0 ns tXHDV Clock Rising Edge to Input Data Valid 10t CLCL - 133 ns
36 AT89S8252
0401F–MICRO–11/03 AT89S8252 TYPICAL ICC (ACTIVE) at 25°C 0 4 8 12 16 20 24 F( M H z ) V = 6.0VCC V = 5.0VCC I C C m A AT89S8252 TYPICAL ICC (IDLE) at 25°C 0.0 0.8 1.6 2.4 3.2 4.0 4.8 0 4 8 12 16 20 24 F (MHz) V=CC V=CC 6.0V 5.0V I C C m A Notes: 1. XTAL1 tied to GND for Icc (power-down) 2. Lock bits programmed
0401F–MICRO–11/03
Ordering Information
(MHz) Power Supply Ordering Code Package Operation Range 4.0V to 6.0V AT89S8252-24AC AT89S8252-24JC AT89S8252-24PC 44A 44J 40P6 Commercial (0° C to 70° C) 4.0V to 6.0V AT89S8252-24AI AT89S8252-24JI AT89S8252-24PI 44A 44J 40P6 Industrial (-40° C to 85° C) Package Type 44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 40P6 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
38 AT89S8252
0401F–MICRO–11/03 Packaging Information 44A – TQFP
2325 Orchard Parkway
San Jose, CA 95131 TITLE DRAWING NO. R REV. 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) B44A 10/5/2001 PIN 1 IDENTIFIER 0˚~7˚ PIN 1 L C A1 A2 A D e E1 E B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 11.75 12.00 12.25 D1 9.90 10.00 10.10 Note 2 E 11.75 12.00 12.25 E1 9.90 10.00 10.10 Note 2 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 e 0.80 TYP
0401F–MICRO–11/03 44J – PLCC Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. A 4.191 – 4.572 A1 2.286 – 3.048 A2 0.508 – – D 17.399 – 17.653 D1 16.510 – 16.662 Note 2 E 17.399 – 17.653 E1 16.510 – 16.662 Note 2 D2/E2 14.986 – 16.002 B 0.660 – 0.813 B1 0.330 – 0.533 e 1.270 TYP COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 1.14(0.045) X 45˚ 0.51(0.020)MAX 0.318(0.0125) 0.191(0.0075) 45˚ MAX (3X) A B1 D2/E2 B e E1 E D 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) B44J 10/04/01 San Jose, CA 95131 TITLE DRAWING NO. R REV.
40 AT89S8252
0401F–MICRO–11/03 40P6 – PDIP San Jose, CA 95131 TITLE DRAWING NO. R REV. 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) B40P6 09/28/01 PIN B REF E C L SEATING PLANE A 0º ~ 15º D e eB COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 4.826 A1 0.381 – – D 52.070 – 52.578 Note 2 E 15.240 – 15.875 E1 13.462 – 13.970 Note 2 B 0.356 – 0.559 B1 1.041 – 1.651 L 3.048 – 3.556 C 0.203 – 0.381 eB 15.494 – 17.526 e 2.540 TYP Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
Printed on recycled paper. 0401F–MICRO–11/03 xM Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. Atmel Corporation Atmel Operations San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza
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