89LV55

AT89LV55 ATMEL | Alldatasheet

Document overview

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Technical content

• Compatible with MCS-51™ Products
• 20K Bytes of Reprogrammable Flash Memory – Endurance: 1,000 Write/Erase Cycles
• Fully Static Operation: 0 Hz to 12 MHz
• Three-Level Program Memory Lock
• 256 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Three 16-bit Timer/Counters
• Eight Interrupt Sources
• Low Power Idle and Power Down Modes
• 2.7V to 6.0V Operating Range

Description

The AT89LV55 is a low-voltage, low-power CMOS 8-bit microcomputer with 20K bytes of Flash programmable and erasable read only memory. The device is manu- factured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89LV55 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control appli- cations. 0811B-B–12/97 8-Bit Microcontroller with 20K Bytes Flash AT89LV55 Pin Configurations TQFP PDIP PLCC (continued)

P2.0 - P2.7 FLASHPORT 0 LATCHRAM PROGRAM ADDRESS REGISTER BUFFER PC INCREMENTER PROGRAM COUNTER DPTR RAM ADDR. REGISTER INSTRUCTION REGISTER B REGISTER INTERRUPT, SERIAL PORT, AND TIMER BLOCKS STACK POINTERACC TMP2 TMP1 ALU PSW TIMING AND CONTROL PORT 3 LATCH PORT 3 DRIVERS P3.0 - P3.7 PORT 1 LATCH PORT 1 DRIVERS P1.0 - P1.7 OSC GND VCC PSEN ALE/PROG EA / VPP RST PORT 0 DRIVERS P0.0 - P0.7

The AT89LV55 provides the following standard features: 20K bytes of Flash, 256-bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt archi- tecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89LV55 is designed with static logic for operation down to zero frequency and sup- ports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power Down Mode saves the RAM con- tents but freezes the oscillator, disabling all other chip func- tions until the next hardware reset. The low-voltage option saves power and operates with a 2.7-volt power supply. Pin Description VCC Supply voltage. GND Ground. Port 0 Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high- impedance inputs. Port 0 can also be configured to be the multiplexed low- order address/data bus during accesses to external pro- gram and data memory. In this mode, P0 has internal pul- lups. Port 0 also receives the code bytes during Flash program- ming and outputs the code bytes during program verifica- tion. External pullups are required during program verifica- tion. Port 1 Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (I IL) because of the internal pullups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table. Port 1 also receives the low-order address bytes during Flash programming and verification. Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I IL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pul- lups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I IL) because of the pullups. Port 3 also serves the functions of various special features of the AT89LV55, as shown in the following table. Port 3 also receives the highest-order address bit and some control signals for Flash programming and verifica- tion. RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. Port Pin Alternate Functions P1.0 T2 (external count input to Timer/Counter 2), clock-out P1.1 T2EX (Timer/Counter 2 capture/reload trigger and direction control) Port Pin Alternate Functions P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2 INT0 (external interrupt 0) P3.3 INT1 (external interrupt 1) P3.4 T0 (timer 0 external input) P3.5 T1 (timer 1 external input) P3.6 WR (external data memory write strobe) P3.7 RD (external data memory read strobe)

Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external mem- ory. This pin is also the program pulse input (PROG ) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external tim- ing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data mem- ory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only dur- ing a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. PSEN Program Store Enable is the read strobe to external pro- gram memory. When the AT89LV55 is executing code from external pro- gram memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA /VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external pro- gram memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program execu- tions. This pin also receives the 12-volt programming enable volt- age (VPP ) during 12-volt Flash programming. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. Special Function Registers A map of the on-chip memory area called the Special Func- tion Register (SFR) space is shown in Table 1. Note that not all of the addresses are occupied, and unoc- cupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indetermi- nate effect. User software should not write 1s to these unlisted loca- tions, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 4) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit cap- ture mode or 16-bit auto-reload mode. Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register. Data Memory The AT89LV55 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #data Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). MOV @R0, #data Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are avail- able as stack space.

Table 1. AT89LV55 SFR Map and Reset Values

Table 2. T2CON—Timer/Counter 2 Control Register in the SFR T2CON (shown in Table 2). modes are selected by bits in T2CON, as shown in Table 3. Table 3. Timer 2 Operating Modes EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1). Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer. 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

1 X 1 Baud Rate

Figure 2. Timer 2 Auto Reload Mode (DCEN = 0) Table 4. T2MOD—Timer 2 Mode Control Register — Not implemented, reserved for future use. T20E Timer 2 Output Enable bit. DCEN When set, this bit allows Timer 2 to be configured as an up/down counter.

into its baud rate generator mode, as shown in Figure 4. and RCAP2L, which are preset by software. 2’s overflow rate according to the following equation. quency). The baud rate formula is given below. RCAP2L taken as a 16-bit unsigned integer. Figure 5. Timer 2 in Clock-Out Mode

must be set. Bit TR2 (T2CON.2) starts and stops the timer. another since they both use RCAP2H and RCAP2L. interrupts are all shown in Figure 6. disables all interrupts at once. and that bit will have to be cleared in software. Table 5. Interrupt Enable (IE) Register Figure 6. Interrupt Sources Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables the interrupt. ET2 IE.5 Timer 2 interrupt enable bit. ES IE.4 Serial Port interrupt enable bit. ET1 IE.3 Timer 1 interrupt enable bit. EX1 IE.2 External interrupt 1 enable bit. ET0 IE.1 Timer 0 interrupt enable bit. EX0 IE.0 External interrupt 0 enable bit. because they may be used in future A T89 products.

In the power down mode, the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Regis- ters retain their values until the power down mode is termi- nated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before V CC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and sta- bilize. Program Memory Lock Bits The AT89LV55 has three lock bits that can be left unpro- grammed (U) or can be programmed (P) to obtain the addi- tional features listed in the following table: Lock Bit Protection Modes When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is pow- ered up without a reset, the latch initializes to a random value and holds that value until reset is activated. The latched value of EA must agree with the current logic level at that pin in order for the device to function properly. The AT89LV55 code memory array is programmed byte- by-byte. To program any non-blank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode. Programming the Flash The AT89LV55 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. Programming Algorithm: Before programming the AT89LV55, the address, data and control signals should be set up according to the Flash programming mode table and Figure 9 and Figure 10. To program the AT89LV55, take the following steps: 1. Input the desired memory location on the address lines. 2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA /VPP to 12V 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89LV55 features Data Polling to indi- cate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the com- plement of the written data on PO.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/Busy : The progress of byte programming can also be monitored by the RDY/BUSY output signal. P3.4 is pulled low after ALE goes high during programming to indi- cate BUSY. P3.4 is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Program Lock Bits LB1 LB2 LB3 Protection Type 1 U U U No program lock features.

2 P U U MOVC instructions executed from external program memory are disabled from fetching code

bytes from internal memory, EA is sampled and latched on reset, and further programming of the Flash memory is disabled. 3 P P U Same as mode 2, but verify is also disabled. 4 P P P Same as mode 3, but external execution is also disabled.

Note: 1. Chip Erase requires a 10-ms PROG pulse. Mode RST PSEN ALE/PROG EA /VPP P2.6 P2.7 P3.6 P3.7 Write Code Data H L 12V L H H H Read Code Data H L H H L L H H Write Lock Bit-1 H L 12V H H H H Bit-2 H L 12V H H L L B i t - 3 H L 1 2 V HLHL Chip Erase H L 12V H L L L Read Signature Byte H L H H L L L L (1)

Flash Programming and Verification Characteristics TA = 0°C to 70°C, VCC = 5.0V ± 10% Flash Programming and Verification Waveforms (VPP = 12V) Symbol Parameter Min Max Units VPP Programming Enable Voltage 11.5 12.5 V IPP Programming Enable Current 1.0 mA 1/tCLCL Oscillator Frequency 3 12 MHz tAVGL Address Setup to PROG Low 48t CLCL tGHAX Address Hold After PROG 48tCLCL tDVGL Data Setup to PROG Low 48t CLCL tGHDX Data Hold After PROG 48tCLCL tEHSH P2.7 (ENABLE) High to VPP 48tCLCL tSHGL VPP Setup to PROG Low 10 µs tGHSL VPP Hold After PROG 10 µs tGLGH PROG Width 1 110 µs tAVQV Address to Data Valid 48t CLCL tELQV ENABLE Low to Data Valid 48t CLCL tEHQZ Data Float After ENABLE 0 48t CLCL tGHBL PROG High to BUSY Low 1.0 µs tWC Byte Write Cycle Time 2.0 ms

Absolute Maximum Ratings* DC Characteristics The values shown in this table are valid for TA = -40°C to 85°C and VCC = 2.7V to 6.0V, unless otherwise noted. Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA, Ports 1, 2, 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum VCC for Power Down is 2V . Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Any Pin Symbol Parameter Condition Min Max Units VIL Input Low Voltage (Except EA )- 0 . 5 0 . 2 V CC - 0.1 V VIL1 Input Low Voltage (EA)- 0 . 5 0 . 2 V CC - 0.3 V VIH Input High Voltage (Except XTAL1, RST) 0.2 V CC + 0.9 V CC + 0.5 V VIH1 Input High Voltage (XT AL1, RST) 0.7 V CC VCC + 0.5 V VOL Output Low Voltage (1) (Ports 1, 2, 3) IOL = 1.6 mA 0.45 V VOL1 Output Low Voltage (1) (Port 0, ALE, PSEN) IOL = 3.2 mA 0.45 V VOH Output High Voltage (Ports 1, 2, 3, ALE, PSEN) IOH = -60 µA, VCC = 5V ± 10% 2.4 V IOH = -25 µA 0.75 V CC V IOH = -10 µA0 . 9 V CC V VOH1 Output High Voltage (Port 0 in External Bus Mode) IOH = -800 µA, VCC = 5V ± 10% 2.4 V IOH = -300 µA 0.75 V CC V IOH = -80 µA0 . 9 V CC V IIL Logical 0 Input Current (Ports 1, 2, 3) VIN = 0.45V -50 µA ITL Logical 1 to 0 T ransition Current (Ports 1, 2, 3) VIN = 2V -650 µA ILI Input Leakage Current (Port 0, EA) 0.45 < VIN < VCC ±10 µA RRST Reset Pulldown Resistor 50 300 k Ω C IO Pin Capacitance Test Freq. = 1 MHz, T A = 25°C 10 pF ICC Power Supply Current Active Mode, 12 MHz 25 mA Idle Mode, 12 MHz 6.5 mA Power Down Mode (1) VCC = 6V 100 µA VCC = 3V 40 µA

Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF. External Program and Data Memory Characteristics Symbol Parameter 12 MHz Oscillator Variable Oscillator Units Min Max Min Max 1/tCLCL Oscillator Frequency 0 12 MHz tLHLL ALE Pulse Width 127 2t CLCL - 40 ns tAVLL Address Valid to ALE Low 43 t CLCL - 40 ns tLLAX Address Hold After ALE Low 48 t CLCL - 35 ns tLLIV ALE Low to Valid Instruction In 233 4t CLCL - 100 ns tLLPL ALE Low to PSEN Low 43 t CLCL - 40 ns tPLPH PSEN Pulse Width 205 3t CLCL - 45 ns tPLIV PSEN Low to Valid Instruction In 145 3t CLCL - 105 ns tPXIX Input Instruction Hold After PSEN 00 n s tPXIZ Input Instruction Float After PSEN 59 t CLCL - 25 ns tPXAV PSEN to Address Valid 75 t CLCL - 8 ns tAVIV Address to Valid Instruction In 312 5t CLCL - 105 ns tPLAZ PSEN Low to Address Float 10 10 ns tRLRH RD Pulse Width 400 6t CLCL - 100 ns tWLWH WR Pulse Width 400 6t CLCL - 100 ns tRLDV RD Low to Valid Data In 252 5t CLCL - 165 ns tRHDX Data Hold After RD 00 n s tRHDZ Data Float After RD 97 2t CLCL - 70 ns tLLDV ALE Low to Valid Data In 517 8t CLCL - 150 ns tAVDV Address to Valid Data In 585 9t CLCL - 165 ns tLLWL ALE Low to RD or WR Low 200 300 3t CLCL - 50 3t CLCL + 50 ns tAVWL Address to RD or WR Low 203 4t CLCL - 130 ns tQVWX Data Valid to WR T ransition 23 t CLCL - 60 ns tQVWH Data Valid to WR High 433 7t CLCL - 150 ns tWHQX Data Hold After WR 33 t CLCL - 50 ns tRLAZ RD Low to Address Float 0 0 ns tWHLH RD or WR High to ALE High 43 123 t CLCL - 40 t CLCL + 40 ns

External Program Memory Read Cycle External Data Memory Read Cycle

External Data Memory Write Cycle External Clock Drive Waveforms External Clock Drive Symbol Parameter Min Max Units 1/tCLCL Oscillator Frequency 0 12 MHz tCLCL Clock Period 83.3 ns tCHCX High Time 20 ns tCLCX Low Time 20 ns tCLCH Rise Time 20 ns tCHCL Fall Time 20 ns

Serial Port Timing: Shift Register Mode Test Conditions The values in this table are valid for VCC = 5.0V ± 20% and Load Capacitance = 80 pF. Shift Register Mode Timing Waveforms AC Testing Input/Output Waveforms (1) Note: 1. AC Inputs during testing are driven at 2.4V for a logic “1” and 0.45V for a logic “0”. Timing measure- ments are made at 2.0V for a logic “1” and 0.8V for a logic “0”. Float Waveforms (1) Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded V OH /VOL level occurs. Symbol Parameter 12 MHz Osc Variable Oscillator Units Min Max Min Max tXLXL Serial Port Clock Cycle Time 1.0 12t CLCL ns tQVXH Output Data Setup to Clock Rising Edge 700 10t CLCL - 133 ns tXHQX Output Data Hold After Clock Rising Edge 50 2t CLCL - 117 ns tXHDX Input Data Hold After Clock Rising Edge 00 n s tXHDV Clock Rising Edge to Input Data Valid 700 10t CLCL - 133 ns

Notes: 1. XT AL1 tied to GND for ICC (power down) 2. Lock bits programmed

Ordering Information

(MHz) Power Supply Ordering Code Package Operation Range 12 2.7V - 6.0V A T89LV55-12AC A T89LV55-12JC A T89LV55-12PC 44A 44J 40P6 Commercial (0°C to 70°C) A T89LV55-12AI A T89LV55-12JI A T89LV55-12PI 44A 44J 40P6 Industrial (-40°C to 85°C) Package Type 44A 44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44 Lead, Plastic J-Leaded Chip Carrier (PLCC) 40P6 40 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)