AT89LS8252 ATMEL | Alldatasheet

Document overview

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Technical content

Features

  • Compatible with MCS-51™ Products
  • 8K Bytes of In-System Reprogrammable Downloadable Flash Memory - SPI Serial Interface for Program Downloading - Endurance: 1,000 Write/Erase Cycles
  • 2K Bytes EEPROM - Endurance: 100,000 Write/Erase Cycles
  • 2.7V to 6V Operating Range
  • Fully Static Operation: 0 Hz to 12 MHz
  • Three-Level Program Memory Lock
  • 256 x 8 bit Internal RAM
  • 32 Programmable I/O Lines
  • Three 16 bit Timer/Counters
  • Nine Interrupt Sources
  • Programmable UART Serial Channel
  • SPI Serial Interface
  • Low Power Idle and Power Down Modes
  • Interrupt Recovery From Power Down
  • Programmable Watchdog Timer
  • Dual Data Pointer
  • Power Off Flag

Description

The AT89LS8252 is a low-power, wide-voltage range, high-performance CMOS 8-bit microcomputer with 8K bytes of Downloadable Flash programmable and erasable read only memory and 2K bytes of EEPROM. The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the indus- try standard 80C51 instruction set and pinout. The on-chip Downloadable Flash allows the program memory to be reprogrammed in-system through an SPI serial interface or by a conventional nonvolatile memory programmer. By combining a ver- satile 8-bit CPU with Downloadable Flash on a monolithic chip, the Atmel AT89LS8252 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. The AT89LS8252 provides the following standard features: 8K bytes of Downloadable Flash, 2K bytes of EEPROM, 256 bytes of RAM, 32 I/O lines, programmable watch- dog timer, two Data Pointers, three 16-bit timer/counters, a six-vector two-level inter- rupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89LS8252 is designed with static logic for operation down to zero fre- quency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt sys- tem to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hard- ware reset. The Downloadable Flash can be changed a single byte at a time and is accessible through the SPI serial interface. Holding RESET active forces the SPI bus into a serial programming interface and allows the program memory to be written to or read from unless Lock Bit 2 has been activated. 0850B-B–12/97

Supply voltage. GND Ground. Port 0 Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high- impedance inputs. Port 0 can also be configured to be the multiplexed low- order address/data bus during accesses to external pro- gram and data memory. In this mode, P0 has internal pul- lups. Port 0 also receives the code bytes during Flash program- ming and outputs the code bytes during program verifica- tion. External pullups are required during program verifica- tion. Port 1 Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (I IL) because of the internal pullups. Some Port 1 pins provide additional functions. P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively. Pin Configurations PDIP (T2) P1.0 (T2 EX) P1.1 P1.2 P1.3 (SS) P1.4 (MOSI) P1.5 (MISO) P1.6 (SCK) P1.7 RST (RXD) P3.0 (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 (WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8) PLCC (MOSI) P1.5 (MISO) P1.6 (SCK) P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) (WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND NC (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4 P1.4 (SS) P1.3 P1.2 P1.1 (T2 EX) P1.0 (T2) NC VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) TQFP (MOSI) P1.5 (MISO) P1.6 (SCK) P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P1.4 (SS) P1.3 P1.2 P1.1 (T2 EX) P1.0 (T2) NC VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) (WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND GND (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4

P2.0 - P2.7 FLASHPORT 0 LATCHRAMEEPROM PROGRAM ADDRESS REGISTER BUFFER PC INCREMENTER PROGRAM COUNTER DPTRINSTRUCTION REGISTER B REGISTER INTERRUPT, SERIAL PORT, AND TIMER BLOCKS STACK POINTERACC TMP2 TMP1 ALU PSW TIMING AND CONTROL PORT 1 DRIVERS P1.0 - P1.7 PORT 3 LATCH PORT 3 DRIVERS P3.0 - P3.7 OSC GND VCC PSEN ALE/PROG EA / VPP RST RAM ADDR. REGISTER PORT 0 DRIVERS P0.0 - P0.7 PORT 1 LATCH WATCH DOG SPI PORT PROGRAM LOGIC

Furthermore, P1.4, P1.5, P1.6, and P1.7 can be configured as the SPI slave port select, data input/output and shift clock input/output pins as shown in the following table. Port 1 also receives the low-order address bytes during Flash programming and verification. Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I IL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pul- lups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8 bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I IL) because of the pullups. Port 3 also serves the functions of various special features of the AT89LS8252, as shown in the following table. Port 3 also receives some control signals for Flash pro- gramming and verification. RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE/PROG Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external mem- ory. This pin is also the program pulse input (PROG ) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/ 6 the oscillator frequency and may be used for external tim- ing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data mem- ory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only dur- ing a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. PSEN Program Store Enable is the read strobe to external pro- gram memory. When the AT89LS8252 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA /VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external pro- gram memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program execu- tions. This pin also receives the 12-volt programming enable voltage (VPP ) during Flash programming when 12- volt programming is selected. Port Pin Alternate Functions P1.0 T2 (external count input to Timer/Counter 2), clock-out P1.1 T2EX (Timer/Counter 2 capture/reload trigger and direction control) P1.4 SS (Slave port select input) P1.5 MOSI (Master data output, slave data input pin for SPI channel) P1.6 MISO (Master data input, slave data output pin for SPI channel) P1.7 SCK (Master clock output, slave clock input pin for SPI channel) Port Pin Alternate Functions P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2 INT0 (external interrupt 0) P3.3 INT1 (external interrupt 1) P3.4 T0 (timer 0 external input) P3.5 T1 (timer 1 external input) P3.6 WR (external data memory write strobe) P3.7 RD (external data memory read strobe)

Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. Special Function Registers A map of the on-chip memory area called the Special Func- tion Register (SFR) space is shown in Table 1. Note that not all of the addresses are occupied, and unoc- cupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. Table 1.AT89LS8252 SFR Map and Reset Values 0F8H 0FFH 0F0H B 00000000 0F7H 0E8H 0EFH 0E0H ACC 00000000 0E7H 0D8H 0DFH 0D0H PSW 00000000 SPCR 000001XX 0D7H 0C8H T2CON 00000000 T2MOD XXXXXX00 RCAP2L 00000000 RCAP2H 00000000 TL2 00000000 TH2 00000000 0CFH 0C0H 0C7H 0B8H IP XX000000 0BFH 0B0H P3 11111111 0B7H 0A8H IE 0X000000 SPSR 00XXXXXX 0AFH 0A0H P2 11111111 0A7H 98H SCON 00000000 SBUF XXXXXXXX 9FH 90H P1 11111111 WMCON 00000010 97H 88H TCON 00000000 TMOD 00000000 TL0 00000000 TL1 00000000 TH0 00000000 TH1 00000000 8FH 80H P0 11111111 SP 00000111 DP0L 00000000 DP0H 00000000 DP1L 00000000 DP1H 00000000 SPDR XXXXXXXX PCON 0XXX0000 87H

User software should not write 1s to these unlisted loca- tions, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. Timer 2 Registers Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 9) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16 bit cap- ture mode or 16-bit auto-reload mode. Watchdog and Memory Control Register The WMCON register contains control bits for the Watchdog Timer (shown in Table 3). The EEMEN and EEMWE bits are used to select the 2K bytes on-chip EEPROM, and to enable byte-write. The DPS bit selects one of two DPTR registers available. SPI Registers Control and status bits for the Serial Periph- eral Interface are contained in registers SPCR (shown in Table 4) and SPSR (shown in Table 5). The SPI data bits are contained in the SPDR register. Writing the SPI data register during serial data transfer sets the Write Collision bit, WCOL, in the SPSR register. The SPDR is double buff- ered for writing and the values in SPDR are not changed by Reset. Interrupt Registers The global interrupt enable bit and the individual interrupt enable bits are in the IE register. In addi- tion, the individual interrupt enable bit for the SPI is in the SPCR register. Two priorities can be set for each of the six interrupt sources in the IP register. Table 2.T2CON—Timer/Counter 2 Control Register T2CON Address = 0C8H Reset Value = 0000 0000B Bit Addressable TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 B i t 76543210 Symbol Function TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1 or TCLK = 1. EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1). RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflows to be used for the receive clock. TCLK T ransmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer. C/T2 Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered). CP/RL2 Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

Dual Data Pointer Registers To facilitate accessing both internal EEPROM and external data memory, two banks of 16 bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR WMCON selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register. Power Off Flag The Power Off Flag (POF) is located at bit_4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and reset under software control and is not affected by RESET. Table 3.WMCON—Watchdog and Memory Control Register WMCON Address = 96H Reset Value = 0000 0010B PS2 PS1 PS0 EEMWE EEMEN DPS WDTRST WDTEN B i t 76543210 Symbol Function PS2 PS1 PS0 Prescaler Bits for the Watchdog Timer. When all three bits are set to “0”, the watchdog timer has a nominal period of 16 ms. When all three bits are set to “1”, the nominal period is 2048 ms. EEMWE EEPROM Data Memory Write Enable Bit. Set this bit to “1” before initiating byte write to on-chip EEPROM with the MOVX instruction. User software should set this bit to “0” after EEPROM write is completed. EEMEN Internal EEPROM Access Enable. When EEMEN = 1, the MOVX instruction with DPTR will access on-chip EEPROM instead of external data memory. When EEMEN = 0, MOVX with DPTR accesses external data memory. DPS Data Pointer Register Select. DPS = 0 selects the first bank of Data Pointer Register, DP0, and DPS = 1 selects the second bank, DP1 WDTRST RDY/BSY Watchdog Timer Reset and EEPROM Ready/Busy Flag. Each time this bit is set to “1” by user software, a pulse is generated to reset the watchdog timer. The WDTRST bit is then automatically reset to “0” in the next instruction cycle. The WDTRST bit is Write-Only. This bit also serves as the RDY/BSY flag in a Read- Only mode during EEPROM write. RDY/BSY = 1 means that the EEPROM is ready to be programmed. While programming operations are being executed, the RDY/BSY bit equals “0” and is automatically reset to “1” when programming is completed. WDTEN Watchdog Timer Enable Bit. WDTEN = 1 enables the watchdog timer and WDTEN = 0 disables the watchdog timer.

Table 4. SPCR—SPI Control Register = 1 and ES = 1 enable SPI interrupts. SPIE = 0 disables SPI interrupts. P1.6, and P1.7. SPI = 0 disables the SPI channel. DORD Data Order. DORD = 1 selects LSB first data transmission. DORD = 0 selects MSB first data transmission. MSTR Master/Slave Select. MSTR = 1 selects Master SPI mode. MSTR = 0 selects Slave SPI mode. when not transmitting. Please refer to figure on SPI Clock Phase and Polarity Control. master and slave. Please refer to figure on SPI Clock Phase and Polarity Control. set, and then accessing the SPI data register. then accessing the SPI data register.

physically separate from SFR space. addressing access SFR space. accesses the SFR at location 0A0H (which is P2). instructions, the EEMEN bit needs to be set to “0”. “1” before any byte location in the EEPROM can be written. bit (read-only) in SFR WMCON. and another write cycle can be initiated. pleted, true data are valid at all bit locations. Table 7. Watchdog Timer Period Selection Table 6. SPDR—SPI Data Register

in the SFR T2CON (shown in Table 2). modes are selected by bits in T2CON, as shown in Table 8. or counter which upon overflow sets bit TF2 in T2CON. Table 8. Timer 2 Operating Modes Figure 1. Timer 2 in Capture Mode

into its baud rate generator mode, as shown in Figure 4. and RCAP2L, which are preset by software. 2’s overflow rate according to the following equation. quency). The baud rate formula is given below. RCAP2L taken as a 16 bit unsigned integer. an extra external interrupt. Figure 5. Timer 2 in Clock-Out Mode

must be set. Bit TR2 (T2CON.2) starts and stops the timer. (RCAP2H, RCAP2L), as shown in the following equation. another since they both use RCAP2H and RCAP2L.

  • Full-Duplex, 3-Wire Synchronous Data Transfer
  • Master or Slave Operation
  • 1.5-MHz Bit Frequency (max.)
  • LSB First or MSB First Data T ransfer
  • Four Programmable Bit Rates
  • End of T ransmission Interrupt Flag
  • Write Collision Flag Protection
  • Wakeup from Idle Mode (Slave Mode Only) Clock-Out Frequency Oscillator Frequency

Figure 6. SPI Block Diagram

The AT89LS8252 has three lock bits that can be left unpro- grammed (U) or can be programmed (P) to obtain the addi- tional features listed in the following table. When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is pow- ered up without a reset, the latch initializes to a random value and holds that value until reset is activated. The latched value of EA must agree with the current logic level at that pin in order for the device to function properly. Once programmed, the lock bits can only be unpro- grammed with the Chip Erase operations in either the par- allel or serial modes. Lock Bit Protection Modes (1) (2) Notes: 1. U = Unprogrammed 2. P = Programmed Program Lock Bits Protection TypeLB1 LB2 LB3 1 U U U No internal memory lock feature. 2PUU MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. EA is sampled and latched on reset and further programming of the Flash memory (parallel or serial mode) is disabled. 3 P P U Same as Mode 2, but parallel or serial verify are also disabled. 4 P P P Same as Mode 3, but external execution is also disabled. Programming the Flash and EEPROM Atmel’s AT89LS8252 Flash Microcontroller offers 8K bytes of in-system reprogrammable Flash Code memory and 2K bytes of EEPROM Data memory. The AT89LS8252 is normally shipped with the on-chip Flash Code and EEPROM Data memory arrays in the erased state (i.e. contents = FFH) and ready to be pro- grammed. This device supports a High-Voltage (12V) Par- allel programming mode and a Low-Voltage (2.7V to 6V) Serial programming mode. The serial programming mode provides a convenient way to download the AT89LS8252 inside the user’s system. The parallel programming mode is compatible with conventional third party Flash or EPROM programmers. The Code and Data memory arrays are mapped via sepa- rate address spaces in the serial programming mode. In the parallel programming mode, the two arrays occupy one contiguous address space: 0000H to 1FFFH for the Code array and 2000H to 27FFH for the Data array. The Code and Data memory arrays on the AT89LS8252 are programmed byte-by-byte in either programming mode. An auto-erase cycle is provided with the self-timed pro- gramming operation in the serial programming mode. There is no need to perform the Chip Erase operation to reprogram any memory location in the serial programming mode unless any of the lock bits have been programmed. In the parallel programming mode, there is no auto-erase cycle. To reprogram any non-blank byte, the user needs to use the Chip Erase operation first to erase both arrays. Parallel Programming Algorithm To program and verify the AT89LS8252 in the parallel pro- gramming mode, the following sequence is recommended: 1. Power-up sequence: Apply power between VCC and GND pins. Set RST pin to “H”. Apply a 3 MHz to 12 MHz clock to XTAL1 pin and wait for at least 10 milliseconds. 2. Set PSEN pin to “L” ALE pin to “H” EA pin to “H” and all other pins to “H”. 3. Apply the appropriate combination of “H” or “L” logic levels to pins P2.6, P2.7, P3.6, P3.7 to select one of the programming operations shown in the Flash Programming Modes table. 4. Apply the desired byte address to pins P1.0 to P1.7 and P2.0 to P2.5. Apply data to pins P0.0 to P0.7 for Write Code opera- tion. 5. Raise EA/VPP to 12V to enable Flash programming, erase or verification. 6. Pulse ALE/PROG once to program a byte in the Code memory array, the Data memory array or the lock bits. The byte-write cycle is self-timed and typi- cally takes 1.5 ms.

  1. T o verify the byte just programmed, bring pin P2.7 to “L” and read the programmed data at pins P0.0 to P0.7. 8. Repeat steps 3 through 7 changing the address and data for the entire 2K or 8K bytes array or until the end of the object file is reached. 9. Power-off sequence: Set XT AL1 to “L”. Set RST and EA pins to “L”. Tu r n VCC power off. In the parallel programming mode, there is no auto-erase cycle and to reprogram any non-blank byte, the user needs to use the Chip Erase operation first to erase both arrays. DATA Polling The AT89LS8252 features DA T A Polling to indicate the end of a write cycle. During a write cycle in the parallel or serial programming mode, an attempted read of the last byte writ- ten will result in the complement of the written datum on P0.7 (parallel mode), and on the MSB of the serial output byte on MISO (serial mode). Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. DA T A Polling may begin any time after a write cycle has been initiated. Ready/Busy The progress of byte programming in the parallel program- ming mode can also be monitored by the RDY/BSY output signal. Pin P3.4 is pulled Low after ALE goes High during programming to indicate BUSY . P3.4 is pulled High again when programming is done to indicate READY. Program Verify If lock bits LB1 and LB2 have not been programmed, the programmed Code or Data byte can be read back via the address and data lines for verification. The state of the lock bits can also be verified directly in the parallel programming mode. In the serial programming mode, the state of the lock bits can only be verified indirectly by observing that the lock bit features are enabled. Chip Erase Both Flash and EEPROM arrays are erased electrically at the same time. In the parallel programming mode, chip erase is initiated by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The Code and Data arrays are written with all “1”s in the Chip Erase operation. In the serial programming mode, a chip erase operation is initiated by issuing the Chip Erase instruction. In this mode, chip erase is self-timed and takes about 16 ms. During chip erase, a serial read from any address location will return 00H at the data outputs. Serial Programming Fuse A programmable fuse is available to disable Serial Pro- gramming if the user needs maximum system security. The Serial Programming Fuse can only be programmed or erased in the Parallel Programming Mode. The AT89LS8252 is shipped with the Serial Programming Mode enabled. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows: (030H) = 1EH indicates manufactured by Atmel (031H) = 82H indicates 89LS8252 Programming Interface Every code byte in the Flash and EEPROM arrays can be written, and the entire array can be erased, by using the appropriate combination of control signals. The write oper- ation cycle is self-timed and once initiated, will automati- cally time itself to completion. All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision. Serial Downloading Both the Code and Data memory arrays can be pro- grammed using the serial SPI bus while RST is pulled to V CC . The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RST is set high, the Programming Enable instruction needs to be executed first before pro- gram/erase operations can be executed. An auto-erase cycle is built into the self-timed programming operation (in the serial mode ONLY) and there is no need to first execute the Chip Erase instruction unless any of the lock bits have been programmed. The Chip Erase opera- tion turns the content of every memory location in both the Code and Data arrays into FFH. The Code and Data memory arrays have separate address spaces: 0000H to 1FFFH for Code memory and 000H to 7FFH for Data memory. Either an external system clock is supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be less than 1/40 of the crystal frequency. With a 12 MHz oscillator clock, the maximum SCK frequency is 300 kHz.

Notes: 1. DAT A polling is used to indicate the end of a write cycle which typically takes less than 10 ms at 2.7V . 2. “aaaaa” = high order address. 3. “x” = don’t care. Instruction Input Format OperationByte 1 Byte 2 Byte 3 Programming Enable 1010 1100 0101 0011 xxxx xxxx Enable serial programming interface after RST goes high. Chip Erase 1010 1100 xxxx x100 xxxx xxxx Chip erase both 8K & 2K memory arrays. Read Code Memory aaaa a001 low addr xxxx xxxx Read data from Code memory array at the selected address. The 5 MSBs of the first byte are the high order address bits. The low order address bits are in the second byte. Data are available at pin MISO during the third byte. Write Code Memory aaaa a010 low addr data in Write data to Code memory location at selected address. The address bits are the 5 MSBs of the first byte together with the second byte. Read Data Memory 00aa a101 low addr xxxx xxxx Read data from Data memory array at selected address. Data are available at pin MISO during the third byte. Write Data Memory 00aa a110 low addr data in Write data to Data memory location at selected address. Write Lock Bits 1010 1100 x x111 xxxx xxxx Write lock bits. Set LB1, LB2 or LB3 = “0” to program lock bits. Serial Programming Algorithm To program and verify the AT89LS8252 in the serial pro- gramming mode, the following sequence is recommended: 1. Power-up sequence: Apply power between VCC and GND pins. Set RST pin to “H”. If a crystal is not connected across pins XT AL1 and XTAL2, apply a 3 MHz to 12 MHz clock to XTAL1 pin and wait for at least 10 milliseconds. 2. Enable serial programming by sending the Pro- gramming Enable serial instruction to pin MOSI/ P1.5. The frequency of the shift clock supplied at pin SCK/P1.7 needs to be less than the CPU clock at XT AL1 divided by 40. 3. The Code or Data array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. The selected memory location is first automatically erased before new data is written. The write cycle is self-timed and typically takes less than 2.5 ms at 5V and less than 10 ms at 2.7V . 4. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO/P1.6. 5. At the end of a programming session, RST can be set low to commence normal operation. Power-off sequence (if needed): Set XT AL1 to “L” (if a crystal is not used). Set RST to “L”. Tu r n V CC power off. Serial Programming Instruction The Instruction Set for Serial Programming follows a 3-byte protocol and is shown in the following table: LB1 LB2 LB3

Flash and EEPROM Parallel Programming Modes Notes: 1. “h” = weakly pulled “High” internally. 2. Chip Erase and Serial Programming Fuse require a 10-ms PROG pulse. Chip Erase needs to be performed first before reprogramming any byte with a content other than FFH. 3. P3.4 is pulled Low during programming to indicate RDY/BSY . 4. “X” = don’t care Mode RST PSEN ALE/PROG EA /VPP P2.6 P2.7 P3.6 P3.7 Data I/O P0.7:0 Address P2.5:0 P1.7:0 Serial Prog. Modes H h (1) h (1) x Chip Erase H L 12V H L L L X X Write (10K bytes) Memory H L 12V L H H H DIN ADDR Read (10K bytes) Memory H L H 12V L L H H DOUT ADDR Write Lock Bits: H L 12V H L H L DIN X Bit - 1 P0.7 = 0 X Bit - 2 P0.6 = 0 X Bit - 3 P0.5 = 0 X Read Lock Bits: H L H 12V H H L L DOUT X Bit - 1 @P0.2 X Bit - 2 @P0.1 X Bit - 3 @P0.0 X Read Atmel Code H L H 12V L L L L DOUT 30H Read Device Code H L H 12V L L L L DOUT 31H Serial Prog. Enable H L 12V L H L H P0.0 = 0 X Serial Prog. Disable H L 12V L H L H P0.0 = 1 X Read Serial Prog. Fuse H L H 12V H H L H @P0.0 X (2) (2) (2)

Flash Programming and Verification Characteristics - Parallel Mode TA = 0°C to 70°C, VCC = 5.0V ± 10% Symbol Parameter Min Max Units VPP Programming Enable Voltage 11.5 12.5 V IPP Programming Enable Current 1.0 mA 1/tCLCL Oscillator Frequency 3 12 MHz tAVGL Address Setup to PROG Low 48t CLCL tGHAX Address Hold After PROG 48tCLCL tDVGL Data Setup to PROG Low 48t CLCL tGHDX Data Hold After PROG 48tCLCL tEHSH P2.7 (ENABLE) High to VPP 48tCLCL tSHGL VPP Setup to PROG Low 10 µs tGLGH PROG Width 1 110 µs tAVQV Address to Data Valid 48t CLCL tELQV ENABLE Low to Data Valid 48t CLCL tEHQZ Data Float After ENABLE 0 48t CLCL tGHBL PROG High to BUSY Low 1.0 µs tWC Byte Write Cycle Time 2.0 ms

Flash/EEPROM Programming and Verification Waveforms - Parallel Mode Serial Downloading Waveforms

Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Any Pin DC Characteristics The values shown in this table are valid for TA = -40°C to 85°C and VCC = 2.7V to 6.0V, unless otherwise noted. Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum I OL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1,2, 3: 15 mA Maximum total I OL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum VCC for Power Down is 2V Symbol Parameter Condition Min Max Units VIL Input Low Voltage (Except EA )- 0 . 5 0 . 2 V CC - 0.1 V VIL1 Input Low Voltage (EA)- 0 . 5 0 . 2 V CC - 0.3 V VIH Input High Voltage (Except XT AL1, RST) 0.2 V CC + 0.9 V CC + 0.5 V VIH1 Input High Voltage (XT AL1, RST) 0.7 V CC VCC + 0.5 V VOL Output Low Voltage (1) (Ports 1,2,3) IOL = 1.6 mA 0.5 V VOL1 Output Low Voltage (1) (Port 0, ALE, PSEN) IOL = 3.2 mA 0.5 V VOH Output High Voltage (Ports 1,2,3, ALE, PSEN) IOH = -60 µA, VCC = 5V ± 10% 2.4 V IOH = -25 µA0 . 7 5 V CC V IOH = -10 µA 0.9 V CC V VOH1 Output High Voltage (Port 0 in External Bus Mode) IOH = -800 µA, VCC = 5V ± 10% 2.4 V IOH = -300 µA0 . 7 5 V CC V IOH = -80 µA 0.9 V CC V IIL Logical 0 Input Current (Ports 1,2,3) V IN = 0.45V -50 µA ITL Logical 1 to 0 T ransition Current (Ports 1,2,3) VIN = 2V -650 µA ILI Input Leakage Current (Port 0, EA) 0.45 < VIN < VCC ±10 µA RRST Reset Pulldown Resistor 50 300 K Ω C IO Pin Capacitance T est Freq. = 1 MHz, T A = 25°C 10 pF ICC Power Supply Current Active Mode, 12 MHz 25 mA Idle Mode, 12 MHz 6.5 mA Power Down Mode (2) VCC = 6V 100 µA VCC = 3V 40 µA

Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF. External Program and Data Memory Characteristics Symbol Parameter 12MHz Oscillator Variable Oscillator UnitsMin Max Min Max 1/tCLCL Oscillator Frequency 0 12 MHz tLHLL ALE Pulse Width 127 2t CLCL - 40 ns tAVLL Address Valid to ALE Low 43 t CLCL - 40 ns tLLAX Address Hold After ALE Low 48 t CLCL - 35 ns tLLIV ALE Low to Valid Instruction In 233 4t CLCL - 100 ns tLLPL ALE Low to PSEN Low 43 t CLCL - 40 ns tPLPH PSEN Pulse Width 205 3t CLCL - 45 ns tPLIV PSEN Low to Valid Instruction In 145 3t CLCL - 105 ns tPXIX Input Instruction Hold After PSEN 00 n s tPXIZ Input Instruction Float After PSEN 59 t CLCL - 25 ns tPXAV PSEN to Address Valid 75 t CLCL - 8 ns tAVIV Address to Valid Instruction In 312 5t CLCL - 105 ns tPLAZ PSEN Low to Address Float 10 10 ns tRLRH RD Pulse Width 400 6t CLCL - 100 ns tWLWH WR Pulse Width 400 6t CLCL - 100 ns tRLDV RD Low to Valid Data In 252 5t CLCL - 165 ns tRHDX Data Hold After RD 00 n s tRHDZ Data Float After RD 97 2t CLCL - 70 ns tLLDV ALE Low to Valid Data In 517 8t CLCL - 150 ns tAVDV Address to Valid Data In 585 9t CLCL - 165 ns tLLWL ALE Low to RD or WR Low 200 300 3t CLCL - 50 3t CLCL + 50 ns tAVWL Address to RD or WR Low 203 4t CLCL - 130 ns tQVWX Data Valid to WR Transition 23 t CLCL - 60 ns tQVWH Data Valid to WR High 433 7t CLCL - 150 ns tWHQX Data Hold After WR 33 t CLCL - 50 ns tRLAZ RD Low to Address Float 0 0 ns tWHLH RD or WR High to ALE High 43 123 t CLCL - 40 t CLCL + 40 ns

External Program Memory Read Cycle External Data Memory Read Cycle

External Data Memory Write Cycle External Clock Drive Waveforms External Clock Drive Symbol Parameter VCC = 2.7V to 6.0V UnitsMin Max 1/tCLCL Oscillator Frequency 0 12 MHz tCLCL Clock Period 83.3 ns tCHCX High Time 30 ns tCLCX Low Time 30 ns tCLCH Rise Time 20 ns tCHCL Fall Time 20 ns

Serial Port Timing: Shift Register Mode Test Conditions The values in this table are valid for VCC = 2.7V to 6V and Load Capacitance = 80 pF. Symbol Parameter

12 MHz Oscillator Variable Oscillator

tXLXL Serial Port Clock Cycle Time 1.0 12t CLCL µs tQVXH Output Data Setup to Clock Rising Edge 700 10t CLCL - 133 ns tXHQX Output Data Hold After Clock Rising Edge 50 2t CLCL - 117 ns tXHDX Input Data Hold After Clock Rising Edge 00 n s tXHDV Clock Rising Edge to Input Data Valid 700 10t CLCL - 133 ns Shift Register Mode Timing Waveforms AC Testing Input/Output Waveforms (1) Notes: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing mea- surements are made at VIH min. for a logic 1 and VIL max. for a logic 0. Float Waveforms (1) Notes: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VOH /VOL level occurs.

TYPICAL ICC (ACTIVE) at 25°C 0 4 8 12 16 20 24 F (MHz) V = 6.0VCC V = 5.0VCC V = 3.0VCC I C C m A 3.0V 4.0V 5.0V 6.0V I C C µ A AT89LS8252 TYPICAL ICC vs. VOLTAGE - POWER DOWN (85°C) V VOLTAGECC AT89LS8252 TYPICAL ICC (IDLE) at 25°C 0.0 0.8 1.6 2.4 3.2 4.0 4.8 0 4 8 12 16 20 24 F (MHz) V=CC V=CC 6.0V 5.0V I C C m A V=CC 3.0V Notes: 1. XT AL1 tied to GND for ICC (power down) 2. Lock bits programmed

Ordering Information

(MHz) Power Supply Ordering Code Package Operation Range 12 2.7V to 6.0V A T89LS8252-12AC A T89LS8252-12JC A T89LS8252-12PC 44A 44J 40P6 Commercial (0°C to 70°C) 2.7V to 6.0V A T89LS8252-12AI A T89LS8252-12JI A T89LS8252-12PI 44A 44J 40P6 Industrial (-40°C to 85°C) Package Type 44A 44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44 Lead, Plastic J-Leaded Chip Carrier (PLCC) 40P6 40 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)