AT83SND1C ATMEL | Alldatasheet
Document overview
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Technical content
Features
- MPEG I/II-Layer 3 Hardwired Decoder – Stand-alone MP3 Decoder – 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency – Separated Digital Volume Control on Left and Right Channels (Software Control using 31 Steps) – Bass, Medium, and Treble Control (31 Steps) – Bass Boost Sound Effect – Ancillary Data Extraction – CRC Error and MPEG Frame Synchronization Indicators Programmable Audio Output for Interfacing with Common Audio DAC – PCM Format Compatible –I 2S Format Compatible 8-bit MCU C51 Core Based (FMAX = 20 MHz) 2304 Bytes of Internal RAM 64K Bytes of Code Memory – AT89C51SND1C: Flash (100K Erase/Write Cycles) – AT83SND1C: ROM 4K Bytes of Boot Flash Memory (AT89C51SND1C) – ISP: Download from USB (standard) or UART (option) External Code Memory – AT80C51SND1C: ROMless USB Rev 1.1 Controller – Full Speed Data Transmission Built-in PLL – MP3 Audio Clocks –U S B C l o c k MultiMedia Card® Interface Compatibility Atmel DataFlash® SPI Interface Compatibility IDE/ATAPI Interface 2 Channels 10-bit ADC, 8 kHz (8-true bit) – Battery Voltage Monitoring – Voice Recording Controlled by Software Up to 44 Bits of General-purpose I/Os – 4-bit Interrupt Keyboard Port for a 4 x n Matrix –S m a r t M e d i a® Software Interface 2 Standard 16-bit Timers/Counters Hardware Watchdog Timer Standard Full Duplex UART with Baud Rate Generator Two Wire Master and Slave Modes Controller SPI Master and Slave Modes Controller Power Management – Power-on Reset – Software Programmable MCU Clock – Idle Mode, Power-down Mode Operating Conditions: –3 V , ±10%, 25 mA Typical Operating at 25°C – Temperature Range: -40°C to +85°C Packages – TQFP80, BGA81, PLCC84 (Development Board) –D i c e Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface AT83SND1C AT89C51SND1C AT80C51SND1C 4109JS–8051–10/06
4109JS–8051–10/06 AT8xC51SND1C 1. Description The AT8xC51SND1C are fully integrated stand-alone hardwired MPEG I/II-Layer 3 decoder with a C51 microcontroller core handling data flow and MP3-player control. The AT89C51SND1C includes 64K Bytes of Flash memory and allows In-System Programming through an embedded 4K Bytes of Boot Flash memory. The AT83SND1C includes 64K Bytes of ROM memory. The AT80C51SND1C does not include any code memory. The AT8xC51SND1C include 2304 Bytes of RAM memory. The AT8xC51SND1C provides the necessary features for human interface like timers, keyboard port, serial or parallel interface (USB, TWI, SPI, IDE), ADC input, I 2S output, and all external memory interface (NAND or NOR Flash, SmartMedia, MultiMedia, DataFlash cards). 2. Typical Applications M P 3 - P l a y e r PDA, Camera, Mobile Phone MP3 Car Audio/Multimedia MP3 Home Audio/Multimedia MP3 3. Block Diagram Figure 3-1. AT8xC51SND1C Block Diagram 8-Bit Internal Bus Clock and PLL Unit C51 (X2 Core) RAM
2304 Bytes
KIN3:0 I2S/PCM Audio Interface AVSSAVDD
1 Alternate function of Port 1
AIN1:0 Ports INT0 INT1 MOSIMISO
3 Alternate function of Port 3
4 Alternate function of Port 4
64 KBytes
4 KBytes
4109JS–8051–10/06 AT8xC51SND1C 4. Pin Description
4.1 Pinouts
Figure 4-1. AT8xC51SND1C 80-pin QFP Package Notes: 1. ISP pin is only available in AT89C51SND1C product. Do not connect this pin on AT83SND1C product. 2. PSEN pin is only available in AT80C51SND1C product. AT89C51SND1C-RO (FLASH) AT83SND1C-RO (ROM) AT80C51SND1C-RO (ROMLESS) P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS VDD P0.6/AD6 P0.7/AD7 P2.0/A8 P2.1/A9 P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.0/RXD P2.2/A10 P2.3/A11 P2.4/A12 P2.6/A14 P2.5/A13 P2.7/A15 MCLK MDAT MCMD P0.2/AD2 P0.1/AD1 P0.0/AD0 PVSS VSS TST VSS P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO VSS VDD RST SCLK DSEL DCLK DOUT AIN1 AIN0 AREFN AREFP AVSS AVDD P3.7/RD P3.6/WR P3.5/T1 VDD P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P1.4 P1.5 P1.7/SDA FILT PVDD VDD P1.6/SCL ALE ISP1/PSEN2/NC UVDD UVSS P5.0 P5.1 P4.7 P4.6 P5.3 P5.2 VSS VDD P4.5 P4.4
4109JS–8051–10/06 AT8xC51SND1C Figure 4-2. AT8xC51SND1C 81-pin BGA Package Notes: 1. ISP pin is only available in AT89C51SND1C product. Do not connect this pin on AT83SND1C and AT80C51SND1C product. 2. PSEN pin is only available in AT80C51SND1C product. P5.0 897 6 5 4 3 2 C B A D E F G H ALE P1.1 P1.4 VDD VSS UVDD ISP1/ P1.5 PVSS TST VSS P0.0/ P1.0/ P1.7/ PVDD UVSS VDD P3.1/ P3.0/ P0.2/ P5.1 P1.6/ FILT P3.4/ P3.5/ P3.3/ P3.2/ VDD P0.1/ VSS P0.5/ AVDD P3.7/ AIN0 P3.6/ P4.2/ P4.3/ P0.6 P0.7/ P2.7/ MDAT P5.3 AVSS AREFN P4.0/ P4.1/ P2.1/ P4.5 VSS MCLK DOUT AIN1 AREFP P2.0/ P4.7 P2.2/ P2.6/ P2.3/ MCMD SCLK VSS P5.2 P4.6 P4.4 P2.5/ P2.4/ VDD RST DSEL DCLK VDD J KIN0 P1.3/ KIN3 P1.2/ KIN2 SSMOSI MISO SCK AD2 P0.3/ AD3A8 P0.4/ AD4 AD0AD1 AD7 AD5 A9A10 A12 A11 A13 A14 A15 SCL SDA RXD TXD INT0 INT1 RD WR PSEN2 NC
4.2 Signals
All the AT8xC51SND1C signals are detailed by functionality in Table 1 to Table 14. Table 1. Ports Signal Description P1 is an 8-bit bidirectional I/O port with internal pull-ups.
Table 2. Clock Signal Description Table 3. Timer 0 and Timer 1 Signal Description P3 is an 8-bit bidirectional I/O port with internal pull-ups. P4 is an 8-bit bidirectional I/O port with internal pull-ups. pin. X1 is the clock source for internal timing. this pin. If an external oscillator is used, leave X2 unconnected.
Table 4. Audio Interface Signal Description Table 5. USB Controller Signal Description Table 6. MutiMediaCard Interface Signal Description (DOUT) and the channel selection signal (DSEL). unused MDAT input must be polarized to VDD or VSS.
Table 7. UART Signal Description Table 8. SPI Controller Signal Description Table 9. TWI Controller Signal Description Table 10. A/D Converter Signal Description serial I/O modes 1, 2 and 3. serial I/O modes 1, 2 and 3. When in master mode, MISO receives data from the slave peripheral. When in slave mode, MISO outputs data to the master controller. When in master mode, MOSI outputs data to the slave peripheral. When in slave mode, MOSI receives data from the master controller. in slave mode, SCK receives clock from the master controller. receives clock from the master controller.
Table 11. Keypad Interface Signal Description Table 12. External Access Signal Description Notes: 1. For ROM/Flash Dice product versions: pad EA must be connected to VCC.
- For ROMless Dice product versions: pad EA must be connected to VSS.
Table 13. System Signal Description Upper address lines for the external bus. Multiplexed higher address and data lines for the IDE interface. to demultiplex the address from address/data bus. falling reset to force execution of the internal bootloader. external program memory locations 0000h to FFFFh. reset by connecting a capacitor between this pin and V DD. returns the chip to normal operation.
Table 14. Power Signal Description
4.3 Internal Pin Structure
Table 15. Detailed Internal Pin Structure Section “DC Characteristics”, page 180.
- When the Two Wire controller is enabled, P 1, P 2, and P 3 transistors are disabled allowing
pseudo open-drain structure.
- In Port 2, P 1 transistor is continuously driven when outputting a high level bit address (A15:8).
4109JS–8051–10/06 AT8xC51SND1C 5. Application Information Figure 5-1. AT8xC51SND1C Typical Application with On-Board Atmel DataFlash and 2-wire LCD Ref. Battery DOUT DCLK DSEL SCLK P1.4 P1.5 AIN0 MCLK VSS AVSS VREFP VREFN VDD AVDD AIN1 MDAT MCMD MMC1 MMC2 Audio DAC RST LCD P1.7/SDA P1.6/SCLP1.1/KIN1 P0.0 P0.1 P1.2/KIN2 P1.3/KIN3 P0.2 P0.3 P1.0/KIN0 FILT PVSS DataFlash P4.2/SCK P4.0/SI P4.1/SO Memories P4n AT8xC51SND1C USB PORT UVDD UVSS
4109JS–8051–10/06 AT8xC51SND1C Figure 5-4. AT8xC51SND1C Typical Application with IDE CD-ROM Drive Ref. Battery IDE CD-ROM DOUT DCLK DSEL SCLK P3.4 P3.5 AIN0 MCLK VSS AVSS VREFP VREFN VDD AVDD AIN1 MDAT MCMD MMC1 MMC2 Audio DAC RST P4.2 P1.0/KIN0 P0.0 P0.1 P1.1/KIN1 P1.2/KIN2 P0.2 P0.3 P4.4 P4.5 P4.6 P4.7 LCD P1.7/SDA P1.6/SCL FILT PVSS AT8xC51SND1C P3.6/WR# P3.7/RD# P4.0 P4.1 USB PORT UVDD UVSS
4109JS–8051–10/06 1. Peripherals The AT8xC51SND1C peripherals are briefly described in the following sections. For fur- ther details on how to interface (hardware and software) to these peripherals, please refer to the AT8xC51SND1C design guide.
1.1 Clock Generator System
The AT8xC51SND1C internal clocks are extracted from an on-chip PLL fed by an on- chip oscillator. Four clocks are generated respectively for the C51 core, the MP3 decoder, the audio interface, and the other peripherals. The C51 and peripheral clocks are derived from the oscillator clock. T he MP3 decoder clock is generated by dividing the PLL output clock. The audio interface sample rates are also obtained by dividing the PLL output clock.
1.2 Ports
The AT8xC51SND1C implements five 8-bit ports (P0 to P4) and one 4-bit port (P5). In addition to performing general-purpose I/O, some ports are capable of external data memory operations; others allow for alternate functions. All I/O Ports are bidirectional. Each Port contains a latch, an output driver and an input buffer. Port 0 and Port 2 output drivers and input buffers facilitate external memory operations. Some Port 1, Port 3 and Port 4 pins serve for both general-purpose I/O and alternate functions.
1.3 Timers/Counters
The AT8xC51SND1C implements the two general-purpose, 16-bit Timers/Counters of a standard C51. They are identified as Timer 0, Timer 1, and can independently be config- ured each to operate in a variety of modes as a Timer or as an event Counter. When operating as a Timer, a Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, a Timer/Counter counts neg- ative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request.
1.4 Watchdog Timer
The AT8xC51SND1C implements a hardware Watchdog Timer that automatically resets the chip if it is allowed to time out. The WDT provides a means of recovering from rou- tines that do not complete successfully due to software or hardware malfunctions.
1.5 MP3 Decoder
The AT8xC51SND1C implements a MPEG I/II audio layer 3 decoder (known as MP3 decoder). In MPEG I (ISO 11172-3) three layers of compression have been standardized support- ing three sampling frequencies: 48, 44.1, and 32 KHz. Among these layers, layer 3 allows highest compression rate of about 12:1 while still maintaining CD audio quality. For example, 3 minutes of CD audio (16-bit PCM, 44.1 KHz) data, which needs about 32 MBytes of storage, can be encoded into only 2.7 MBytes of MPEG I audio layer 3 data. In MPEG II (ISO 13818-3), three additional sampling frequencies: 24, 22.05, and 16 KHz are supported for low bit rates applications. The AT8xC51SND1C can decode in real-time the MPEG I audio layer 3 encoded data into a PCM audio data, and also supports MPEG II audio layer 3 additional frequencies.
16 AT8xC51SND1C
4109JS–8051–10/06 Additional features are supported by the AT8xC51SND1C MP3 decoder such as vol- ume, bass, medium, and treble controls, bass boost effect and ancillary data extraction.
1.6 Audio Output Interface
The AT8xC51SND1C implements an audio output interface allowing the decoded audio bitstream to be output in various formats. It is compatible with right and left justification PCM and I 2S formats and thanks to the on-chip PLL (see Section 1.1) allows connection of almost all of the commercial audio DAC families available on the market.
1.7 Universal Serial Bus Interface
The AT8xC51SND1C implements a full speed Universal Serial Bus Interface. It can be used for the following purposes: Download of MP3 encoded audio files by supporting the USB mass storage class. In System Programming by supporting the USB firmware upgrade class.
1.8 MultiMediaCard Interface
The AT8xC51SND1C implements a MultiMediaCard (MMC) interface compliant to the V2.2 specification in MultiMediaCard Mode. The MMC allows storage of MP3 encoded audio files in removable flash memory cards that can be easily plugged or removed from the application. It can also be used for In System Programming.
1.9 IDE/ATAPI interface
The AT8xC51SND1C provides an IDE/ATAPI interface allowing connexion of devices such as CD-ROM reader, CompactFlash cards, Hard Disk Drive… It consists in a 16-bit bidirectional bus part of the low-level ANSI ATA/ATAPI specification. It is provided for mass storage interface but could be used for In System Programming using CD-ROM.
1.10 Serial I/O Interface
The AT8xC51SND1C implements a serial port with its own baud rate generator provid- ing one single synchronous communication mode and three full-duplex Universal Asynchronous Receiver Transmitter (UART) communication modes. It is provided for the following purposes: In System Programming. Remote control of the AT8xC51SND1C by a host.
1.11 Serial Peripheral Interface
The AT8xC51SND1C implements a Serial Peripheral Interface (SPI) supporting master and slave modes. It is provided for the following purposes: Interfacing DataFlash memory for MP3 encoded audio files storage. Remote control of the AT8xC51SND1C by a host. In System Programming.
4109JS–8051–10/06 1.12 2-wire Controller The AT8xC51SND1C implements a 2-wire controller supporting the four standard mas- ter and slave modes with multimaster capability. It is provided for the following purposes: Connection of slave devices like LCD controller, audio DAC… Remote control of the AT8xC51SND1C by a host. In System Programming.
1.13 A/D Controller
The AT8xC51SND1C implements a 2-channel 10-bit (8 true bits) analog to digital con- verter (ADC). It is provided for the following purposes: Battery monitoring. Voice recording. Corded remote control.
1.14 Keyboard Interface
The AT8xC51SND1C implements a keyboard interface allowing connection of 4 x n matrix keyboard. It is based on 4 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1.3:0 and allow exit from idle and power down modes.
- Electrical Characteristics
22.1 Absolute Maximum Rating
22.2 DC Characteristics
22.2.1 Digital Logic
mum Ratings” may cause permanent damage. Conditions” may affect device reliability. Table 143. Digital DC Characteristics
0.45 V I
- Flash retention is guaranteed with the same formula for V DD min down to 0V.
- See Table 144 for typical consumption in player mode.
Table 144. Typical Reference Design AT89C51SND1C Power Consumption
12 MHz
16 MHz
20 MHz
4109JS–8051–10/06 AT8xC51SND1C
22.2.1.1 I DD, IDL and IPD Test Conditions
Figure 22-1. IDD Test Condition, Active Mode Figure 22-2. IDL Test Condition, Idle Mode Figure 22-3. IPD Test Condition, Power-Down Mode RST TST All other pins are unconnected VDD VDD VDD IDD VDD PVDD UVDD AVDD Clock Signal VSS (NC) VSS PVSS UVSS AVSS VDD Clock Signal RST VSS TST (NC) IDL All other pins are unconnected VSS VDD VSS VDD PVDD UVDD AVDD PVSS UVSS AVSS RST MCMD All other pins are unconnected VSS VDD TST MDAT VDD IPD VDD PVDD UVDD AVDD VSS (NC) VSS PVSS UVSS AVSS
22.2.2 A to D Converter
Table 145. A to D Converter DC Characteristics
22.2.3 Oscillator & Crystal
22.2.3.1 Schematic
pF). X1 and X2 may not be used to drive other circuits.
22.2.3.2 Parameters
Table 146. Oscillator & Crystal Characteristics
2.4 AV DD
22.2.4 Phase Lock Loop
22.2.4.1 Schematic
22.2.4.2 Parameters
Table 147. PLL Filter Characteristics
22.2.5 USB Connection
22.2.5.1 Schematic
22.2.5.2 Parameters
Table 148. USB Characteristics
22.2.6 In System Programming
22.2.6.1 Schematic
22.2.6.2 Parameters
Table 149. ISP Pull-Down Characteristics
22.3 AC Characteristics
22.3.1 External Program Bus Cycles
22.3.1.1 Definition of Symbols
Table 150. External Program Bus Cycles Timing Symbol Definitions
22.3.1.2 Timings
Test conditions: capacitive load on all pins= 50 pF. Table 151. External Program Bus Cycle - Read AC Timings
22.3.1.3 Waveforms
22.3.2 External Data 8-bit Bus Cycles
22.3.2.1 Definition of Symbols
Table 152. External Data 8-bit Bus Cycles Timing Symbol Definitions
22.3.2.2 Timings
Test conditions: capacitive load on all pins= 50 pF. Table 153. External Data 8-bit Bus Cycle - Read AC Timings
Table 154. External Data 8-bit Bus Cycle - Write AC Timings
22.3.2.3 Waveforms
22.3.3 External IDE 16-bit Bus Cycles
22.3.3.1 Definition of Symbols
Table 155. External IDE 16-bit Bus Cycles Timing Symbol Definitions
22.3.3.2 Timings
Test conditions: capacitive load on all pins= 50 pF. Table 156. External IDE 16-bit Bus Cycle - Data Read AC Timings Table 157. External IDE 16-bit Bus Cycle - Data Write AC Timings
22.3.3.3 Waveforms
Note: 1. D15:8 is written in DAT16H SFR. Note: 1. D15:8 is the content of DAT16H SFR.
22.4 SPI Interface
22.4.0.4 Definition of Symbols
Table 158. SPI Interface Timing Symbol Definitions
22.4.0.5 Timings
Test conditions: capacitive load on all pins= 50 pF. Table 159. SPI Interface Master AC Timing Note: 1. Value of this parameter depends on software.
4109JS–8051–10/06 AT8xC51SND1C
22.4.0.6 Waveforms
Figure 22-13. SPI Slave Waveforms (SSCPHA= 0) Note: 1. Not Defined but generally the MSB of the character which has just been received. Figure 22-14. SPI Slave Waveforms (SSCPHA= 1) Note: 1. Not Defined but generally the LSB of the character which has just been received. TSLCL TSLCH TCHCL TCLCH MOSI (input) SCK (SSCPOL= 0) (input) SS (input) SCK (SSCPOL= 1) (input) MISO (output) TCHCH TCLCXTCHCX TIVCL TCLIX TCHIXTIVCH TCHOV TCLOV TCHOX TCLOX MSB IN BIT 6 LSB IN SLAVE MSB OUT SLAVE LSB OUTBIT 6 TSLOV (1) TSHOX TSHSLTCHSH TCLSH TCHCL TCLCH MOSI (input) SCK (SSCPOL= 0) (input) SS (input) SCK (SSCPOL= 1) (input) MISO (output) TCHCH TCLCXTCHCX TIVCL TCLIX TCHIXTIVCH TCLOV TCHOV TCLOX TCHOX MSB IN BIT 6 LSB IN SLAVE MSB OUT SLAVE LSB OUTBIT 6 TSLOV (1) TSHOX TSHSLTCHSH TCLSH TSLCL TSLCH
Note: 1. SS handled by software using general purpose port pin. Note: 1. SS handled by software using general purpose port pin.
22.4.1 Two-wire Interface
22.4.1.1 Timings
Table 160. TWI Interface AC Timing
4109JS–8051–10/06 AT8xC51SND1C VDD = 2.7 to 3.3 V, TA = -40 to +85°C Notes: 1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. Determined by the external bus-line capacitance and the external bus-line pull-up resistor, this must be < 1 μs. 3. Spikes on the SDA and SCL lines with a duration of less than 3·T CLCL will be filtered out. Maxi- mum capacitance on bus-lines SDA and SCL= 400 pF. 4. TCLCL= TOSC= one oscillator clock period.
22.4.1.2 Waveforms
Figure 22-17. Two Wire Waveforms Symbol Parameter INPUT Mi n Max OUTPUT Mi n Max THD; STA Start condition hold time 14·T CLCL(4) 4.0 μs(1) TLOW SCL low time 16·T CLCL(4) 4.7 μs(1) THIGH SCL high time 14·T CLCL(4) 4.0 μs(1) TRC SCL rise time 1 μs- (2) TFC SCL fall time 0.3 μs0 . 3 μs(3) TSU; DAT1 Data set-up time 250 ns 20·T CLCL(4)- TRD TSU; DAT2 SDA set-up time (before repeated START condition) 250 ns 1 μs(1) TSU; DAT3 SDA set-up time (before STOP condition) 250 ns 8·T CLCL(4) THD; DAT Data hold time 0 ns 8·T CLCL(4) - TFC TSU; STA Repeated START set-up time 14·T CLCL(4) 4.7 μs(1) TSU; STO STOP condition set-up time 14·T CLCL(4) 4.0 μs(1) TBUF Bus free time 14·T CLCL(4) 4.7 μs(1) TRD SDA rise time 1 μs - (2) TFD SDA fall time 0.3 μs0 . 3 μs(3) Tsu;DAT1 Tsu;STA Tsu;DAT2Thd;STA ThighTlow SDA (INPUT/OUTPUT) 0.3 VDD
0.7 VDD
TbufTsu;STO
0.3 VDD
(INPUT/OUTPUT) Thd;DAT Tsu;DAT3 START or Repeated START condition START condition STOP condition Repeated START condition
22.4.2 MMC Interface
22.4.2.1 Definition of symbols
Table 161. MMC Interface Timing Symbol Definitions
22.4.2.2 Timings
Table 162. MMC Interface AC timings
22.4.2.3 Waveforms
22.4.3 Audio Interface
22.4.3.1 Definition of symbols
Table 163. Audio Interface Timing Symbol Definitions
22.4.3.2 Timings
Table 164. Audio Interface AC timings Note: 1. 32-bit format with Fs= 48 KHz.
22.4.3.3 Waveforms
22.4.4 Analog to Digital Converter
22.4.4.1 Definition of symbols
Table 165. Analog to Digital Converter Timing Symbol Definitions
22.4.4.2 Characteristics
Table 166. Analog to Digital Converter AC Characteristics Notes: 1. AV DD= AVREFP= 3.0 V, AVSS= AVREFN= 0 V. ADC is monotonic with no missing code.
- The differential non-linearity is the difference between the actual step width and the ideal step
- The integral non-linearity is the peak difference between the center of the actual step and the
ideal transfer curve after appropriate adjustment of gain and offset errors (see Figure 22-21).
- The offset error is the absolute difference between the straight line which fits the actual trans -
- The gain error is the relative difference in percent between the straight line which fits the actual
4109JS–8051–10/06 AT8xC51SND1C
22.4.4.3 Waveforms
Figure 22-20. Analog to Digital Converter Internal Waveforms Figure 22-21. Analog to Digital Converter Characteristics ADEN Bit ADSST Bit TEHSH TSHSL CLK TCLCL 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 1018 1019 1020 1021 1022 1023 Offset Error OSe Code Out AVIN Offset Error OSe Gain Error Ge Ideal Transfer curve
1 LSB
(ideal) Integral non-linearity (ILe) Differential non-linearity (DLe) Center of a step Example of an actual transfer curve 0 (LSB ideal)
22.4.5 Flash Memory
22.4.5.1 Definition of symbols
Table 167. Flash Memory Timing Symbol Definitions
22.4.5.2 Timings
Table 168. Flash Memory AC Timing
22.4.5.3 Waveforms
22.4.6 External Clock Drive and Logic Level References
22.4.6.1 Definition of symbols
Table 169. External Clock Timing Symbol Definitions
22.4.6.2 Timings
22.4.6.3 Waveforms
Note: 1. During AC testing, all inputs are driven at V DD -0.5 V for a logic 1 and 0.45 V for a logic 0.
- Timing measurements are made on all outputs at V IH min for a logic 1 and VIL max for a logic 0.
4109JS–8051–10/06 AT8xC51SND1C Note: For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loading V OH/VOL level occurs with IOL/IOH= ±20 mA.
4109JS–8051–10/06 AT8xC51SND1C 24. Ordering Information Notes: 1. Refers to ROM code. 2. PLCC84 package only available for development board. Part Number Memory Size Supply Voltage Temperature Range Max Frequency Package (2) Packing Product Marking AT89C51SND1C-ROTIL 64K Flash 3V Industrial 40 MHz TQFP80 Tray 89C51SND1C-IL AT89C51SND1C-7HTIL 64K Flash 3V Industrial 40 MHz BGA81 Tray 89C51SND1C-IL AT89C51SND1C-DDV 64K Flash 3V Industrial 40 MHz Dice Tray - AT83SND1Cxxx(1)-ROTIL 64K ROM 3V Industrial 40 MHz TQFP80 Tray 89C51SND1C-IL AT83SND1Cxxx(1)-7HTIL 64K ROM 3V Industrial 40 MHz BGA81 Tray 89C51SND1C-IL AT83SND1Cxxx-DDV 64K ROM 3V Industrial 40 MHz Dice Tray - AT80C51SND1C-ROTIL ROMless 3V Industrial 40 MHz TQFP80 Tray 89C51SND1C-IL AT80C51SND1C-7HTIL ROMless 3V Industrial 40 MHz BGA81 Tray 89C51SND1C-IL AT80C51SND1C-DDV ROMless 3V Industrial 40 MHz Dice Tray - AT89C51SND1C-ROTUL 64K Flash 3V Industrial & Green 40 MHz TQFP80 Tray 89C51SND1C-IL AT89C51SND1C-7HTJL 64K Flash 3V Industrial 40 MHz BGA81 Tray 89C51SND1C-IL AT83SND1Cxxx(1)-ROTUL 64K ROM 3V Industrial & Green 40 MHz TQFP80 Tray 89C51SND1C-IL AT83SND1Cxxx(1)-7HTJL 64K ROM 3V Industrial & Green 40 MHz BGA81 Tray 89C51SND1C-IL AT80C51SND1C-ROTUL ROMless 3V Industrial & Green 40 MHz TQFP80 Tray 89C51SND1C-IL AT80C51SND1C-7HTJL ROMless 3V Industrial & Green 40 MHz BGA81 Tray 89C51SND1C-IL
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