Microcontroller

89C51RB2-CM

ATMEL Corporation

Microcontroller with 16K/32K Bytes Flash

Manufacturer: ATMEL Corporation

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AT89C51RC2_0312 ATMEL | Alldatasheet

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Features

80C52 Compatible – 8051 Pin and Instruction Compatible – Four 8-bit I/O Ports – Three 16-bit Timer/Counters – 256 Bytes Scratch Pad RAM – 9 Interrupt Sources with 4 Priority Levels – Dual Data Pointer Variable Length MOVX for Slow RAM/Peripherals ISP (In-system Programming) Using Standard VCC Power Supply Boot ROM Contains Low Level Flash Programming Routines and a Default Serial Loader High-speed Architecture – In Standard Mode: 40 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution) 60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only) – In X2 mode (6 Clocks/machine cycle) 20 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution) 30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only) – 16K/32K Bytes On-chip Flash Program/Data Memory – Byte and Page (128 Bytes) Erase and Write – 100K Write Cycles On-chip 1024 Bytes Expanded RAM (XRAM) – Software Selectable Size (0, 256, 512, 768, 1024 Bytes) – 256 Bytes Selected at Reset for TS87C51RB2/RC2 Compatibility Keyboard Interrupt Interface on Port P1 SPI Interface (Master/Slave Mode) 8-bit Clock Prescaler Improved X2 Mode with Independent Selection for CPU and Each Peripheral Programmable Counter Array 5 Channels – High-speed Output – Compare/Capture – Pulse Width Modulator – Watchdog Timer Capabilities Asynchronous Port Reset Full Duplex Enhanced UART Dedicated Baud Rate Generator for UART Low EMI (Inhibit ALE) Hardware Watchdog Timer (One-time Enabled with Reset-out) Power Control Modes – Idle Mode – Power-down Mode – Power-off Flag Power Supply: – 2.7 to 3.6 (3V Version) – 2.7 to 5.5V (5V Version) Temperature Ranges: Commercial (0 to +70°C) and Industrial (-40°C to +85°C) Packages: PDIL40, PLCC44, VQFP44

Description

The AT89C51RB2/RC2 is a high-performance Flash version of the 80C51 8-bit micro- controllers. It contains a 16K or 32K Bytes Flash memory block for program and data. The Flash memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard VCC pin. 8-bit Microcontroller with 16K/ 32K Bytes Flash AT89C51RB2 AT89C51RC2

2 AT89C51RB2/RC2

RAM, a 9-source 4-level interrupt controller and three timer/counters.

1024 Bytes, a Hardware Watchdog Timer, a Keyboard Interface, an SPI Interface, a

and a speed improvement mechanism (X2 mode). The Pinout is the standard 40/44 pins of the C52. allowing it to bring the clock frequency down to any value, even DC, without loss of data. mode, the RAM is saved and all other functions are inoperative. alarms, motor control, corded phones, and smart card readers. Table 1. Memory Size

Figure 1. Block Diagram Notes: 1. Alternate function of Port 1.

Alternate function of Port 3.

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4180C–8051–12/03 SFR Mapping The Special Function Registers (SFRs) of the AT89C51RB2/RC2 fall into the following categories: C51 core registers: ACC, B, DPH, DPL, PSW, SP I/O port registers: P0, P1, P2, P3 Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H Serial I/O port registers: SADDR, SADEN, SBUF, SCON PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH, CCAPxH, CCAPxL (x: 0 to 4) Power and clock control registers: PCON Hardware Watchdog Timer registers: WDTRST, WDTPRG Interrupt system registers: IEN0, IPL0, IPH0, IEN1, IPL1, IPH1 Keyboard Interface registers: KBE, KBF, KBLS SPI registers: SPCON, SPSTR, SPDAT BRG (Baud Rate Generator) registers: BRL, BDRCON Flash register: FCON Clock Prescaler register: CKRL Others: AUXR, AUXR1, CKCON0, CKCON1

Table 2. C51 Core SFRs Table 3. System Management SFRs Table 4. Interrupt SFRs Table 5. Port SFRs

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Table 6. Timer SFRs Table 7. PCA SFRs

Table 8. Serial I/O Port SFRs Table 9. SPI Controller SFRs Table 10. Keyboard Interface SFRs

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Table 11 shows all SFRs with their address and their reset value. Table 11. SFR Mapping

FCON access is reserved for the Flash API and ISP software.

Figure 2. Pin Configurations

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Table 12. Pin Description for 40 - 44 Pin Packages during memory programming and verification. SPI is in slave mode, MISO outputs data to the master controller.

is in slave mode, MOSI receives data from the master controller. 80C51 family, as listed below. watchdog forces a system reset. bit. With this bit set, ALE will be inactive during internal fetches. Table 12. Pin Description for 40 - 44 Pin Packages (Continued)

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security level 1 is programmed, EA will be internally latched on Reset.

CPU clocks, in order to pull the port pin high quickly. Then it turns off again. ports when latch data is logical 0. The quasi-bidirectional port configuration is shown in Figure 3. Figure 3. Quasi-Bidirectional Output

2 CPU

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Table 14. PCON Register Set to select double baud rate in mode 1, 2 or 3. Cleared to select SM0 bit in SCON register. Set to select FE bit in SCON register. The value read from this bit is indeterminate. Do not set this bit. Cleared to recognize next reset type. Cleared by software for general-purpose usage. Set by software for general-purpose usage. Cleared by software for general-purpose usage. Set by software for general-purpose usage. Cleared by hardware when reset occurs. Set to enter power-down mode. Cleared by hardware when interrupt or reset occurs.

Figure 4. Functional Oscillator Block Diagram

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Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. Save power consumption while keeping same CPU power (oscillator power saving). Increase CPU power by 2 while keeping same crystal frequency. the CPU core and the peripherals. bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. the switching mode waveforms. Figure 5. Clock Generation Diagram

Figure 6. Mode Switching Waveforms X2 bit activates the X2 feature (X2 mode).

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Table 15. CKCON0 Register

7 Reserved

Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. periods per peripheral clock cycle. periods per peripheral clock cycle. Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. periods per peripheral clock cycle. periods per peripheral clock cycle.

Table 16. CKCON1 Register Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

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code to switch between them (see Figure 7). Figure 7. Use of Dual Pointer

Table 17. AUXR1 register Note: 1. Bit 2 stuck at 0; this allows using INC AUXR1 to toggle DPS without changing GF3.

0008 LOOP:

The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.

5 ENBOOT

Cleared to disable boot ROM. Set to map the boot ROM between F800h - 0FFFFh. The value read from this bit is indeterminate. Do not set this bit. 3G F 3 This bit is a general-purpose user flag.

20 Always Cleared

The value read from this bit is indeterminate. Do not set this bit.

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4180C–8051–12/03 INC is a short (2 Bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.

space for increased data parameter handling and high-level language usage. and location are described in Table 18. Table 18. Expanded RAM

The Lower 128 Bytes of RAM (addresses 00h to 7Fh) are directly and indirectly
The Upper 128 Bytes of RAM (addresses 80h to FFh) are indirectly addressable
The Special Function Registers, SFRs, (addresses 80h to FFh) are directly
The expanded RAM Bytes are indirectly accessed by MOVX instructions, and

with the EXTRAM bit cleared in the AUXR register (see Table 18). physically separate from SFR space. Figure 8. Internal and External Data Memory Address addressing mode used in the instruction. MOV 0A0H, # data, accesses the SFR at location 0A0h (which is P2).

128 Bytes

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4180C–8051–12/03 Instructions that use indirect addressing access the Upper 128 Bytes of data RAM. For example: MOV @R0, # data where R0 contains 0A0h, accesses the data Byte at address 0A0h, rather than P2 (whose address is 0A0h). The XRAM Bytes can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions. This part of memory that is physically located on-chip, logically occupies the first Bytes of external data memory. The bits XRS0 and XRS1 are used to hide a part of the available XRAM as explained in Table 18. This can be useful if external peripherals are mapped at addresses already used by the internal XRAM. With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. An access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H rather than external memory. An access to external data memory locations higher than the accessible size of the XRAM will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and read timing signals. Accesses to XRAM above 0FFH can only be done by the use of DPTR. With EXTRAM = 1 , MOVX @RI and MOVX @DPTR will be similar to the standard 80C51. MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0 and any output port pins can be used to output higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs the high-order eight address bits (the contents of DPH) while Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX @ RI and MOVX @DPTR will generate either read or write signals on P3.6 (WR ) and P3.7 (RD). The stack pointer (SP) may be located anywhere in the 256 Bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the XRAM. The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses are extended from 6 to 30 clock periods. This is useful to access external slow peripherals.

4180C–8051–12/03 Registers Table 19. AUXR Register AUXR - Auxiliary Register (8Eh) Reset Value = XX0X 00’HSB. XRAM’0b (see Table 65) Not bit addressable 76543210 DPU - M0 - XRS1 XRS0 EXTRAM AO Bit Number Bit Mnemonic Description 7D P U Disable Weak Pull-up Cleared to activate the permanent weak pull up when latch data is logical 1 Set to disactive the weak pull-up (reduce power consumption) 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5M 0 Pulse Length Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock periods (default). Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3X R S 1 XRAM Size XRS1 XRS0 XRAM size 0 0 256 Bytes (default) 0 1 512 Bytes 1 0 768 Bytes 1 1 1024 Bytes 2X R S 0

1 EXTRAM

Cleared to access internal XRAM using movx @ Ri/ @ DPTR. Set to access external memory. Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), default setting, XRAM selected. 0A O ALE Output Bit Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC instruction is used.

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4180C–8051–12/03 Timer 2 The Timer 2 in the AT89C51RB2/RC2 is the standard C52 Timer 2. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 are cascaded. It is controlled by T2CON (Table 20) and T2MOD (Table 21) registers. Timer 2 operation is similar to Timer 0 and Timer 1C/T2 selects FOSC /12 (timer operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to increment by the selected input. Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON). see the Atmel 8-bit Microcontroller Hardware description for the description of Capture and Baud Rate Generator Modes. Timer 2 includes the following enhancements: Auto-reload mode with up or down counter Programmable clock-output Auto-reload Mode The auto-reload mode configures Timer 2 as a 16-bit timer or event counter with auto- matic reload. If DCEN bit in T2MOD is cleared, Timer 2 behaves as in 80C52 (see the Atmel C51 Microcontroller Hardware description). If DCEN bit is set, Timer 2 acts as an Up/down timer/counter as shown in Figure 9. In this mode the T2EX pin controls the direction of count. When T2EX is high, Timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2. When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers. The EXF2 bit toggles when Timer 2 overflows or underflows according to the direction of the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution.

Figure 9. Auto-Reload Mode Up/Down Counter (DCEN = 1) Set T2OE bit in T2MOD register. Clear C/T2 bit in T2CON register. reload value or a different one depending on the application. To start the timer, set TR2 run control bit in T2CON register. independent since both functions use the values in the RCAP2H and RCAP2L registers.

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Figure 10. Clock-Out Mode C/T2 = 0

4180C–8051–12/03 Registers Table 20. T2CON Register T2CON – Timer 2 Control Register (C8h) Reset Value = 0000 0000b Bit addressable 76543210 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Bit Number Bit Mnemonic Description

7 TF2

Must be cleared by software. Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0. 6E X F 2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2 = 1. When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2 interrupt is enabled. Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1).

5 RCLK

Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3. 4T C L K Transmit Clock Bit Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.

3 EXEN2

Timer 2 External Enable Bit Cleared to ignore events on T2EX pin for Timer 2 operation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if Timer 2 is not used to clock the serial port. 2T R 2 Timer 2 Run Control Bit Cleared to turn off Timer 2. Set to turn on Timer 2. 1C / T 2 # Timer/Counter 2 Select Bit Cleared for timer operation (input from internal clock system: F CLK PERIPH ). Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode. 0C P / R L 2 # Timer 2 Capture/Reload Bit If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to auto-reload on Timer 2 overflow. Cleared to auto-reload on Timer 2 overflows or negative transitions on T2EX pin if EXEN2 = 1. Set to capture on negative transitions on T2EX pin if EXEN2 = 1.

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Table 21. T2MOD Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. Cleared to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output.

0 DCEN

Cleared to disable Timer 2 as up/down counter. Set to enable Timer 2 as up/down counter.

4180C–8051–12/03 Programmable Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture Modules. Its clock input can be programmed to count any one of the following signals: Peripheral clock frequency (F CLK PERIPH ) ÷ 6 Peripheral clock frequency (FCLK PERIPH ) ÷ 2 Timer 0 overflow External input on ECI (P1.2) Each compare/capture Modules can be programmed in any one of the following modes: Rising and/or falling edge capture Software timer High-speed output Pulse width modulator Module 4 can also be programmed as a watchdog timer (see Section "PCA Watchdog Timer", page 42). When the compare/capture Modules are programmed in the capture mode, software timer, or high speed output mode, an interrupt can be generated when the Module exe- cutes its function. All five Modules plus the PCA timer overflow share one interrupt vector. The PCA timer/counter and compare/capture modules share Port 1 for external I/O. These pins are listed below. If one or several bits in the port are not used for the PCA, they can still be used for standard I/O. The PCA timer is a common time base for all five Modules (see Figure 11). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD register (Table 22) and can be programmed to run at: 1/6 the peripheral clock frequency (FCLK PERIPH ) 1/2 the peripheral clock frequency (FCLK PERIPH ) The Timer 0 overflow The input on the ECI pin (P1.2) PCA Component External I/O Pin 16-bit Counter P1.2/ECI 16-bit Module 0 P1.3/CEX0 16-bit Module 1 P1.4/CEX1 16-bit Module 2 P1.5/CEX2 16-bit Module 3 P1.6/CEX3

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Figure 11. PCA Timer/Counter

4180C–8051–12/03 Registers Table 22. CMOD Register CMOD – PCA Counter Mode Register (D9h) Reset Value = 00XX X000b Not bit addressable The CMOD register includes three additional bits associated with the PCA. The CIDL bit which allows the PCA to stop during idle mode. The WDTE bit which enables or disables the watchdog function on Module 4. The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows. The CCON register contains the run control bit for the PCA and the flags for the PCA timer (CF) and each Module (see Table 23). Bit CR (CCON. 6) must be set by software to run the PCA. The PCA is shut off by clearing this bit. Bit CF: The CF bit (CCON. 7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by software. Bits 0 through 4 are the flags for the Modules (bit 0 for Module 0, bit 1 for Module 1, etc. ) and are set by hardware when either a match or a capture occurs. These flags also can only be cleared by software. 76543210 CIDL WDTE - - - CPS1 CPS0 ECF Bit Number Bit Mnemonic Description 7C I D L Counter Idle Control Cleared to program the PCA Counter to continue functioning during idle Mode. Set to program PCA to be gated off during idle. 6W D T E Watchdog Timer Enable Cleared to disable Watchdog Timer function on PCA Module 4. Set to enable Watchdog Timer function on PCA Module 4. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit.

2 CPS1 PCA Count Pulse Select

0 0 Internal clock F CLK PERIPH /6 0 1 Internal clock F LK PERIPH /2 1 0 Timer 0 Overflow 1 1 External clock at ECI/P1.2 pin (max rate = fCLK PERIPH/ 4)

1 CPS0

PCA Enable Counter Overflow Interrupt Cleared to disable CF bit in CCON to inhibit an interrupt. Set to enable CF bit in CCON to generate an interrupt.

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Table 23. CCON Register The watchdog timer function is implemented in Module 4 (see Figure 14). The PCA interrupt system is shown in Figure 12. Must be cleared by software to turn the PCA counter off. Set by software to turn the PCA counter on. The value read from this bit is indeterminate. Do not set this bit.