89C51CC02CA-UM

T89C51CC02_08 ATMEL | Alldatasheet

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 80C51 Core Architecture  256 Bytes of On-chip RAM  256 Bytes of On-chip XRAM  16K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C – Erase/Write Cycle: 100K  Boot Code Section with Independent Lock Bits  2K Bytes of On-chip Flash for Bootloader  In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability  2K Bytes of On-chip EEPROM – Erase/Write Cycle: 100K  14-sources 4-level Interrupts  Three 16-bit Timers/Counters  Full Duplex UART Compatible 80C51  Maximum Crystal Frequency 40 MHz. In X2 Mode, 20 MHz (CPU Core, 40 MHz)  Three or Four Ports: 16 or 20 Digital I/O Lines  Two-channel 16-bit PCA – PWM (8-bit) – High-speed Output – Timer and Edge Capture  Double Data Pointer  21-bit Watchdog Timer (7 Programmable bits)  A 10-bit Resolution Analog-to-Digital Converter (ADC) with 8 Multiplexed Inputs  Full CAN Controller – Fully Compliant with CAN rev.# 2.0A and 2.0B – Optimized Structure for Communication Management (Via SFR) – 4 Independent Message Objects -Each Message Object Programmable on Transmission or Reception -Individual Tag and Mask Filters up to 29-bit Identifier/Channel -8-byte Cyclic Data Register (FIFO)/Message Object -16-bit Status and Control Register/Message Object -16-bit Time-Stamping Register/Message Object -CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message Object -Access to Message Object Control and Data Registers Via SFR -Programmable Reception Buffer Length up to 4 Message Objects -Priority Management of Reception of Hits on Several Message Objects Simultaneously (Basic CAN Feature) -Priority Management for Transmission -Message Object Overrun Interrupt – Supports -Time Triggered Communication -Autobaud and Listening Mode -Programmable Automatic Reply Mode  1-Mbit/s Maximum Transfer Rate at 8 MHz(1) Crystal Frequency In X2 Mode  Readable Error Counters  Programmable Link to On-chip Timer for Time Stamping and Network Synchronization  Independent Baud Rate Prescaler  Data, Remote, Error and Overload Frame Handling  Power-saving Modes –I d l e M o d e – Power-down Mode  Power Supply: 3 Volts to 5.5 Volts  Temperature Range: Industrial (-40° to +85°C)  Packages: SOIC28, SOIC24, PLCC28, VQFP32 Note: 1. At BRP = 1 sampling point will be fixed. Enhanced 8-bit Microcontroller with CAN Controller and Flash T89C51CC02 AT89C51CC02

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4126L–CAN–01/08 Description Part of the CANaryTM family of 8-bit microcontrollers dedicated to CAN network applica- tions, the T89C51CC02 is a low-pin count 8-bit Flash microcontroller. In X2 Mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time. Besides the full CAN controller T89C51CC02 provides 16K Bytes of Flash memory including In-System Programming (ISP), 2K Bytes Boot Flash Memory, 2K Bytes EEPROM and 512 Bytes RAM. Special attention is payed to the reduction of the electro-magnetic emission of T89C51CC02. Block Diagram Note: 1. 8 analog Inputs/8 Digital I/O. 2. 2-bit I/O Port. Timer 0 INT RAM 256x8 RxD TxD XTAL2 XTAL1 UART CPU Timer 1 INT1 CtrlINT0 C51 CORE P2(2) Port 1 Port 2 Port 3 Parallel I/O PortsP1(1) XRAM 256 x 8 IB-bus PCA RESET Watch Dog PCA ECI Vss Vcc Timer 2 T2EX Port 4 P4(2) 10-bit ADC Flash 16K x Boot loader 2K x 8 EE PROM 2K x 8 CAN CONTROLLER TxDC RxDC VAVCC VAREF VAGND

4126L–CAN–01/08 Pin Configurations P3.4/T0 P3.3/INT1 P4.1/RxDC P3.7 P3.2/INT0 P1.5/AN5 P1.7/AN7 P1.6/AN6 P2.0 VAREF VAVCC VAGND P1.0/AN0/T2 P1.1/AN1/T2EX P1.2/AN2/ECI P1.3/AN3/CEX0 P1.4/AN4/CEX1 RESET VCC VSS P4.0/TxDC P2.1 P3.6 P3.5/T1 P3.1/TxD 13 P3.0/RxD 14

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15 XTAL2

P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2 P3.7 P4.0/TxDC P4.1/RxDC P2.1 P3.6 P2.0 P1.4/AN4/CEX1 P1.5/AN5 P1.6/AN6 P1.7/AN7 P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 VAVCC PLCC-28 P3.1/TxD P3.0/RxD P4.1/RxDC P3.4/T0 XTAL2 P1.5/AN5 P1.7/AN7 P1.6/AN6 RESET VAREF VAVCC VAGND P1.0/AN0/T2 P1.1/AN1/T2EX P1.2/AN2/ECI P1.3/AN3/CEX0 P1.4/AN4/CEX1 VSS XTAL1 VCC P4.0/TxDC P3.5/T1 P3.3/INT1 P3.2/INT0 SO24

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4126L–CAN–01/08 P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2 P3.7 P4.0/TxDC P4.1/RxDC P2.1 P3.6 P2.0 P1.4/AN4/CEX1 P1.5/AN5 P1.6/AN6 P1.7/AN7 P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 VAVCC QFP-32 NC NC NC NC 2425

4126L–CAN–01/08 Pin Description Pin Name Type Description VSS GND Circuit ground VCC Supply Voltage VAREF Reference Voltage for ADC (input) VAVCC Supply Voltage for ADC VAGND Reference Ground for ADC (internaly connected with the VSS) P1.0:7 I/O Port 1: Is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins can be used for digital input/output or as analog inputs for the Analog Digital Converter (ADC). Port 1 pins that have 1’s written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 1 pins that are being pulled low externally will be the source of current (I IL, See section ’Electrical Characteristic’) because of the internal pull-ups. Port 1 pins are assigned to be used as analog inputs via the ADCCF register (in this case the internal pull-ups are disconnected). As a secondary digital function, port 1 contains the Timer 2 external trigger and clock input; the PCA external clock input and the PCA module I/O. P1.0/AN0/T2 Analog input channel 0, External clock input for Timer/counter2. P1.1/AN1/T2EX Analog input channel 1, Trigger input for Timer/counter2. P1.2/AN2/ECI Analog input channel 2, PCA external clock input. P1.3/AN3/CEX0 Analog input channel 3, PCA module 0 Entry of input/PWM output. P1.4/AN4/CEX1 Analog input channel 4, PCA module 1 Entry of input/PWM output. P1.5/AN5 Analog input channel 5, P1.6/AN6 Analog input channel 6, P1.7/AN7 Analog input channel 7, It can drive CMOS inputs without external pull-ups. P2.0:1 I/O Port 2: Is an 2-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1’s written to them are pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 2 pins that are being pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-ups. In the T89C51CC02 Port 2 can sink or source 5mA. It can drive CMOS inputs without external pull-ups.

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4126L–CAN–01/08 P3.0:7 I/O Port 3: Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 3 pins that are being pulled low externally will be a source of current (IIL, See section ’Electrical Characteristic’) because of the internal pull-ups. The output latch corresponding to a secondary function must be programmed to one for that function to operate (except for TxD and WR). The secondary functions are assigned to the pins of port 3 as follows: P3.0/RxD: Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface P3.1/TxD: Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface P3.2/INT0 : External interrupt 0 input/timer 0 gate control input P3.3/INT1: External interrupt 1 input/timer 1 gate control input P3.4/T0: Timer 0 counter input P3.5/T1: Timer 1 counter input P3.6: Regular I/O port pin P3.7: Regular I/O port pin P4.0:1 I/O Port 4: Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s written to them are pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 4 pins that are being pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-up transistor. The output latch corresponding to a secondary function RxDC must be programmed to one for that function to operate. The secondary functions are assigned to the two pins of port 4 as follows: P4.0/TxDC: Transmitter output of CAN controller P4.1/RxDC: Receiver input of CAN controller. It can drive CMOS inputs without external pull-ups. RESET I/O Reset: A high level on this pin during two machine cycles while the oscillator is running resets the device. An internal pull-down resistor to VSS permits power-on reset using only an external capacitor to VCC. XTAL1 I XTAL1: Input of the inverting oscillator amplifier and input of the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate above a frequency of 16 MHz, a duty cycle of 50% should be maintained. XTAL2 O XTAL2: Output from the inverting oscillator amplifier. Pin Name Type Description

independently programmed as input or output. for its alternate input output function. ister (x = 1 to 4). To use a pin for general- purpose input, set the bit in the Px register. This turns off the output FET drive. Figure 1. Ports Structure Note: 1. The internal pull-up can be disabled on P1 when analog function is selected.

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rather than the pins returns the correct logic one value. returned to input conditions by a logic one written to the latch. ify-Write instruction cycle. Table 1. Read/Modify/Write Instructions

strengths are 1/10 that of pFET #3. Figure 2. Internal Pull-up Configurations

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Table 2. C51 Core SFRs Table 3. I/O Port SFRs Table 4. Timers SFRs

1 Modes GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00

Table 4. Timers SFRs (Continued) Table 5. Serial I/O Port SFRs Table 6. PCA SFRs

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Table 6. PCA SFRs (Continued) Table 7. Interrupt SFRs Table 8. ADC SFRs Table 9. CAN SFRs

12 TIMSTMP 11 TIMSTMP

10 TIMSTMP 9 TIMSTMP 8

Table 9. CAN SFRs (Continued)

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Table 10. Other SFRs

Notes: 1. These registers are bit-addressable. whose address ends in 0 and 8. The bit addresses, in this area, are 0x80 through to 0xFF.

1. AUXR1 bit ENBOOT is initialized with the content of the BLJB bit inverted.

Table 11. SFR Mapping

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4126L–CAN–01/08 Clock The T89C51CC02 core needs only 6 clock per iods per machine cycle. This feature, called “X2”, provides the following advantages:  Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power.  Saves power consumption while keeping the same CPU power (oscillator power saving).  Saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes.  Increases CPU power by 2 while keeping the same crystal frequency. In order to keep the original C51 compatibility, a divider-by-2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by the software. An extra feature is available to start after Reset in the X2 Mode. This feature can be enabled by a bit X2B in the Hardware Security Byte. This bit is described in the section ’In-System Programming’. Description The X2 bit in the CKCON register (See Table 12) allows switching from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 Mode) for the CPU Clock only (See Figure 3). The Timers 0, 1 and 2, Uart, PCA, watchdog or CAN switch in X2 Mode only if the corre- sponding bit is cleared in the CKCON register. The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1 input. In X2 Mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 3. shows the clock generation block diagram. The X2 bit is validated on the XTAL1 ÷ 2 rising edge to avoid glitches when switching from the X2 to the STD mode. Figure 4 shows the mode switching waveforms.

Figure 3. Clock CPU Generation Diagram

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Figure 4. Mode Switching Waveforms(1)

4126L–CAN–01/08 Register Table 12. CKCON Register CKCON (S:8Fh) Clock Control Register Note: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit has no effect. Reset Value = 0000 0000b 76543210 CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 Bit Number Bit Mnemonic Description 7C A N X 2 CAN Clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 6W D X 2 Watchdog Clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 5P C A X 2 Programmable Counter Array Clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 4S I X 2 Enhanced UART clock (MODE 0 and 2) (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 3T 2 X 2 Timer 2 Clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 2T 1 X 2 Timer 1 Clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 1T 0 X 2 Timer 0 Clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 0X 2 CPU Clock Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6 clock periods per machine cycle (X2 Mode) and to enable the individual peripherals ’X2’ bits.

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cally divided by 2 using the X2 Mode detailed in Section “Clock”. internal reset source such as a watchdog, PCA, timer, etc.  The level on xtal1 input must be outside the specification (VIH, VIL).  Oscillator startup time (oscrst). To determine the capacitor the highest value of these two parameters has to be chosen. The reset circuitry is shown in Figure 5. Figure 5. Reset Circuitry two values of oscillator start-up time and two pull-down resistor values. Table 13. Minimum Reset Capacitor for a 50K Pull-down Resistor

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4126L–CAN–01/08 Reset Recommendation to Prevent Flash Corruption When a Flash program memory is embedded on-chip, it is strongly recommended to use an external reset chip (brown out device) to apply a reset (Figure 7). It prevents sys- tem malfunction during periods of insufficient power-supply voltage (power-supply failure, power supply switched off, etc.). Idle Mode Idle mode is a power reduction mode that reduces the power consumption. In this mode, program execution halts. Idle mode freezes the clock to the CPU at known states while the peripherals continue to be clocked. The CPU status before entering Idle mode is preserved, i.e., the program counter and program status word register retain their data for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The status of the Port pins during Idle mode is detailed in Table 15. Entering Idle Mode To enter Idle mode, set the IDL bit in PCON register (See Table 16). The A/T89C51CC02 enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed. Note: If IDL bit and PD bit are set simultaneously, the A/T89C51CC02 enters Power-down mode. Then it does not go in Idle mode when exiting Power-down mode. Exiting Idle Mode There are two ways to exit Idle mode: 1. Generate an enabled interrupt. Hardware clears IDL bit in PCON register which restores the clock to the CPU. Exe- cution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately follow- ing the instruction that activated Idle mode. The general purpose flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt occurred dur- ing normal operation or during Idle mode. When Idle mode is exited by an interrupt, the interrupt service routine may examine GF1 and GF0. 2. Generate a reset. A logic high on the RST pin clears IDL bit in PCON register directly and asynchro- nously. This restores the clock to the CPU. Program execution momentarily resumes with the instruction immediately following the instruction that activated the Idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the A/T89C51CC02 and vectors the CPU to address C:0000h. Notes: 1. During the time that execution resumes, the internal RAM cannot be accessed; how- ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction immediately following the instruction that activated Idle mode should not write to a Port pin or to the external RAM. 2. If Idle mode is invoked by ADC Idle, the ADC conversion completion will exit Idle. Power-down Mode The Power-down mode places the A/T89C51CC02 in a very low power state. Power- down mode stops the oscillator, freezes all clock at known states. The CPU status prior to entering Power-down mode is preserved, i.e., the program counter, program status word register retain their data for the duration of Power-down mode. In addition, the SFRs and RAM contents are preserved. The status of the Port pins during Power-down mode is detailed in Table 15. Entering Power-down Mode To enter Power-down mode, set PD bit in PCON register. The A/T89C51CC02 enters the Power-down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed.

VDD is restored to the normal operating level.

1. Generate an enabled external interrupt.

following the instruction that activated Power-down mode. the duration of the interrupt must be long enough to allow the oscillator to stabilize. The execution will only resume when the interrupt is deasserted.

1. Exit from power-down by external interrupt does not affect the SFRs nor the internal

Figure 8. Power-down Exit Waveform Using INT1:0# vectors the CPU to address 0000h. Power-down mode should not write to a Port pin or to the external RAM.

1. Exit from power-down by reset redefines all the SFRs, but does not affect the internal

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Table 15. Pin Conditions in Special Operating Modes

4126L–CAN–01/08 Registers Table 16. PCON Register PCON (S:87h) Power Control Register Reset Value = 00X1 0000b Not bit addressable 76543210 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Number Bit Mnemonic Description 7S M O D 1 Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. 6S M O D 0 Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4P O F Power-off Flag Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. 3G F 1 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. 2G F 0 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. 1P D Power-down Mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. 0I D L Idle Mode bit Clear by hardware when interrupt or reset occurs. Set to enter idle mode.

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 The lower 128 Bytes RAM segment.  The upper 128 Bytes RAM segment.  The expanded 256 Bytes RAM segment (XRAM). SFRs, (addresses 80h to FFh) accessible by direct addressing mode. Figure 9 shows the internal data memory spaces organization. Figure 9. Internal memory - RAM ing, and can be used for context switching in interrupt service routines. Table 17. Register Bank Selection addresses in this area are 00h to 7Fh.

256 Bytes

128 Bytes

Figure 10. Lower 128 Bytes Internal RAM Organization must then be initialized properly.

4 Banks of

8 Registers

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and reducing code size in case of intensive usage of external memory accesses. Figure 11. Dual Data Pointer Implementation using one data pointer as a “source” pointer and the other one as a “destination” pointer. enhanced algorithm libraries.

4126L–CAN–01/08 Registers Table 18. PSW Register PSW (S:D0h) Program Status Word Register Reset Value = 0000 0000b 76543210 CY AC F0 RS1 RS0 OV F1 P Bit Number Bit Mnemonic Description 7C Y Carry Flag Carry out from bit 1 of ALU operands. 6A C Auxiliary Carry Flag Carry out from bit 1 of addition operands. 5F 0 User Definable Flag 0 4 - 3 RS1:0 Register Bank Select bits Refer to Table 17 for bits description. 2O V Overflow Flag Overflow set by arithmetic operations. 1F 1 User Definable Flag 1 Parity bit Set when ACC contains an odd number of 1’s. Cleared when ACC contains an even number of 1’s.

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Table 19. AUXR1 Register The value read from these bits is indeterminate. Do not set these bits.

5 ENBOOT (1)

Clear this bit to disable boot Flash. The value read from this bit is indeterminate. Do not set this bit. Set to select second dual data pointer: DPTR1. Clear to select first dual data pointer: DPTR0.

4126L–CAN–01/08 EEPROM Data Memory The 2K bytes on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/XRAM memory space and is selected by setting control bits in the EECON register. A read in the EEPROM memory is done with a MOVX instruction. A physical write in the EEPROM memory is done in two steps: write data in the column latches and transfer of all data latches into an EEPROM memory row (programming). The number of data written on the page may vary from 1 up to 128 Bytes (the page size). When programming, only the data written in the column latch is programmed and a ninth bit is used to obtain this feature. This provides the capability to program the whole memory by Bytes, by page or by a number of Bytes in a page. Indeed, each ninth bit is set when the writing the corresponding byte in a row and all these ninth bits are reset after the writing of the complete EEPROM row. Write Data in the Column Latches Data is written by byte to the column latches as for an external RAM memory. Out of the 11 address bits of the data pointer, the 4 MSBs are used for page selection (row) and 7 are used for byte selection. Between two EEPROM programming sessions, all the addresses in the column latches must stay on the same page, meaning that the 4 MSB must no be changed. The following procedure is used to write to the column latches:  Save and disable interrupt  Set bit EEE of EECON register  Load DPTR with the address to write  Store A register with the data to be written  Execute a MOVX @DPTR, A  If needed loop the three last instructions until the end of a 128 Bytes page  Restore interrupt Note: The last page address used when loading the column latch is the one used to select the page programming address. Programming The EEPROM programming consists of the following actions:  Write one or more Bytes of one page in the column latches. Normally, all Bytes must belong to the same page; if not, the last page address will be latched and the others discarded.  Launch programming by writing the control sequence (50h followed by A0h) to the EECON register.  EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress and that the EEPROM segment is not available for reading.  The end of programming is indicated by a hardware clear of the EEBUSY flag. Note: The sequence 5xh and Axh must be executed without instructions between then other- wise the programming is aborted. Read Data The following procedure is used to read the data stored in the EEPROM memory:  Save and disable interrupt  Set bit EEE of EECON register  Load DPTR with the address to read  Execute a MOVX A, @DPTR  Restore interrupt

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4126L–CAN–01/08 ;* NAME: api_rd_eeprom_byte ;* DPTR contain address to read. ;* Acc contain the reading value ;* NOTE: before execute this function, be sure the EEPROM is not BUSY api_rd_eeprom_byte: ; Save and clear EA MOV EECON, #02h; map EEPROM in XRAM space MOVX A, @DPTR MOV EECON, #00h; unmap EEPROM ; Restore EA ret ;* NAME: api_ld_eeprom_cl ;* DPTR contain address to load ;* Acc contain value to load ;* NOTE: in this example we load only 1 byte, but it is possible upto ;* 128 Bytes. ;* before execute this function, be sure the EEPROM is not BUSY api_ld_eeprom_cl: ; Save and clear EA MOV EECON, #02h ; map EEPROM in XRAM space MOVX @DPTR, A MOVEECON, #00h; unmap EEPROM ; Restore EA ret ;* NAME: api_wr_eeprom ;* NOTE: before execute this function, be sure the EEPROM is not BUSY api_wr_eeprom: ; Save and clear EA MOV EECON, #050h MOV EECON, #0A0h ; Restore EA ret

4126L–CAN–01/08 Registers Table 20. EECON Register EECON (S:0D2h) EEPROM Control Register Reset Value = XXXX XX00b Not bit addressable 76543210 EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY Bit Number Bit Mnemonic Description 7 - 4 EEPL3-0 Programming Launch Command bits Write 5Xh followed by AXh to EEPL to launch the programming. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2- Reserved The value read from this bit is indeterminate. Do not set this bit. 1E E E Enable EEPROM Space bit Set to map the EEPROM space during MOVX instructions (Write in the column latches) Clear to map the XRAM space during MOVX. 0E E B U S Y Programming Busy Flag Set by hardware when programming is in progress. Cleared by hardware when programming is done. Can not be set or cleared by software.

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The T89C51CC02 implement 16K Bytes of on-chip program/code memory. Figure 12. Program/Code Memory Organization 2K Bytes for boot loader and Application Programming Interfaces (API). ’In-System Programming’ section. a set of API described in the ’In-System Programming’ section. Figure 13. Flash Memory Architecture

4126L–CAN–01/08 FM0 Memory Architecture The Flash memory is made up of 4 blocks (See Figure 13): 1. The memory array (user space) 16K Bytes 2. The Extra Row 3. The Hardware security bits 4. The column latch registers User Space This space is composed of a 16K Bytes Fl ash memory organized in 128 pages of 128 Bytes. It contains the user’s application code. Extra Row (XRow) This row is a part of FM0 and has a size of 128 Bytes. The extra row may contain infor- mation for boot loader usage. Hardware Security Byte The Hardware security Byte space is a part of FM0 and has a size of 1 byte. The 4 MSB can be read/written by software, the 4 LSB can only be read by software and written by hardware in parallel mode. Column Latches The column latches, also part of FM0, have a size of full page (128 Bytes). The column latches are the entrance buffers of the three previous memory locations (user array, XROW and Hardware security byte). Cross Flash Memory Access

Description

The FM0 memory can be programmed as describe on Table 21. Programming FM0 from FM0 is impossible. The FM1 memory can be program only by parallel programming. Table 21 show all software Flash access allowed. Table 21. Cross Flash Memory Access

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The CPU interfaces the Flash memory through the FCON register and AUXR1 register. page while bits 14 to 7 are used to select the programming address of the page. Setting FPS bit takes precedence on the EEE bit in EECON register. dance with Table 22. A MOVC instruction is then used for reading these spaces. Table 22. FM0 blocks Select bits spaces to program according to FMOD1:0 bits. Table 23. Programming Spaces wise the programming is aborted. ous exit of the programming mode.

11 R e s e r v e d

4126L–CAN–01/08 Status of the Flash Memory The bit FBUSY in FCON register is used to indicate the status of programming. FBUSY is set when programming is in progress. Selecting FM1 The bit ENBOOT in AUXR1 register is used to map FM1 from F800h to FFFFh. Loading the Column Latches Any number of data from 1 byte to 128 Bytes can be loaded in the column latches. This provides the capability to program the whole memory by byte, by page or by any number of Bytes in a page. When programming is launched, an automatic erase of the locations loaded in the col- umn latches is first performed, then programming is effectively done. Thus no page or block erase is needed and only the loaded data are programmed in the corresponding page. The following procedure is used to load the column latches and is summarized in Figure 14:  Save then disable interrupt and map the column latch space by setting FPS bit.  Load the DPTR with the address to load.  Load Accumulator register with the data to load.  Execute the MOVX @DPTR, A instruction.  If needed loop the three last instructions until the page is completely loaded.  unmap the column latch and Restore Interrupt

38 AT/T89C51CC02

Figure 14. Column Latches Loading Procedure(1) the page programming address.  Load up to one page of data in the column latches from address 0000h to 3FFFh.  Save then disable the interrupts. FCON register.This step must be executed from FM1. The end of the programming indicated by the FBUSY flag cleared.  Load data in the column latches from address FF80h to FFFFh.  Save then disable the interrupts. FCON register. This step of the procedure must be executed from FM1. The end of the programming indicated by the FBUSY flag cleared.

Figure 15. Flash and Extra row Programming Procedure  Save then disable the interrupts.  Load DPTR at address 0000h.  Load Accumulator register with the data to load.  Execute the MOVX @DPTR, A instruction. FCON register. This step of the procedure must be executed from FM1. The end of the programming indicated by the FBusy flag cleared.

40 AT/T89C51CC02

Figure 16. Hardware Programming Procedure the address of the code byte to read. Note: FCON must be cleared (00h) when not used.  Map the Extra Row space by writing 02h in FCON register.  Clear FCON to unmap the Extra Row.  Map the Hardware Security space by writing 04h in FCON register.  Clear FCON to unmap the Hardware Security Byte.

Figure 17. Reading Procedure Note: aa = 10 for the Hardware Security Byte. chip code and data located in FM0 and FM1. The only way to write this bits are the parallel mode. They are set by default to level 3. Table 24. Program Lock bit Preventing Flash Corruption See Section “Power Management”. 1 U U U No program lock features enabled. 2 P U U Parallel programming of the Flash is disabled. disabled. This is the factory defaul programming.

42 AT/T89C51CC02

4126L–CAN–01/08 Registers Table 25. FCON Register FCON Register FCON (S:D1h) Flash Control Register Reset Value = 0000 0000b 76543210 FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY Bit Number Bit Mnemonic Description 7 - 4 FPL3:0 Programming Launch Command bits Write 5Xh followed by AXh to launch the programming according to FMOD1:0. (See Table 23.) 3F P S Flash Map Program Space Set to map the column latch space in the data memory space. Clear to re-map the data memory space. 2 - 1 FMOD1:0 Flash Mode See Table 22 or Table 23. 0F B U S Y Flash Busy Set by hardware when programming is in progress. Clear by hardware when programming is done. Can not be changed by software.

4126L–CAN–01/08

44 AT/T89C51CC02

Table 26. Cross Memory Access

Table 28. Read MOVX A, @DPTR Table 29. Write MOVX @DPTR,A

00 X O K

01 X O K

10 X O K

11 X O K

46 AT/T89C51CC02

Table 30. Read MOVC A, @DPTR

1. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from
2. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from

can be ordered with CAN bootloader or UART bootloader). Note: 1. The user can also program his own bootloader in FM1. This ISP allows code modification over the total lifetime of the product. This allow the customer to have a full use of the 16-Kbyte user memory. bootloader located in FM0 at [SBV]00h.  A further method exist in activating the Atmel boot loader by hardware activation. See the Section “Hardware Security Byte”.  The FM0 can be programmed also by the parallel mode using a programmer. Figure 18. Flash Memory Mapping

48 AT/T89C51CC02

the different flags and Bytes. @0000h on FM0 or execute the boot loader at address @F800h on FM1. -To read or modify this bit, the APIs are used.

• This byte contains the MSB of the user boot loader address in FM0.
• The default value of SBV is FCh (no user boot loader in FM0).
• To read or modify this byte, the APIs are used.
• These Bytes are reserved for customer use.
• To read or modify these Bytes, the APIs are used.

Figure 19. Hardware Boot Process Algorithm All these APIs are described in detail in the following documents on the Atmel web site. – Datasheet Bootloader CAN T89C51CC02. – Datasheet Bootloader UART T89C51CC02. Is Initialized with BLJB Inverted.

cific purpose in conjonction with the bootloader. Table 31. XROW Mapping met, the chip will start executing the bootloader at the end of the Reset. See a detailed description in the applicable Document. – Datasheet Bootloader CAN T89C51CC02. – Datasheet Bootloader UART T89C51CC02.

50 AT/T89C51CC02

4126L–CAN–01/08 Hardware Security Byte Table 32. Hardware Security byte After erasing the chip in parallel mode, the default value is : FFh The erasing in ISP mode (from bootloader) does not modify this byte. Notes: 1. Only the 4 MSB bits can be accessed by software. 2. The 4 LSB bits can only be accessed by parallel mode. 76543210 X2B BLJB - - - LB2 LB1 LB0 Bit Number Bit Mnemonic Description 7X 2 B X2 bit Set this bit to start in standard mode Clear this bit to start in X2 Mode. 6B L J B Boot Loader Jump bit - 1: To start the user’s application on next RESET (@0000h) located in FM0, - 0: To start the boot loader(@F800h) located in FM1. 5 - 3 - Reserved The value read from these bits are indeterminate. 2 - 0 LB2:0 Lock bits (see Table 22)

52 AT/T89C51CC02

Figure 22. UART Timing in Mode 1 Figure 23. UART Timing in Modes 2 and 3 nication feature is enabled (SM2 bit in SCON register is set). the CPU is not interrupted by command frames addressed to other devices. If necessary, the user can enable the automatic address recognition feature in mode 1. be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect). more slaves at a time. The following example illustrates how a given address is formed.

4126L–CAN–01/08 Here is an example of how to use given addresses to address different slaves: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0011b SADEN1111 1101b Given1111 00X1b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To com- municate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b). Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t-care bits, e.g.: SADDR 0101 0110b SADEN 1111 1100b SADDR OR SADEN1111 111Xb The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 1X11b, Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 1X11B, Slave C:SADDR=1111 0010b SADEN1111 1101b Given1111 1111b For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh.

54 AT/T89C51CC02

Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. Refer to SM1 for serial port mode selection. Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3. Clear to disable serial reception. Set to enable serial reception. Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit. Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. Clear to acknowledge interrupt. stop bit in the other modes. Clear to acknowledge interrupt. Figure 23. in the other modes.

Table 34. SADEN Register Table 35. SADDR Register Table 36. SBUF Register

56 AT/T89C51CC02

Table 37. PCON Register Set to select double baud rate in mode 1, 2 or 3. Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register. The value read from this bit is indeterminate. Do not set this bit. Clear to recognize next reset type. Cleared by user for general purpose usage. Set by user for general purpose usage. Cleared by user for general purpose usage. Set by user for general purpose usage. Cleared by hardware when reset occurs. Set to enter power-down mode. Clear by hardware when interrupt or reset occurs.

4126L–CAN–01/08 Timers/Counters The T89C51CC02 implements two general-purpose, 16-bit Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, the Timer/Counter counts negative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request. The various operating modes of each Timer/Counter are described in the following sections. Timer/Counter Operations A basic operation is Timer registers THx and TLx (x = 0, 1) connected in cascade to form a 16-bit Timer. Setting the run control bit (TRx) in TCON register (See Figure 38) turns the Timer on by allowing the selected input to increment TLx. When TLx overflows it increments THx; when THx overflows it sets the Timer overflow flag (TFx) in TCON register. Setting the TRx does not clear the THx and TLx Timer registers. Timer regis- ters can be accessed to obtain the current count or to enter preset values. They can be read at any time but TRx bit must be cleared to preset their values, otherwise the behav- ior of the Timer/Counter is unpredictable. The C/Tx# control bit selects Timer operation or Counter operation by selecting the divided-down peripheral clock or external pin Tx as the source for the counted signal. TRx bit must be cleared when changing the mode of operation, otherwise the behavior of the Timer/Counter is unpredictable. For Timer operation (C/Tx# = 0), the Timer register counts the divided-down peripheral clock. The Timer register is incremented once every peripheral cycle (6 peripheral clock periods). The Timer clock rate is f PER/6, i.e. f OSC/12 in standard mode or f OSC/6 in X2 Mode. For Counter operation (C/Tx# = 1), the Timer register counts the negative transitions on the Tx external input pin. The external input is sampled every peripheral cycles. When the sample is high in one cycle and low in the next one, the Counter is incremented. Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition, the maximum count rate is f PER/12, i.e. fOSC/24 in standard mode or fOSC/12 in X2 Mode. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full peripheral cycle. Timer 0 Timer 0 functions as either a Timer or event Counter in four modes of operation. Figure 24 through Figure 27 show the logical configuration of each mode. Timer 0 is controlled by the four lower bits of TMOD register (See Figure 39) and bits 0, 1, 4 and 5 of TCON register (See Figure 38). TMOD register selects the method of Timer gating (GATE0), Timer or Counter operation (T/C0#) and mode of operation (M10 and M00). TCON register provides Timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0). For normal Timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by the selected input. Setting GATE0 and TR0 allows external pin INT0# to control Timer operation. Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an inter- rupt request. It is important to stop Timer/Counter before changing mode.

58 AT/T89C51CC02

ignored. Prescaler overflow increments TH0 register. Figure 24. Timer/Counter x (x= 0 or 1) in Mode 0 cascade (See Figure 25). The selected input increments TL0 register. Figure 25. Timer/Counter x (x= 0 or 1) in Mode 1 reload value may be changed at any time by writing it to TH0 register.

60 AT/T89C51CC02

and out of mode 3 to turn it off and on.  It is important to stop Timer/Counter before changing mode. cascade (See Figure 25). The selected input increments TL1 register. Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in mode 3. interrupts are globally enabled by setting EA bit in IEN0 register. Figure 28. Timer Interrupt System

4126L–CAN–01/08 Registers Table 38. TCON Register TCON (S:88h) Timer/Counter Control Register Reset Value = 0000 0000b 76543210 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Number Bit Mnemonic Description 7T F 1 Timer 1 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 1 register overflows. 6T R 1 Timer 1 Run Control bit Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1. 5T F 0 Timer 0 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 0 register overflows. 4T R 0 Timer 0 Run Control bit Clear to turn off Timer/Counter 0. Set to turn on Timer/Counter 0. 3I E 1 Interrupt 1 Edge Flag Cleared by hardware when interrupt is processed if edge-triggered (See IT1). Set by hardware when external in terrupt is detected on INT1# pin. 2I T 1 Interrupt 1 Type Control bit Clear to select low level active (level triggered) for external interrupt 1 (INT1#). Set to select falling edge active (edge triggered) for external interrupt 1. 1I E 0 Interrupt 0 Edge Flag Cleared by hardware when interrupt is processed if edge-triggered (See IT0). Set by hardware when external in terrupt is detected on INT0# pin. 0I T 0 Interrupt 0 Type Control bit Clear to select low level active (level triggered) for external interrupt 0 (INT0#). Set to select falling edge active (edge triggered) for external interrupt 0.

62 AT/T89C51CC02

Table 39. TMOD Register Notes: 1. Reloaded from TH1 at overflow.

1. Reloaded from TH0 at overflow.

Table 40. TH0 Register Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set. Clear for Timer operation: Timer 1 counts the divided-down system clock. Set for Counter operation: Timer 1 counts negative transitions on external pin T1. 0 0 Mode 0: 8-bit Timer/Counter (TH1) with 5bit prescaler (TL1). 0 1 Mode 1: 16-bit Timer/Counter. 1 1 Mode 3: Timer 1 halted. Retains count. 1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL1). Clear to enable Timer 0 whenever TR0 bit is set. Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set. Clear for Timer operation: Timer 0 counts the divided-down system clock. Set for Counter operation: Timer 0 counts negative transitions on external pin T0. 0 0 Mode 0: 8-bit Timer/Counter (TH0) with 5bit prescaler (TL0). 0 1 Mode 1: 16-bit Timer/Counter. 1 1 Mode 3: TL0 is an 8-bit Timer/Counter. TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 bits.

0 M00

Table 41. TL0 Register Table 42. TH1 Register Table 43. TL1 Register

64 AT/T89C51CC02

Timer 2 The T89C51CC02 Timer 2 is compatible with Timer 2 in the 80C52. timer clock. Setting TR2 allows TL2 to be incremented by the selected input. this mode the T2EX pin controls the counting direction. in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2. timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers. Figure 29. Auto-Reload Mode Up/Down Counter

 Set T2OE bit in T2MOD register. reload value or different depending on the application.  To start the timer, set TR2 run control bit in T2CON register. independent since both functions use the values in the RCAP2H and RCAP2L registers. Figure 30. Clock-Out Mode

66 AT/T89C51CC02

4126L–CAN–01/08 Registers Table 44. T2CON Register T2CON (S:C8h) Timer 2 Control Register Reset Value = 0000 0000b bit addressable 76543210 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Bit Number Bit Mnemonic Description 7T F 2 Timer 2 Overflow Flag TF2 is not set if RCLK=1 or TCLK = 1. Must be cleared by software. Set by hardware on Timer 2 overflow. 6E X F 2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. Set to cause the CPU to vector to Timer 2 interrupt routine when Timer 2 interrupt is enabled. Must be cleared by software.

5 RCLK

Clear to use timer 1 overflow as receiv e clock for serial port in mode 1 or 3. Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3. 4T C L K Transmit Clock bit Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3. 3E X E N 2 Timer 2 External Enable bit Clear to ignore events on T2EX pin for Timer 2 operation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if Timer 2 is not used to clock the serial port. 2T R 2 Timer 2 Run Control bit Clear to turn off Timer 2. Set to turn on Timer 2. 1C / T 2 # Timer/Counter 2 Select bit Clear for timer operation (input from internal clock system: f OSC). Set for counter operation (input from T2 input pin).

0 CP/RL2#

Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on Timer 2 overflow. Clear to auto-reload on Timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1.

Table 45. T2MOD Register Table 46. TH2 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. Clear to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output.

0 DCEN

Clear to disable Timer 2 as up/down counter. Set to enable Timer 2 as up/down counter.

68 AT/T89C51CC02

Table 47. TL2 Register Table 48. RCAP2H Register Table 49. RCAP2L Register 7 - 0 High Byte of Timer 2 Reload/Capture. 7 - 0 Low Byte of Timer 2 Reload/Capture.

ter. When exiting reset, the WDT is -by default- disable. Note: When the watchdog is enable it is impossible to change its period. Figure 31. Watchdog Timer

70 AT/T89C51CC02

Table 50. Machine Cycle Count Table 51. Timeout Computation

4126L–CAN–01/08 Watchdog Timer During Power-down Mode and Idle In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are 2 methods of exiting Power-down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, the watchdog is disabled. Exiting Power-down with an interrupt is signif- icantly different. The interrupt shall be held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down. To ensure that the WDT does not overflow within a few states of exiting powerdown, it is best to reset the WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting T89C51CC02 while in Idle mode, the user should always set up a timer that will periodi- cally exit Idle, service the WDT, and re-enter Idle mode. Register Table 52. WDTPRG Register WDTPRG (S:A7h) – Watchdog Timer Duration Programming register Reset Value = XXXX X000b 76543210 ----- S 2 S 1 S 0 Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2S 2 Watchdog Timer Duration selection bit 2 Work in conjunction with bit 1 and bit 0. 1S 1 Watchdog Timer Duration selection bit 1 Work in conjunction with bit 2 and bit 0. 0S 0 Watchdog Timer Duration selection bit 0 Work in conjunction with bit 1 and bit 2.

72 AT/T89C51CC02

Table 53. WDTRST Register sequence without instruction between these two sequences.

1 Crystal frequency in X2 Mode. Note: 1. At BRP = 1 sampling point will be fixed. and ISO 11519-2 for low speed. dynamically. The identifier with the lowest binary number has the highest priority. highest priority and do not re-attempt transmission until the bus is available again. as CAN 2.0 B, supports a length of 29 bits for the identifier. Figure 32. CAN Standard Frames

74 AT/T89C51CC02

there is no following bus access by any node, the bus remains idle. Figure 33. CAN Extended Frames frame in CAN standard frame format, and transmitted as recessive in the other case. has priority over the message in extended format. ing edge SOF and on each recessive to dominant edge. the smallest discrete timing resolution used by a CAN node.

Figure 34. CAN Bit Construction Synchronization Segment The first segment is used to synchronize the various bus nodes. is expected to occur within this segment by the receiving nodes. Propagation Time Segment This segment is used to compensate for signal delays across the network. through the transceivers of the bus nodes. Phase Segment 1 Phase Segment 1 is used to compensate for edge phase errors. This segment may be lengthened during resynchronization. Phase Segment 2 This segment is also used to compensate for edge phase errors. Information Processing Time It is the time required for the logic to determine the bit level of a sampled bit. less than the Information processing Time. adjust the sample point and the end of the bit time.

76 AT/T89C51CC02

Resynchronization Jump Width. This segment may not be longer than Phase Segment 2. Programming the Sample Point Programming of the sample point allows "tuning" of the characteristics to suit the bus. so that lower cost oscillators such as ceramic resonators may be used. a poorer bus topology and maximum bus length. Figure 35. Bus Arbitration Multiple Access with Arbitration on Message Priority”. the most important message is sent first without time loss. same time, the data frame prevails over the remote frame (c.f. RTR bit). the received bits. If they do not agree there has been a CRC error.

4126L–CAN–01/08 fields against the fixed format and the frame size. Errors detected by frame checks are designated "format errors".  ACK Errors As already mentioned frames received are acknowledged by all receivers through positive acknowledgement. If no acknowledgement is received by the transmitter of the message an ACK error is indicated. Error at Bit Level  Monitoring The ability of the transmitter to detect errors is based on the monitoring of bus signals. Each node which transmits also observes the bus level and thus detects differences between the bit sent and the bit received. This permits reliable detection of global errors and errors local to the transmitter.  Bit Stuffing The coding of the individual bits is tested at bit level. The bit representation used by CAN is "Non Return to Zero (NRZ)" coding, which guarantees maximum efficiency in bit coding. The synchronization edges are generated by means of bit stuffing. Error Signalling If one or more errors are discovered by at least one node using the above mechanisms, the current transmission is aborted by sending an "error flag". This prevents other nodes accepting the message and thus ensures the consistency of data throughout the net- work. After transmission of an erroneous message that has been aborted, the sender automatically re-attempts transmission. CAN Controller The CAN controller accesses are made through SFR. Several operations are possible by SFR:  arithmetic and logic operations, transfers and program control (SFR is accessible by direct addressing).  4 independent message objects are implemented, a pagination system manages their accesses. Any message object can be programmed in a reception buffer block (even non-consec- utive buffers). For the reception of defined messages one or several receiver message objects can be masked without participating in the buffer feature. An IT is generated when the buffer is full. The frames following the buffer-full interrupt will not be taken into account until at least one of the buffer message objects is re-enabled in reception. Higher priority of a message object for reception or transmission is given to the lower message object number. The programmable 16-bit Timer (CANTIMER) is used to stamp each received and sent message in the CANSTMP register. This timer starts counting as soon as the CAN con- troller is enabled by the ENA bit in the CANGCON register. The Time Trigger Communication (TTC) protocol is supported by the T89C51CC02.

78 AT/T89C51CC02

Figure 36. CAN Controller Block Diagram register (CANPAGE) as illustrate in Figure 37.

Figure 37. CAN Controller Memory Organization

4 Message Objects

8 Bytes

80 AT/T89C51CC02

each access. The range of this counter is 8. Note that the maibox is a pure RAM, dedicated to one message object, without overlap. lations or tests can be executed in the mailbox area which provide quicker access. – Message object Status (CANSTCH). view of the message objects availability. The CAN messages can be handled by interrupt or polling modes. Table 54. Configuration for CONCH1:2 object, it is necessary to re-write the configuration in CANCONCH register. (Transmitter, Receiver and Receiver buffer).

10 R e c e i v e r

sage objects, and with no limitation in number of message objects used up to 4. Figure 38. Buffer Mode The same acceptance filter must be defined for each message objects of the buffer. When there is no mask on the identifier or the IDE, all messages are accepted. A received frame will always be stored in the lowest free message object. the message object re-enabled in buffer reception in order to free the message object. message objects is re-enabled in reception. This flag must be cleared by the software in order to acknowledge the interrupt.

82 AT/T89C51CC02

Figure 39. CAN Controller Interrupt Structure

4126L–CAN–01/08 To enable an interrupt on Buffer-full condition:  Enable General CAN IT in the interrupt system register  Enable interrupt on Buffer full, ENBUF To enable an interrupt when Timer overruns:  Enable Overrun IT in the interrupt system register When an interrupt occurs, the corresponding message object bit is set in the SIT register. To acknowledge an interrupt, the corresponding CANSTCH bits (RXOK, TXOK,...) or CANGIT bits (OVRTIM, OVRBUF,...), must be cleared by the software application. When the CAN node is in transmission and detects a Form Error in its frame, a bit Error will also be raised. Consequently, two consecutive interrupts can occur, both due to the same error. When a message object error occurs and is set in CANSTCH register, no general error are set in CANGIE register.

84 AT/T89C51CC02

quantum. So, the input clock for bit timing is the clock used into CAN channel FSM’s.  TQ: Time Quantum (output of Baud Rate Prescaler).  SYNS: SYNchronization Segment is 1 TQ long.  PRS: PRopagation time Segment is programmable to be 1, 2, ..., 8 TQ long.  PHS1: PHase Segment 1 is programmable to be 1, 2, ..., 8 TQ long.  INFORMATION PROCESSING TIME is 2 TQ. The total number of TQ in a bit time has to be programmed at least from 8 to 25. Figure 40. Sample and Transmission Point

Figure 41. General Structure of a bit Period Verify that the CAN baud rate you want is an integer division of FCAN clock.

86 AT/T89C51CC02

when the CAN macro detects an error. transmission, an error passive unit will wait before initiating further transmission. A bus off unit is not allowed to have any influence on the bus. For fault confinement, two error counters (TEC and REC) are implemented. See CAN Specification for details on Fault confinement. Figure 42. Line Error Mode

11 Consecutive

ID+RTR+RB+IDE received are written over the ID TAG Registers. Figure 43. Acceptance Filter Block Diagram To accept only ID = 318h in part A.

88 AT/T89C51CC02

4126L–CAN–01/08 Data and Remote Frame Description of the different steps for:  Data frame  Remote frame, with automatic reply  Remote frame u uu uu 0 1 x 0 0 u uu uu ENCH RTR RPLV TXOK RXOK 0 1 x 0 0 c uc uu 0 0 x 1 0 u cc uu 0 0 x 0 1 DATA FRAME Node A Node B ENCH RTR RPLV TXOK RXOK message object in reception message object disabled message object in transmission message object disabled u uu uu 1 1 x 0 0 c uu uc 0 1 x 1 0 u cc uu 0 0 x 0 1 REMOTE FRAME DATA FRAME u uu uu 1 1 1 0 0 u uu cc 0 1 0 0 0 c uc cu 0 0 0 1 0 ENCH RTR RPLV TXOK RXOK ENCH RTR RPLV TXOK RXOK (immediate) message object in reception message object in transmission message object disabled message object in transmission message object in reception message object disabled by CAN controller by CAN controller u uu uu 1 1 x 0 0 u uu uu ENCH RTR RPLV TXOK RXOK 1 1 0 0 0 c uu uc 0 1 x 1 0 u cc uu 1 0 0 0 1 REMOTE FRAME ENCH RTR RPLV TXOK RXOK u uu uu 0 1 x 0 0 c uc uu 0 0 x 1 0 u cc uc 0 0 x 0 1 DATA FRAME (deferred) u : modified by useri c : modified by CANi message object in reception message object in transmission by user message object disabled message object disabled message object in transmission message object in reception message object disabled by user

bit in the CANGCON register. Note: In this mode, CAN only sends the frame once, even if an error occurs. message object which received or sent the frame. – All messages can be stamps. – The stamping of a received frame occurs when the RxOk flag is set. – The stamping of a sent frame occurs when the TxOk flag is set. The CAN Timer works in a roll-over from FFFFh to 0000h which serves as a time base. in the interrupt enable register IEN1 is set. Figure 44. Block Diagram of CAN Timer

90 AT/T89C51CC02

ing the received messages. It cannot send any message. The error flags are updated. The bit timing can be adjusted until no error occurs (good configuration find). In this mode, the error counters are frozen. To go back to the standard mode, the AUTOBAUD bit must be cleared. Figure 45. Autobaud Mode

4126L–CAN–01/08 // Enable the CAN macro CANGCON = 02h 2. Configure message object 3 in reception to receive only standard (11bit identifier) message 100h // Select the message object 3 CANPAGE = 30h // Enable the interrupt on this message object CANIE = 08h // Clear the status and control register CANSTCH = 00h CANCONCH= 00h // Init the acceptance filter to accept only message 100h in standard mode CANIDT1 = 20h CANIDT2 = 00h CANIDT3 = 00h CANIDT4 = 00h CANIDM1 = FFh CANIDM2 = FFh CANIDM3 = FFh CANIDM4 = FFh // Enable channel in reception CANCONCH = 88h // enable reception Note: to enable the CAN interrupt in reception: EA = 1 ECAN = 1 CANGIE = 20h 3. Send a message on the message object 0 // Select the message object 0 CANPAGE = 00h // Enable the interrupt on this message object CANIE = 01h // Clear the Status register CANSTCH = 00h; // load the identifier to send (ex: 555h) CANIDT1 = AAh; CANIDT2 = A0h; // load data to send CANMSG = 00h CANMSG = 01h CANMSG = 02h CANMSG = 03h CANMSG = 04h CANMSG = 05h CANMSG = 06h CANMSG = 07h // configure the control register CANCONCH = 18h 4. Interrupt routine // Save the current CANPAGE

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4126L–CAN–01/08 // Find the first message object which generate an interrupt in CANSIT // Select the corresponding message object // Analyse the CANSTCH register to identify which kind of interrupt is generated // Manage the interrupt // Clear the status register CANSTCH = 00h; // if it is not a channel interrupt but a general interrupt // Manage the general interrupt and clear CANGIT register // restore the old CANPAGE

Table 55. SFR Mapping

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4126L–CAN–01/08 Registers Table 56. CANGCON Register CANGCON (S:ABh) CAN General Control Register Reset Value = 0000 0000b 7654 32 10 ABRQ OVRQ TTC SYNCTTC AUTOBAUD TEST ENA GRES Bit Number Bit Mnemonic Description 7A B R Q Abort Request Not an auto-resetable bit. A reset of the ENCH bit (message object control & DLC register) is done for each message object. The pending transmission communications are immediately aborted but the on-going communication will be terminated normally, setting the appropriate status flags, TxOk or RxOk. 6O V R Q Overload Frame Request (Initiator) . Auto-resetable bit. Set to send an overload frame after the next received message. Cleared by the hardware at the beginning of transmission of the overload frame. 5T T C Network in Timer Trigger Communication set to select node in TTC. clear to disable TTC features.

4 SYNCTTC

When this bit is set the TTC timer is caught on the last bit of the End Of Frame. When this bit is clear the TTC timer is caught on the Start Of Frame. This bit is only used in the TTC mode. 3A U T O B A U D AUTOBAUD set to active listening mode. Clear to disable listening mode 2T E S T Test mode. The test mode is intended for factory testing and not for customer use. 1E N A / S T B Enable/Standby CAN Controller When this bit is set, it enables the CAN controller and its input clock. When this bit is clear, the on-going communication is terminated normally and the CAN controller state of the machine is frozen (the ENCH bit of each message object does not change). In the standby mode, the transmitter constantly provides a recessive level; the receiver is not activated and the input clock is stopped in the CAN controller. During the disable mode, the registers and the mailbox remain accessible. Note that two clock periods are needed to start the CAN controller state of the machine. 0G R E S General Reset (Software Reset). Auto-resetable bit. This reset command is ‘ORed’ with the hardware reset in order to reset the controller. After a reset, the controller is disabled.

Table 57. CANGSTA Register The values read from this bit is indeterminate. Do not set this bit. The values read from this bit is indeterminate. Do not set this bit. Spacing if a frame must be sent. This flag does not generate an interrupt. acquires or monitors a frame. This flag does not generate an interrupt. this status bit gives the true state of a chosen mode. This flag does not generate an interrupt.

0 ERRP Error passive mode

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Table 58. CANGIT Register Note: 1. This field is Read Only. to the interrupt controller. It can be used in the case of the polling method. The values read from this bit is indeterminate. Do not set this bit. If the bit ETIM in the IE1 register is set, an interrupt is generated. Clear this bit in order to reset the interrupt. This bit is set when the buffer is full. Detection of more than five consecutive bits with the same polarity. This flag can generate an interrupt. resetable by user. message from the start of frame up to the data field. This flag can generate an interrupt. resetable by user. This flag can generate an interrupt. resetable by user. No detection of the dominant bit in the acknowledge slot. This flag can generate an interrupt. resetable by user.

Table 59. CANTEC Register Table 60. CANREC Register

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Table 61. CANGIE Register

5 ENRX

3 ENERCH

2 ENBUF

1 ENERG

The value read from this bit is indeterminate. Do not set this bit.

Table 62. CANEN Register Table 63. CANSIT Register 1 - message object is enabled. corresponding message object. 1 - IT turned on. Reset when interr upt condition is cleared by user.

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Table 64. CANIE Register Table 65. CANBT1 Register disabled with the ENA bit of the CANGCON register set to 0. No default value after reset. IECH3:0 = 0b 0000 1100 -> Enable IT’s of message objects 3 & 2. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.

Table 66. CANBT2 Register disabled with the ENA bit of the CANGCON register set to 0. No default value after reset. The value read from this bit is indeterminate. Do not set this bit. relevant signal edge of the current transmission. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.

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Table 67. CANBT3 Register disabled with the ENA bit of the CANGCON register set to 0. No default value after reset. The value read from this bit is indeterminate. Do not set this bit. segment can be shortened by the re-synchronization jump width. Information Processing Time (= 2TQ). segment can be lengthened by the re-synchronization jump width. 0 - once, at the sample point. result corresponds to the majority decision of the three values.

Table 68. CANPAGE Register Table 69. CANCONCH Register The available numbers are: 0 to 3(See Figure 37). 0 - auto-increment of the index (default value). 1 - non-auto-increment of the index. corresponding bit in the CANEN1:2 registers. 0 - CAN standard rev 2.0 A (ident = 11 bits). 1 - CAN standard rev 2.0 B (ident = 29 bits). Number of Bytes in the data field of the message. The range of DLC is from 0 up to 8. appears in the CANSTCH register.

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Table 70. CANSTCH Register No default value after reset. The incoming message does not have the DLC expected. is updated by the received DLC. The communication enabled by transmission is completed. This flag can generate an interrupt. The communication enabled by reception is completed. This flag can generate an interrupt. The bit value monitored is different from the bit value sent. during the sending of an error frame. Must be cleared by software. This flag can generate an interrupt. Detection of more than five consecutive bits with the same polarity. Must be cleared by software. This flag can generate an interrupt. message from the start of frame up to the data field. CRC error is set. Must be cleared by software. This flag can generate an interrupt. Must be cleared by software. This flag can generate an interrupt. This flag can generate an interrupt.

Table 71. CANIDT1 Register for V2.0 part A No default value after reset. Table 72. CANIDT2 Register for V2.0 part A No default value after reset. Table 73. CANIDT3 Register for V2.0 part A No default value after reset.

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Table 74. CANIDT1 for V2.0 part A No default value after reset. Table 75. CANIDT2Register for V2.0 part A No default value after reset. Table 76. CANIDT2 Register for V2.0 Part B No default value after reset. 2 RTRTAG Remote transmission request tag value. 0 RB0TAG Reserved bit 0 tag value.

Table 77. CANIDT3 Register for V2.0 Part B No default value after reset. Table 78. CANIDT4 Register for V2.0 Part B No default value after reset. 1 RB1TAG Reserved bit 1 tag value. 0 RB0TAG Reserved bit 0 tag value.

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Table 79. CANIDM1 Register for V2.0 part A No default value after reset. Table 80. CANIDM2 Register for V2.0 part A No default value after reset. Table 81. CANIDM3 Register for V2.0 part A No default value after reset. The values read from these bits are indeterminate.

Table 82. CANIDM4 Register for V2.0 part A Note: The ID Mask is only used for reception. No default value after reset. Table 83. CANIDM1 Register for V2.0 Part B Note: The ID Mask is only used for reception. No default value after reset. The value read from this bit is indeterminate. Do not set this bit.

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Table 84. CANIDM2 Register for V2.0 Part B Note: 1. The ID Mask is only used for reception. No default value after reset. Table 85. CANIDM3 Register for V2.0 Part B Note: The ID Mask is only used for reception. No default value after reset.

Table 86. CANIDM4 Register for V2.0 Part B Note: The ID Mask is only used for reception. No default value after reset. Table 87. CANMSG Register No default value after reset. The value read from this bit is indeterminate. Do not set this bit.

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Table 88. CANTCON Register Table 89. CANTIMH Register Table 90. CANTIML Register

Table 91. CANSTMPH Register Table 92. CANSTMPL Register Table 93. CANTTCH Register Table 94. CANTTCL Register

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4126L–CAN–01/08 Programmable Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of two compare/capture modules. Its clock input can be programmed to count any of the following signals:  PCA clock frequency/6 (See “clock” section)  PCA clock frequency/2  Timer 0 overflow  External input on ECI (P1.2) Each compare/capture modules can be programmed in any one of the following modes:  Rising and/or falling edge capture,  Software timer  High-speed output  Pulse width modulator When the compare/capture modules are programmed in capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. Both modules and the PCA timer overflow share one interrupt vector. The PCA timer/counter and compare/capture modules share Port 1 for external I/Os. These pins are listed below. If the pin is not used for the PCA, it can still be used for standard I/O. PCA Timer The PCA timer is a common time base for both modules (See Figure 9). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (See Table 8) and can be programmed to run at:  1/6 the PCA clock frequency.  1/2 the PCA clock frequency.  The Timer 0 overflow.  The input on the ECI pin (P1.2). PCA Component External I/O Pin 16-bit Counter P1.2/ECI 16-bit Module 0 P1.3/CEX0 16-bit Module 1 P1.4/CEX1

Figure 46. PCA Timer/Counter The CMOD register includes three additional bits associated with the PCA.  The CIDL bit which allows the PCA to stop during idle mode. CCON register to be set when the PCA timer overflows.  The CR bit must be set to run the PCA. The PCA is shut off by clearing this bit. if the ECF bit in CMOD register is set. The CF bit can only be cleared by software.

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4126L–CAN–01/08 PCA Modules Each one of the two compare/capture modules has six possible functions. It can perform:  16-bit Capture, positive-edge triggered  16-bit Capture, negative-edge triggered  16-bit Capture, both positive and negative-edge triggered  16-bit Software Timer  16-bit High Speed Output  8-bit Pulse Width Modulator. Each module in the PCA has a special function register associated with it (CCAPM0 for module 0 ...). The CCAPM0:1 registers contain the bits that control the mode that each module will operate in.  The ECCF bit enables the CCF flag in the CCON register to generate an interrupt when a match or compare occurs in the associated module.  The PWM bit enables the pulse width modulation mode.  The TOG bit when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module’s capture/compare register.  The match bit MAT when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module’s capture/compare register.  The two bits CAPN and CAPP in CCAPMn register determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled.  The bit ECOM in CCAPM register when set enables the comparator function.

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SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set. Figure 49. PCA 16-bit Software Timer and High Speed Output Mode For software Timer mode, set ECOMn and MATn. For high speed output mode, set ECOMn, MATn and TOGn.

each time a match occurs between the PCA counter and the module’s capture registers. Figure 50. PCA High Speed Output Mode

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Figure 51. PCA PWM Mode

4126L–CAN–01/08 PCA Registers Table 95. CMOD Register CMOD (S:D9h) PCA Counter Mode Register Reset Value = 0XXX X000b 76543210 CIDL - - - - CPS1 CPS0 ECF Bit Number Bit Mnemonic Description 7C I D L PCA Counter Idle Control bit Clear to let the PCA run during Idle mode. Set to stop the PCA when Idle mode is invoked. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2-1 CPS1:0 EWC Count Pulse Select bits CPS1 CPS0 Clock source 0 0 Internal Clock, FPca/6 0 1 Internal Clock, FPca/2 1 0 Timer 0 overflow 1 1 External clock at ECI/P1.2 pin (Max. Rate = FPca/4) 0E C F Enable PCA Counter Overflow Interrupt bit Clear to disable CF bit in CCON register to generate an interrupt. Set to enable CF bit in CCON register to generate an interrupt.

122 AT/T89C51CC02

Table 96. CCON Register Must be cleared by software. Clear to turn the PCA Timer/Counter off. Set to turn the PCA Timer/Counter on. PCA interrupt request if the ECCF 1 bit in CCAPM 1 register is set. Must be cleared by software. PCA interrupt request if the ECCF 0 bit in CCAPM 0 register is set. Must be cleared by software.

Table 97. CCAPnH Registers Table 98. CCAPnL Registers

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Table 99. CCAPMn Registers The Value read from this bit is indeterminate. Do not set this bit. Clear to disable the Compare function. Set to enable the Compare function.

5 CAPPn

register sets CCFx bit in CCON register, flagging an interrupt. register toggles the CEXx pin. with output waveform on CEXx pin.

0 ECCFn

Table 100. CH Register Table 101. CL Register

126 AT/T89C51CC02

4126L–CAN–01/08 Analog-to-Digital Converter (ADC) This section describes the on-chip 10-bit analog-to-digital converter of the T89C51CC02. Eight ADC channels are availabl e for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC converter to select one from the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10-bit- cascaded potentiometric ADC. Two modes of conversion are available: - Standard conversion (8 bits). - Precision conversion (10 bits). For the precision conversion, set bit PSID LE in ADCON register and start conversion. The device is in a pseudo-idle mode, the CPU does not run but the peripherals are always running. This mode allows digital noise to be as low as possible, to ensure high precision conversion. For this mode it is necessary to work with end of conversion interrupt, which is the only way to wake the device up. If another interrupt occurs during the precision conversion, it will be served only after this conversion is completed. Features  8 channels with multiplexed inputs  10-bit cascaded potentiometric ADC  Conversion time 16 micro-seconds (typ.)  Zero Error (offset) ± 2 LSB max  Positive External Reference Voltage Range (VAREF) 2.4 to 3.0-volt (typ.)  ADCIN Range 0 to 3-volt  Integral non-linearity typical 1 LSB, max. 2 LSB  Differential non-linearity typical 0.5 LSB, max. 1 LSB  Conversion Complete Flag or Conversion Complete Interrupt  Selectable ADC Clock ADC Port1 I/O Functions Port 1 pins are general I/O that are shared with the ADC channels. The channel select bit in ADCF register define which ADC channel/port1 pin will be used as ADCIN. The remaining ADC channels/port1 pins can be used as general purpose I/O or as the alter- nate function that is available. A conversion launched on a channel which are not selected on ADCF register will not have any effect. VAREF VAREF should be connected to a low impedance point and must remain in the range specified VAREF absolute maximum range (See section “AC-DC”). . If the ADC is not used, it is recommended to tie VAREF to VAGND.

128 AT/T89C51CC02

Table 102. Selected Analog input 3FFh if greater than VAREF and 000h if less than VAGND. Clock Selection The ADC clock is the same as CPU. caler is featured (ADCCLK) to generate the ADC clock from the oscillator frequency. Figure 54. A/D Converter Clock in ADCON register. In this mode the power dissipation is reduced.

000 A N 0

001 A N 1

010 A N 2

011 A N 3

100 A N 4

101 A N 5

110 A N 6

111 A N 7

EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software. Figure 55. ADC interrupt structure

1. Start a standard conversion
2. Start a precision conversion (need interrupt ADC)

130 AT/T89C51CC02

Table 104. ADCON Register Set to use P1.x as ADC input. Clear to use P1.x as standart I/O port. The value read from these bits are indeterminate. Do not set these bits.

6 PSIDLE

Clear to convert without idle mode. Must be cleared by software.

3 ADSST

Set to start an A/D conversion.

Table 105. ADCLK Register Table 106. ADDH Register Table 107. ADDL Register The value read from these bits are indeterminate. Do not set these bits. The value read from these bits are indeterminate. Do not set these bits.

132 AT/T89C51CC02

interrupt, a timer overrun interrupt and an ADC. These interrupts are shown below. Figure 56. Interrupt Control System

which must be cleared to disable all the interrupts at the same time. bit values and priority levels associated with each combination. Table 108. Priority Level bit Values determined by the polling sequence, See Table 109. Table 109. Interrupt Priority Within Level

134 AT/T89C51CC02

4126L–CAN–01/08 Registers Figure 57. IEN0 Register IEN0 (S:A8h) Interrupt Enable Register Reset Value = 0000 0000b bit addressable 76543210 EA EC ET2 ES ET1 EX1 ET0 EX0 Bit Number Bit Mnemonic Description 7E A Enable All Interrupt bit Clear to disable all interrupts. Set to enable all interrupts. If EA=1, each interrupt source is indivi dually enabled or disabled by setting or clearing its interrupt enable bit. 6E C PCA Interrupt Enable Clear to disable the PCA interrupt. Set to enable the PCA interrupt. 5E T 2 Timer 2 Overflow Interrupt Enable bit Clear to disable Timer 2 overflow interrupt. Set to enable Timer 2 overflow interrupt. 4E S Serial port Enable bit Clear to disable serial port interrupt. Set to enable serial port interrupt. 3E T 1 Timer 1 Overflow Interrupt Enable bit Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt. 2E X 1 External Interrupt 1 Enable bit Clear to disable external interrupt 1. Set to enable external interrupt 1. 1E T 0 Timer 0 Overflow Interrupt Enable bit Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. 0E X 0 External Interrupt 0 Enable bit Clear to disable external interrupt 0. Set to enable external interrupt 0.

Figure 58. IEN1 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. Clear to disable the timer overrun interrupt. Set to enable the timer overrun interrupt.

1 EADC

Clear to disable the ADC interrupt. Set to enable the ADC interrupt. Clear to disable the CAN interrupt. Set to enable the CAN interrupt.

136 AT/T89C51CC02

Table 110. IPL0 Register The value read from this bit is indeterminate. Do not set this bit.

6 PPC PCA Interrupt Priority bit

Refer to PT2H for priority level. Refer to PSH for priority level. Refer to PT1H for priority level. Refer to PX1H for priority level. Refer to PT0H for priority level. Refer to PX0H for priority level.

Table 111. IPL1 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. Refer to PI2CH for priority level. Refer to PSPIH for priority level. Refer to PKBH for priority level.

138 AT/T89C51CC02

Table 112. IPH0 Register The value read from this bit is indeterminate. Do not set this bit.

6 PPCH

4 PSH

Table 113. IPH1 Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.

1 PADCH

140 AT/T89C51CC02

4126L–CAN–01/08

Electrical Characteristics

TA = -40°C to +85°C; VSS = 0 V; VCC = 3 volts to 5.5 volts; F = 0 to 40 MHz Notes: 1. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature. 2. Flash retention is guaranteed with the same formula for V CC min down to 0V. 3. Under steady state (non-transient) conditions, I OL must be externally limited as follows: Maximum IOL per port pin: 10 mA Absolute Maximum Ratings Note: Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Power Dissipation value is based on the maximum allowable die temperature and the thermal resistance of the package. Table 114. DC Parameters in Standard Voltage

142 AT/T89C51CC02

Figure 61. ICC Test Condition, Power-down Mode Figure 62. Clock Signal Waveform for ICC Tests in Active and Idle Modes Table 115. DC Parameters for AD Converter in Precision Conversion Notes: 1. Typicals are based on a limited number of samples and are not guaranteed. All other pins are disconnected.

Table 116. Symbol Description (F = 40 MHz) Table 118. AC Parameters for a Variable Clock Table 117. AC Parameters for a Fix Clock (F = 40 MHz)

144 AT/T89C51CC02

Table 119. AC Parameters AC inputs during testing are driven at V CC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”.

Clock Waveforms Valid in normal clock mode. In X2 Mode XTAL2 must be changed to XTAL2/2. Table 120. Memory AC Timing Figure 63. Flash Memory - Internal Busy Waveforms

146 AT/T89C51CC02

4126L–CAN–01/08

Ordering Information

Factory default programming for T89C51CC02CA-xxxx is Bootloader CAN and HSB = BBh: X 1 m o d e  BLJB = 0 : jump to Bootloader  LB2 = 0 : Security Level 3. (1) Factory default programming for T89C51CC02UA-xxxx is Bootloader UART and HSB = BBh: X 1 m o d e  BLJB = 0 : jump to Bootloader  LB2 = 0 : Security Level 3. (1) Notes: 1. LB2 = 0 is not described in Table 22 Program load bit. LB2 = 0 is equivalent to LB1 = 0: Security Level 3. 2. Customer can change these modes by re-programming with a parallel programmer, this can be done by an Atmel distributor. Part Number Bootloader Temperature Range Package Packing Product Marking T89C51CC02CA-RATIM OBSOLETE T89C51CC02CA-SISIM T89C51CC02CA-TDSIM T89C51CC02CA-TISIM T89C51CC02UA-RATIM T89C51CC02UA-SISIM T89C51CC02UA-TDSIM T89C51CC02UA-TISIM AT89C51CC02CA-RATUM CAN (2) Industrial & Green VQFP32 Tray 89C51CC02CA-UM AT89C51CC02CA-SISUM CAN (2) Industrial & Green PLCC28 Stick 89C51CC02CA-UM AT89C51CC02CA-TDSUM CAN (2) Industrial & Green SOIC24 Stick 89C51CC02CA-UM AT89C51CC02CA-TISUM CAN (2) Industrial & Green SOIC28 Stick 89C51CC02CA-UM AT89C51CC02UA-RATUM UART (2) Industrial & Green VQFP32 Tray 89C51CC02UA-UM AT89C51CC02UA-SISUM UART (2) Industrial & Green PLCC28 Stick 89C51CC02UA-UM AT89C51CC02UA-TDSUM UART (2) Industrial & Green SOIC24 Stick 89C51CC02UA-UM AT89C51CC02UA-TISUM UART (2) Industrial & Green SOIC28 Stick 89C51CC02UA-UM

4126L–CAN–01/08 Package Drawings VQFP32

148 AT/T89C51CC02

4126L–CAN–01/08 STANDARD NOTES FOR PQFP/ VQFP / TQFP / DQFP 1/ CONTROLLING DIMENSIONS : INCHES 2/ ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y 14.5M - 1982. 3/ "D1 AND E1" DIMENSIONS DO NOT INCLUDE MOLD PROTUSIONS. MOLD PROTUSIONS SHALL NOT EXCEED 0.25 mm (0.010 INCH). THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM PACKAGE BODY SIZE BY AS MUCH AS 0.15 mm. 4/ DATUM PLANE "H" LOCATED AT MOLD PARTING LINE AND COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT BOTTOM OF PARTING LINE. 5/ DATUM "A" AND "D" TO BE DETERMINED AT DATUM PLANE H. 6/ DIMENSION " f " DOES NOT INCLUDE DAMBAR PROTUSION ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08mm/.003" TOTAL IN EXCESS OF THE " f " DIMENSION AT MAXIMUM MATERIAL CONDITION . DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.

4126L–CAN–01/08 PLCC28

150 AT/T89C51CC02

4126L–CAN–01/08 STANDARD NOTES FOR PLCC 1/ CONTROLLING DIMENSIONS : INCHES 2/ DIMENSIONING AND TOLERANCING PER ANSI Y 14.5M - 1982. 3/ "D" AND "E1" DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSION MOLD FLASH OR PROTUSIONS SHALL NOT EXCEED 0.20 mm (.008 INCH) PER SIDE.

4126L–CAN–01/08 SOIC24

152 AT/T89C51CC02

4126L–CAN–01/08 SOIC28

4126L–CAN–01/08

154 AT/T89C51CC02

4126L–CAN–01/08 Datasheet Revision History Changes from 4126C- 10/02 to 4126D - 04/03 1. Changed the endurance of Flash to 100, 000 Write/Erase cycles. 2. Added note on Flash retention formula for V IH1, in Section "DC Parameters for Standard Voltage", page 141.Changes from 4129F-11/02 to 4129G-04/03 1. Changed the endurance of Flash to 100, 000 Write/Erase cycles. 2. Added note on Flash retention formula for V IH1, in Section "DC Parameters for Standard Voltage", page 141. Changes from 4126D - 05/03 to 4126E - 10/03 1. Updated “Electrical Characteristics” on page 140. 2. Corrected Figure 39 on page 82. Changes from 4126E - 10/03 to 4126F - 12/03 1. Changed value of IPDMAX to 400, Section "Absolute Maximum Ratings", page 140. 2. PCA , CPS0, register correction, Section "PCA Registers", page 121. 3. Cross Memory section added. Section "Operation Cross Memory Access", page 44. Changes from 4126F - 12/03 4126G - 08/04 1. Figure clock-out mode modified see, Figure 30 on page 65. 2. Corrected error in Table 51 on page 70, (1.25ms to 1.25s) for Time-out Computation. 3. Added explanation on the CAN protocol, see Section “CAN Controller”, page 73. Changes from 4126G - 08/04 to 4126H - 01/05 1. Various minor corrections throughout the document. Changes from 4126H - 01/05 to 4126I 11/05 1. Added Green product ordering information. Changes from 4126I to 4126J 05/06 1. Minor corrections throughout the document. Changes from 4126J to 4126K 11/07 1. Updated Package drawings. Changes from 4126K 11/07 to 4126L 02/08 1. Removed non-green part numbers from ordering information.

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