89C1632 MAXWELL | Alldatasheet

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All data sheets are subject to change without notice (619) 503-3300 - Fax: (619) 503-3301 - www.maxwell.com

16 Megabit (512K x 32-Bit)

©2005 Maxwell Technologies. All rights reserved. MCM SRAM

01.10.05 Rev 3

FEATURES:

  • Four 512k x 8 SRAM architecture R AD-PAK® technology hardens against natural space radia- tion technology  Total dose hardness: - > 100 krad (Si), depending upon space mission  Excellent Single Event Effects: - SEL > 101MeV-cm2/mg - SEU threshold = 3 MeV-cm2/mg - SEU saturated cross section: 6E-9 cm2/bit  Package: 68-pin quad flat package  Fast access time: 20, 25 and 30 ns  Completely static memory - no clock or timing strobe required  Internal bypass capacitor  High-speed silicon-gate CMOS technology  5V or 3V ± 10% power supply  Equal address and chip enable access times  Three-state outputs  All inputs and outputs are TTL compatible DESCRIPTION: Maxwell Technologies’ 89C1632 high-performance 16 Mega- bit Multi-Chip Module (MCM) Static Random Access Memory features a greater than 100 krad (Si) total dose tolerance, depending upon space mission. The four 4-Megabit SRAM die and bypass capacitors are incorporated into a high-reliable hermetic quad flat-pack ceramic package. With high-perfor- mance silicon-gate CMOS technology, the 89C1632 reduces power consumption and eliminates the need for external clocks or timing strobes. It is equipped with output enable (OE ) and four byte enable (CS1 - CS4) inputs to allow greater system flexibility. When OE input is high, the output is forced to high impedance. Maxwell Technologies' patented RAD-PAK® packaging technol- ogy incorporates radiation shielding in the microcircuit pack- age. In a GEO orbit, R AD-PAK provides true greater than 100 krad (Si) total radiation dose tolerance, dependent upon space mission. It eliminates the need for box shielding while provid- ing the required radiation shielding for a lifetime in orbit or a space mission. This product is available with screening up to Maxwell Technologies self-defined Class K. CS 1-4 MCM OE, WE Address 4Mb SRAM 4Mb SRAM 4Mb SRAM 4Mb SRAMPower Ground I/O 0-7 I/O 8-15 I/O 16-23 I/O 24-31

16 Megabit (512k x 32-bit) SRAM MCM

16 Megabit (512K x 32-Bit) MCM SRAM 89C1632

TABLE 1. PINOUT DESCRIPTION

65 WE WriteEnable

66 OE Output Enable

TABLE 2. 89C1632 ABSOLUTE MAXIMUM RATINGS TABLE 3. 89C1632 RECOMMENDED OPERATING CONDITIONS

  1. V IH (max) = VCC + 2V ac (pulse width < 10ns) for I < 80 mA.

TABLE 4. 89C1632 DELTA LIMITS

TABLE 5. 89C1632 DC ELECTRICAL CHARACTERISTICS TABLE 6. 89C1632 AC OPERATING CONDITIONS AND CHARACTERISTICS TABLE 4. 89C1632 DELTA LIMITS

TABLE 7. 89C1632 READ CYCLE TABLE 6. 89C1632 AC OPERATING CONDITIONS AND CHARACTERISTICS

TABLE 8. 89C1632 FUNCTIONAL DESCRIPTION TABLE 9. 89C1632 WRITE CYCLE

TABLE 9. 89C1632 WRITE CYCLE

FIGURE 1. AC TEST LOADS FIGURE 2. TIMING WAVEFORM OF READ CYCLE (1) (ADDRESS CONTROLLED) FIGURE 3. TIMING WAVEFORM OF READ CYCLE (2) (WE = VIH)

  1. WE is high for read cycle.
  2. All read cycle timing is referenced from the last valid address to the first transition address.
  1. t HZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or
  2. At any given temperature and voltage conditions, t HZ (max) is less than tLZ (min) both for a given device and from device to
  3. Transition is measured + 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
  4. Device is continuously selected with CS = VIL.
  5. Address valid prior to coincident with CS transition low.
  6. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write

FIGURE 4. TIMING WAVEFORM OF WRITE CYCLE (1) (OE CLOCK) FIGURE 5. TIMING WAVEFORM OF WRITE CYCLE (2) (OE LOW FIIXED)

FIGURE 6. TIMING WAVEFORM OF WRITE CYCLE (3) (CS CONTROLLED)

  1. All write cycle timing is referenced from the last valid address to the first transition address.
  2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low.
  3. t CW is measured from the later of CS going low to end of write.
  4. t AS is measured from the address valid to the beginning of write.
  5. t WR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
  6. If OE , CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase

of the output must not be applied because bus contention can occur.

  1. For common I/O applications, minimization of elimination of bus contention conditions is necessary during read and write
  2. If CS foes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
  3. D OUT is the read data of the new address.

FIGURE 7. SRAM HEAVY ION CROSS SECTION FIGURE 8. SRAM PROTON SEU CROSS SECTION STATIC

11All data sheets are subject to change without notice ©2005 Maxwell Technologies. All rights reserved. Note: All dimensions in inches

68 PIN RAD-PAK® QUAD FLAT PACKAGE

A 0.206 0.225 0.244 b 0.015 0.017 0.018 c 0.008 0.009 0.12 D 1.479 1.494 1.509 D1 0.800 e 0.050 BSC S1 -- 0.339 -- F1 1.239 1.244 1.249 F2 1.429 1.434 1.439 L 2.485 2.510 2.545 L1 2.485 2.500 2.505 L2 1.690 1.700 1.710 A1 0.180 0.195 0.210 N6 8

12All data sheets are subject to change without notice ©2005 Maxwell Technologies. All rights reserved. Important Notice: These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech- nologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.

13All data sheets are subject to change without notice ©2005 Maxwell Technologies. All rights reserved. 1) Products are manufactured and screened to Maxwell Technologies self-defined Class H and Class K. Model Number Feature Option Details89C1632 RP Q X -XX Access Time Screening Flow Package Radiation Feature Base Product Nomenclature 20 = 20 ns 25 = 25 ns 30 = 30 ns Multi Chip Module (MCM) K = Maxwell Self-Defined Class K H = Maxwell Self-Defined Class H I = Industrial (testing E = Engineering (testing @ +25°C) Q = Quad Flat Pack RP = R AD-PAK® package

16 Megabit (512K x 32-Bit) MCM