Microcontroller

895132-IL

ATMEL Corporation

USB Microcontroller with 64K Bytes Flash Memory

Manufacturer: ATMEL Corporation

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Technical content

Features

Programmable Audio Output for Interfacing with Common Audio DAC – PCM Format Compatible – I 2S Format Compatible
8-bit MCU C51 Core-based (F MAX = 20 MHz)
2304 Bytes of Internal RAM
64K Bytes of Code Memory – AT89C5132: Flash (100K Write/Erase Cycles)
4K Bytes of Boot Flash Memory (AT89C5132) – ISP: Download from USB (standard) or UART (option)
USB Rev 1.1 Device Controller – “Full Speed” Data Transmission
Built-in PLL
MultiMedia Card ® Interface Compatibility
Atmel DataFlash ® SPI Interface Compatibility
IDE/ATAPI Interface
2 Channels 10-bit ADC, 8 kHz (8 True Bits) – Battery Voltage Monitoring – Voice Recording Controlled by Software
Up to 44 Bits of General-purpose I/Os – 4-bit Interrupt Keyboard Port for a 4 x n Matrix – SmartMedia ® Software Interface
Two Standard 16-bit Timers/Counters
Hardware Watchdog Timer
Standard Full Duplex UART with Baud Rate Generator
Two Wire Master and Slave Modes Controller
SPI Master and Slave Modes Controller
Power Management – Power-on Reset – Software Programmable MCU Clock – Idle Mode, Power-down Mode
Operating Conditions – 3V, ±10%, 25 mA Typical Operating at 25° C – Temperature Range: -40 °C to +85 °C
Packages – TQFP80, PLCC84 (Development Board Only) – Dice 1. Description The AT89C5132 is a mass storage device controlling data exchange between various Flash modules, HDD and CD-ROM. The AT89C5132 includes 64K Bytes of Flash memory and allows In-System Program- ming through an embedded 4K Bytes of Boot Flash Memory. The AT89C5132 include 2304 Bytes of RAM memory. The AT89C5132 provides all the necessary features f or man-machine interface including, timers, keyboard port, serial or paralle l interface (USB, SPI, IDE), ADC input, I 2S output, and all external memory interface (NAND o r NOR Flash, SmartMe- dia, MultiMedia, DataFlash cards). 2. Typical Applications
Flash Recorder/Writer
PDA, Camera, Mobile Phone
PC Add-on USB Microcontroller with 64K Bytes Flash Memory AT89C5132 4173E–USB–09/07

4173E–USB–09/07 AT89C5132 3. Block Diagram Figure 3-1. AT89C5132 Block Diagram Notes: 1. Alternate function of Port 3 2. Alternate function of Port 4 3. Alternate function of Port 1 8-BIT INTERNAL BUS Clock and PLL Unit C51 (X2 CORE) RAM

2304 Bytes

KIN3:0 I2S/PCM Audio Interface AVSS AVDD AIN1:0 Ports INT0 INT1 MOSI MISO Timers 0/1 T1 T0 SPI/DataFlash Controller MCLK MCMD SCK RST AREF DSEL DCLK SCLK DOUT 64K Bytes USB Controller D+ D- UART RXD TXD IDE Interface SS Watchdog Flash Boot 4K Bytes UVSS UVDD and BRG 1 1 1 1 1 1 2 2 2 2 TWI Controller SCL SDA 1 1

4173E–USB–09/07 AT89C5132 4. Pin Description Figure 4-1. AT89C5132 80-pin TQFP Package P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS VDD P0.6/AD6 P0.7/AD7 P2.0/A8 P2.1/A9 P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.0/RXD P2.2/A10 P2.3/A11 P2.4/A12 P2.6/A14 P2.5/A13 P2.7/A15 MCLK MDAT MCMD P0.2/AD2 P0.1/AD1 P0.0/AD0 PVSS VSS TST VSS P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO VSS VDD RST SCLK DSEL DCLK DOUT AIN1 AIN0 AREFN AREFP AVSS AVDD P3.7/RD P3.6/WR P3.5/T1 VDD P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P1.4 P1.5 P1.7/SDA FILT PVDD VDD P1.6/SCL ALE ISP UVDD UVSS P5.0 P5.1 P4.7 P4.6 P5.3 P5.2 VSS VDD P4.5 P4.4 TQFP80

Note: 1. For development board only.

4.1 Signals

All the AT89C5132 signals are detailed by functionality in Table 1 to Table 14. Table 1. Ports Signal Description current consumption, floating P0 inputs must be pol arized to V DD or V SS . P1 is an 8-bit bidirectional I/O port with internal pull-ups.

Table 2. Clock Signal Description Table 3. Timer 0 and Timer 1 Signal Description P3 is an 8-bit bidirectional I/O port with internal pull-ups. P4 is an 8-bit bidirectional I/O port with internal pull-ups. To use the internal oscillator, a crystal/resonator circuit is connected to this pin. clock source for internal timing. To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave X2 unconne cted.

Table 4. Audio Interface Signal Description Table 5. USB Controller Signal Description Table 6. MutiMediaCard Interface Signal Description and the channel selection signal (DSEL). must be polarized to V DD or V SS . MDAT input must be polarized to V DD or V SS .

Table 7. UART Signal Description Table 8. SPI Controller Signal Description Table 9. TWI Controller Signal Description Table 10. A/D Converter Signal Description slave mode, MISO outputs data to the master control ler. slave mode, MOSI receives data from the master cont roller. slave mode, SCK receives clock from the master cont roller.

Table 11. Keypad Interface Signal Description Table 12. External Access Signal Description Table 13. System Signal Description Upper address lines for the external bus. Multiplexed higher address and data lines for the I DE interface. the address from address/data bus. reset to force execution of the internal bootloader . voltage lower than V IL is applied, whether or not the oscillator is runni ng. by connecting a capacitor between this pin and V DD .

Table 14. Power Signal Description

4.2 Internal Pin Structure

Table 15. Detailed Internal Pin Structure Section “DC Characteristics”, page 183.

When the Two Wire controller is enabled, P 1, P 2, and P 3 transistors are disabled allowing

pseudo open-drain structure.

In Port 2, P 1 transistor is continuously driven when outputting a high level bit address (A15:8).

4173E–USB–09/07 AT89C5132 5. Address Spaces The AT8xC5132 derivatives implement four different address spaces:

Program/Code Memory
Boot Memory
Data Memory
Special Function Registers (SFRs)

5.0.1 Code Memory

The AT89C5132 implements 64K Bytes of on-chip program/code memory in Flash technology. The Flash memory increases ROM functionality by enabling in-circuit electrical erasure and pro- gramming. Thanks to the internal charge pump, the h igh voltage needed for programming or erasing Flash cells is generated on-chip using the standard V DD voltage. Thus, the AT89C5132 can be programmed using only one voltage and allows in application software programming commonly known as IAP. Hardware programming mode is also available using specific pro- gramming tools.

5.0.2 Boot Memory

The AT89C5132 implements 4K Bytes of on-chip boot m emory provided in Flash technology. This boot memory is delivered programmed with a standard bootloader software allowing in sys- tem programming commonly known as ISP. It also cont ains some Application Programming Interfaces routines commonly known as API allowing user to develop his own bootloader.

5.0.3 Data Memory

The AT89C5132 derivatives implement 2304 bytes of on-chip data RAM. This memory is divided in two separate areas:

256 bytes of on-chip RAM memory (standard C51 memo ry).
2048 bytes of on-chip expanded RAM memory (ERAM ac cessible via MOVX instructions).

4173E–USB–09/07 AT89C5132 6. Clock Controller The AT89C5132 clock controller is based on an on-ch ip oscillator feeding an on-chip Phase Lock Loop (PLL). All internal clocks to the periphe rals and CPU core are generated by this controller.

6.1 Oscillator

The AT89C5132 X1 and X2 pins are the input and the output of a single-stage on-chip inverter (see Figure 6-1) that can be configured with off-ch ip components such as a Pierce oscillator (see Figure 6-2). Value of capacitors and crystal c haracteristics are detailed in the Section “DC Characteristics”. The oscillator outputs three different clocks: a clock for the PLL, a clock for the CPU core, and a clock for the peripherals as shown in Figure 6-1. T hese clocks are either enabled or disabled, depending on the power reduction mode as detailed i n the section “Power Management” on page 44 . The peripheral clock is used to generate the Time r 0, Timer 1, MMC, ADC, SPI, and Port sampling clocks. Figure 6-1. Oscillator Block Diagram and Symbol Figure 6-2. Crystal Connection

6.2 X2 Feature

Unlike standard C51 products that require 12 oscill ator clock periods per machine cycle, the AT89C5132 needs only 6 oscillator clock periods per machine cycle. This feature called the “X2 feature” can be enabled using the X2 bit (1) in CKCON (see Table 1) and allows the AT89C5132 to operate in 6 or 12 oscillator clock periods per machine cycle. As shown in Figure 6-1, both CPU and peripheral clocks are affected by this feature. Figure 6-3 shows the X2 mode switching waveforms. After reset, the standard mode is activa ted. In standard mode, the CPU and periph- PD PCON.1 IDL PCON.0 Peripheral CPU Core CKCON.0 ÷ 2 PER CLOCK Clock Clock Peripheral Clock Symbol CPU CLOCK CPU Core Clock Symbol OSC CLOCK Oscillator Clock Symbol Oscillator Clock VSS Q

4173E–USB–09/07 AT89C5132 eral clock frequency is the oscillator frequency di vided by 2 while in X2 mode, it is the oscillator frequency. Note: 1. The X2 bit reset value depends on the X2B bi t in the Hardware Security Byte (see Table 12 on page 24). Using the AT89C5132 (Flash Version) the system can boot either in standard or X2 mode depending on the X2B value. Using AT83C51SND1C (ROM Version) the system always boots in standard mode. X2B bit can be changed to X2 mode later by software. Figure 6-3. Mode Switching Waveforms Note: In order to prevent any incorrect operation wh ile operating in X2 mode, the user must be aware that all peripherals using clock frequency as time reference (timers…) will have their time refer- ence divided by two. For example, a free running ti mer generating an interrupt every 20 ms will then generate an interrupt every 10 ms.

6.3 PLL

6.3.1 PLL Description

The AT89C5132 PLL is used to generate internal high frequency clock (the PLL Clock) synchro- nized with an external low-frequency (the Oscillato r Clock). The PLL clock provides the audio interface, and the USB interface clocks. Figure 6-4 shows the internal structure of the PLL. The PFLD block is the Phase Frequency Comparator an d Lock Detector. This block makes the comparison between the reference clock coming from the N divider and the reverse clock com- ing from the R divider and generates some pulses on the Up or Down signal depending on the edge position of the reverse clock. The PLLEN bit i n PLLCON register is used to enable the clock generation. When the PLL is locked, the bit P LOCK in PLLCON register (see Table 3) is set. The CHP block is the Charge Pump that generates the voltage reference for the VCO by inject- ing or extracting charges from the external filter connected on PFILT pin (see Figure 6-5). Value of the filter components are detailed in the Section “DC Characteristics”. The VCO block is the Voltage Controlled Oscillator controlled by the voltage V ref produced by the charge pump. It generates a square wave signal: the PLL clock. X1 ÷ 2 Clock X2 Bi t X2 Mode (1) STD Mode STD Mode

6.3.2 PLL Programming

PLL clock frequency will depend on the audio interface clock frequencies.

6.4 Registers

Table 1. CKCON Register

Table 2. PLLNDIV Register

7 TWIX2

Set to select the oscillator clock divided by 2 as TWI clock input (X2 independent). Clear to select the peripheral clock as TWI clock i nput (X2 dependent).

6 WDX2

Set to select the oscillator clock divided by 2 as watchdog clock input (X2 independent). Clear to select the peripheral clock as watchdog cl ock input (X2 dependent). The value read from this bit is indeterminate. Do n ot set this bit.

4 SIX2

Set to select the oscillator clock divided by 2 as UART clock input (X2 independent). Clear to select the peripheral clock as UART clock input (X2 dependent).. The value read from this bit is indeterminate. Do n ot set this bit.

2 T1X2

Set to select the oscillator clock divided by two a s Timer 1 clock input (X2 independent). Clear to select the peripheral clock as Timer 1 clo ck input (X2 dependent).

1 T0X2

Set to select the oscillator clock divided by two a s timer 0 clock input (X2 independent). Clear to select the peripheral clock as timer 0 clo ck input (X2 dependent). Clear to select 12 clock periods per machine cycle (STD mode, F CPU = F PER = F OSC /2). Set to select 6 clock periods per machine cycle (X2 mode, F CPU = F PER = F OSC ). The value read from this bit is always 0. Do not se t this bit.

Table 3. PLLCON Register Table 4. PLLRDIV Register 2 LSB of the 10-bit R divider. The values read from these Bits are always 0. Do no t set these Bits.

3 PLLRES

Set this bit to reset the PLL. Clear this bit to free the PLL and allow enabling. The values read from this bit is always 0. Do not s et this bit.

1 PLLEN

0 PLOCK

Set by hardware when PLL is locked. Clear by hardware when PLL is unlocked. 8 MSB of the 10-bit R divider.

4173E–USB–09/07 AT89C5132 7. Program/Code Memory The AT89C5132 implements 64K Bytes of on-chip program/code memory. Figure 7-1 shows the split of internal and external program/code memory spaces depending on the product. The Flash memory increases EPROM and ROM functional ity by in-circuit electrical erasure and programming. The high voltage needed for programmin g or erasing Flash cells is generated on- chip using the standard V DD voltage, made possible by the internal charge pump . Thus, the AT89C5132 can be programmed using only one voltage and allows in application software pro- gramming. Hardware programming mode is also availab le using common programming tools. See the application note ‘Programming T89C51x and AT89C51x with Device Programmers’. The AT89C5132 implements an additional 4K Bytes of on-chip boot Flash memory provided in Flash memory. This boot memory is delivered program med with a standard bootloader software allowing In-System Programming (ISP). It also conta ins some Application Programming Inter- faces (API), allowing In Application Programming (IAP) by using user’s own bootloader. Figure 7-1. Program/Code Memory Organization

7.1 Flash Memory Architecture

As shown in Figure 7-2 the AT89C5132 Flash memory i s composed of four spaces detailed in the following paragraphs. Figure 7-2. AT89C5132 Memory Architecture 4K Bytes Boot Flash FFFFh F000h 0000h 64K Bytes Code Flash FFFFh F000h FFFFh 64K Bytes Flash Memory 0000h Hardware Security User 4K Bytes Flash Memory FFFFh F000h Boot Extra Row

7.1.1 User Space

7.1.2 Boot Space

Programming and the routines for In-System Application Programming. This space can only be read or written by hardware mode using a parallel programming tool.

7.1.3 Hardware Security Space

detailed in section “Hardware Security System” and can only be written by hardware.

7.1.4 Extra Row Space

The Software Boot Vector (SBV see Table 8). This byte is used by the software bootloader to build the boot address.
The Software Security Byte (SSB see Figure ). This byte is used to lock the execution of some bootloader commands.

7.2 Hardware Security System

always set in read disabled mode.

Level 0 is the level of an erased part and does no t enable any security feature.
Level 1 locks the hardware programming of both use r and boot memories.
Level 2 locks hardware verifying of both user and boot memories.
Level 3 locks the external execution. Notes: 1. U means unprogrammed, P means programmed an d X means don’t care (programmed or unprogrammed). 2. LB2 is not implemented in the AT89C5132 products. 3. AT89C5132 products are delivered with third level programmed to ensure that the code pro- grammed by software using ISP or user’s bootloader is secured from any hardware piracy.

Table 5. Lock Bit Features (1)

0 U U U Enable Enable Enable Enable Enable

1 U U P Enable Enable Enable Disable Enable

2 U P X Enable Enable Disable Disable Enable

4173E–USB–09/07 AT89C5132

7.3 Boot Memory Execution

As internal C51 code space is limited to 64K Bytes, some mechanisms are implemented to allow boot memory to be mapped in the code space for execution at addresses from F000h to FFFFh. The boot memory is enabled by setting the ENBOOT bi t in AUXR1 (see Table 6 ). The three ways to set this bit are detailed in the following sections.

7.3.1 Software Boot Mapping

The software way to set ENBOOT consists in writing to AUXR1 from the user’s software. This enables bootloader or API routines execution.

7.3.2 Hardware Condition Boot Mapping

The hardware condition is based on the ISP pin. When driving this pin to low level, the chip reset sets ENBOOT and forces the reset vector to F000h in stead of 0000h in order to execute the bootloader software. As shown in Figure 7-3, the hardware condition alwa ys allows in-system recovery when user’s memory has been corrupted.

7.3.3 Programmed Condition Boot Mapping

The programmed condition is based on the Bootloader Jump Bit (BLJB) in HSB. As shown in Figure 7-3, when this bit is programmed (by hardwar e or software programming mode), the chip resets ENBOOT and forces the reset vector to F000h instead of 0000h, in order to execute the bootloader software. Figure 7-3. Hardware Boot Process Algorithm The software process (bootloader) is detailed in the AT89C5132 Bootloader datasheet. Atmel’s Boot Loader HardwareSoftware Hard Cond? ISP = L? RESET Hard Cond Init ENBOOT = 1 PC = F000h FCON = 00h Prog Cond? BLJB = P? Standard Init ENBOOT = 0 PC = 0000h FCON = F0h Prog Cond Init ENBOOT = 1 PC = F000h FCON = F0h User’s Application Process Process

7.3.4 Preventing Flash Corruption

See “Reset Recommendation to Prevent Flash Corruption” on page 45 .

7.4 Registers

Table 6. AUXR1 Register

7.5 Hardware Bytes

Table 7. HSB Byte – Hardware Security Byte The values read from these Bits are indeterminate. Do not set these Bits.

5 ENBOOT

Clear this bit to disable boot Flash. The values read from this bit is indeterminate. Do not set this bit.

3 GF3 General Flag

This bit is a general-purpose user flag. This bit is stuck to logic 0 to allow INC AUXR1 ins truction without affecting GF3 flag. 1 - Reserved for Data Pointer Extension.

0 DPS

Set to select second data pointer: DPTR1. Clear to select first data pointer: DPTR0.

7 X2B (1)

Program this bit to start in X2 mode. Unprogram (erase) this bit to start in standard mod e.

6 BLJB (2)

Program this bit to execute the boot loader at addr ess F000h on next reset. Unprogram (erase) this bit to execute user’s applic ation at address 0000h on next reset. The value read from these bits is always unprogramm ed. Do not program these bits. The value read from this bit is always unprogrammed . Do not program this bit.

Reset Value = XXUU UXXX, UUUU UUUU after an hardwar e full chip erase. Note: 1. X2B initializes the X2 bit in CKCON during t he reset phase.

In order to ensure boot loader activation at firs t power-up, AT89C5132 products are delivered
Bits 0 to 3 (LSN) can only be programmed by hardw are mode.

Table 8. SBV Byte – Software Boot Vector Reset Value = XXXX XXXX, UUUU UUUU after an hardware full chip erase. Table 9. SSB Byte – Software Security Byte Reset Value = XXXX XXXX, UUUU UUUU after an hardware full chip erase. Refer to for bits description. Refer to the bootloader datasheet for usage informa tion (bootloader dependent). Refer to the bootloader datasheet for usage informa tion (bootloader dependent).

The internal space mapped in three separate segme nts:

refer to the section “Special Function Registers”, page 29. Figure 8-1 shows the internal and external data mem ory spaces organization.

8.1 Internal Space

8.1.1 Lower 128 Bytes RAM

Table 10. Register Bank Selection

128 Bytes

8.1.2 Upper 128 Bytes RAM

8.1.3 Expanded RAM

See “External Space” on page 23. Table 11. ERAM Size Selection

8.2 External Space

8.2.1 Memory Interface

control signals (RD , WR , and ALE).

4 Banks of

8 Registers

nal memory interface signals. Table 12. External Data Memory Interface Signals

8.2.2 Page Access Mode

while keeping P2 for general I/O usage.

8.2.3 External Bus Cycles

write data (see Figure 8-5) in the external data memory.

4173E–USB–09/07 AT89C5132

8.3 Dual Data Pointer

8.3.1 Description

The AT89C5132 implement a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR0 and DPTR1 are seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Table 15) is used to select whether DPTR is the dat a pointer 0 or the data pointer 1 (see Figure 8-6). Figure 8-6. Dual Data Pointer Implementation

8.3.2 Application

Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, com pare, search …) are well served by using one data pointer as a “source” pointer and the othe r one as a “destination” pointer. Below is an example of block move implementation us ing the two pointers and coded in assem- bler. The latest C compiler also takes advantage of this feature by providing enhanced algorithm libraries. The INC instruction is a short (2 Bytes) and fast (6 CPU clocks) way to manipulate the DPS bit in the AUXR1 register. However, note that the INC inst ruction does not directly forces the DPS bit to a particular state, but simply toggles it. In si mple routines, such as the block move example, only the fact that DPS is toggled in the proper seq uence matters, not its actual value. In other words, the block move routine works the same whether DPS is “0” or “1” on entry. ; ASCII block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; Ends when encountering NULL character ; Note: DPS exits opposite of entry state unless an extra INC AUXR1 is added AUXR1 EQU 0A2h move: mov DPTR,#SOURCE ; address of SOURCE inc AUXR1 ; switch data pointers mov DPTR,#DEST ; address of DEST mv_loop: inc AUXR1 ; switch data pointers movx A,@DPTR ; get a byte from SOURCE inc DPTR ; increment SOURCE address inc AUXR1 ; switch data pointers movx @DPTR,A ; write the byte to DEST inc DPTR ; increment DEST address jnz mv_loop ; check for NULL terminator end_move: DPH0 DPH1 DPL0 DPS AUXR1.0 DPH DPL DPL1 DPTR DPTR0 DPTR1

8.4 Registers

Table 13. PSW Register Table 14. AUXR Register

7 CY Carry Flag

Carry out from bit 1 of ALU operands.

6 AC Auxiliary Carry Flag

Carry out from bit 1 of addition operands. Refer to Table 10 for Bits description.

2 OV Overflow Flag

Overflow set by arithmetic operations.

1 F1 User Definable Flag 1

Set when ACC contains an odd number of 1’s. Cleared when ACC contains an even number of 1’s. The values read from this bit is indeterminate. Do not set this bit.

6 EXT16

Set to enable 16-bit access mode during MOVX instru ctions. Set to stretch RD or WR signals duration to 15 CPU clock periods. Clear not to stretch RD or WR signals and set duration to 3 CPU clock periods.

4 DPHDIS

Set to disable DPH output on P2 when executing MOVX @DPTR instruction. Clear to enable DPH output on P2 when executing MOV X @DPTR instruction. Refer to Table 11 for ERAM size description.

4173E–USB–09/07 AT89C5132 Reset Value = X000 1101b

1 EXTRAM

Set to select the external XRAM when executing MOVX @Ri or MOVX @DPTR instructions. Clear to select the internal expanded RAM when exec uting MOVX @Ri or MOVX @DPTR instructions. 0 AO ALE Output Enable Bit Set to output the ALE signal only during MOVX instr uctions. Clear to output the ALE signal at a constant rate o f F CPU /3. Bit Number Bit Mnemonic Description

Special Function Registers

Table 15. C51 Core SFRs Table 16. System Management SFRs Table 17. PLL and System Clock SFRs Table 18. Interrupt SFRs

Table 19. Port SFRs Table 20. Flash Memory SFR Table 21. Timer SFRs Table 22. Audio Interface SFRs

Table 23. USB Controller SFRs Table 24. MMC Controller SFRs Table 25. IDE Interface SFR

Table 26. Serial I/O Port SFRs Table 27. SPI Controller SFRs Table 28. Special Register Table 29. Keyboard Interface SFRs Table 30. A/D Controller SFRs

Notes: 1. SFR registers with least significant nibble address equal to 0 or 8 are bit-addressable.

NVERS reset value depends on the silicon version: 1000 0011 for AT89C5132 product
FCON register is only available in AT89C5132 prod uct.
FCON reset value is 00h in case of reset with har dware condition.
CKCON reset value depends on the X2B bit (program med or unprogrammed) in the Hardware Byte.

Table 31. SFR Addresses and Reset Values

sources are enabled or disabled by the system designer and may be manipulated dynamically.

An internal or external device initiates an inter rupt-request signal. The AT89C5132, latch

this event into a flag buffer.

The priority of the flag is compared to the prior ity of other interrupts by the interrupt han-

dler. A high priority causes the handler to set an interrupt flag.

This signals the instruction execution unit to ex ecute a context switch. This context

with the start address of a software service routine.

The software service routine executes assigned ta sks and as a final activity performs a

operation then continues from the original point of interruption. Table 32. Interrupt System Signals enable separately the interrupt sources: IEN0 and IEN1 registers (see Table 35 and Table 36). IPL1 registers (see Table 10-1 to Table 39).

10.1 Interrupt System Priorities

interrupt source four possible priority levels according to Table 33.

Table 33. Priority Levels Table 34. Priority Within Same Level

4173E–USB–09/07 AT89C5132 Figure 10-1. Interrupt Control System EI2C IEN1.1 EMMC IEN1.0 EUSB IEN1.6 ESPI IEN1.2 EX0 IEN0.0 External Interrupt 0 INT0 EA IEN0.7 EX1 IEN0.2 External Interrupt 1 INT1 ET0 IEN0.1 Timer 0 ET1 IEN0.3 Timer 1 EAUD IEN0.6 Audio Interface EADC IEN1.3 A to D Converter SPI Controller USB Controller EKB IEN1.4 Keyboard MMC Controller Two-wire Controller IPH/L Interrupt Enable Lowest Priority Interrupts Highest KIN3:0 Priority Enable SCK SI SO SCL SDA Priority Interrupts ES IEN0.4 Serial Port TXD RXD MCLK MDAT MCMD AIN1:0

4173E–USB–09/07 AT89C5132

10.2 External Interrupts

10.2.1 INT1:0 Inputs

External interrupts INT0 and INT1 (INTn , n = 0 or 1) pins may each be programmed to be lev el- triggered or edge-triggered, dependent upon bits IT 0 and IT1 (ITn, n = 0 or 1) in TCON register as shown in Figure 10-2. If ITn = 0, INTn is triggered by a low level at the pin. If ITn = 1 , INTn is negative-edge triggered. External interrupts are enabled with bits EX0 and EX1 (EXn, n = 0 or 1) in IEN0. Events on INTn set the interrupt request flag IEn in TCON registe r. If the interrupt is edge-triggered, the request flag is cleared by hard ware when vectoring to the interrupt service routine. If the interrupt is level-triggered, the i nterrupt service routine must clear the request fla g and the interrupt must be deasserted before the end of the interrupt service routine. INT0 and INT1 inputs provide both the capability to exit from Power-down mode on low level sig- nals as detailed in Section “Exiting Power-down Mod e”, page 47. Figure 10-2. INT1:0 Input Circuitry

10.2.2 KIN3:0 Inputs

External interrupts KIN0 to KIN3 provide the capabi lity to connect a matrix keyboard. For detailed information on these inputs, refer to Section “Keyboard Interface”, page 152.

10.2.3 Input Sampling

External interrupt pins (INT1:0 and KIN3:0) are sampled once per peripheral cycle (6 peripheral clock periods) (see Figure 10-3). A level-triggered interrupt pin held low or high for more than 6 peripheral clock periods (12 oscillator in standard mode or 6 oscillator clock periods in X2 mode) guarantees detection. Edge-triggered external inter rupts must hold the request pin low for at least 6 peripheral clock periods. Figure 10-3. Minimum Pulse Timings INT0/1 IT0/1 TCON.0/2 EX0/1 IEN0.0/2 INT0/1 Interrupt Request IE0/1 TCON.1/3 Edge-Triggered Interrupt Level-Triggered Interrupt 1 cycle 1 cycle > 1 peripheral cycle 1 cycle > 1 peripheral cycle

10.3 Registers

Table 35. IEN0 Register Table 36. IEN1 Register Set to enable all interrupts. Clear to disable all interrupts.

6 EAUD

Set to enable audio interface interrupt. Clear to disable audio interface interrupt. The values read from this bit is always 0. Do not s et this bit. Set to enable serial port interrupt. Clear to disable serial port interrupt.

3 ET1

Set to enable Timer 1 overflow interrupt. Clear to disable Timer 1 overflow interrupt.

2 EX1

Set to enable external interrupt 1. Clear to disable external interrupt 1.

1 ET0

Set to enable timer 0 overflow interrupt. Clear to disable timer 0 overflow interrupt.

0 EX0

Set to enable external interrupt 0. Clear to disable external interrupt 0.

4173E–USB–09/07 AT89C5132 Reset Value = 0000 0000b Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is always 0. Do not se t this bit.

6 EUSB

USB Interface Interrupt Enable Bit Set this bit to enable USB interrupts. Clear this bit to disable USB interrupts. 5 - Reserved The value read from this bit is always 0. Do not se t this bit.

4 EKB

Keyboard Interface Interrupt Enable Bit Set to enable Keyboard interrupt. Clear to disable Keyboard interrupt.

3 EADC

A to D Converter Interrupt Enable Bit Set to enable ADC interrupt. Clear to disable ADC interrupt.

2 ESPI

SPI Controller Interrupt Enable Bit Set to enable SPI interrupt. Clear to disable SPI interrupt.

1 EI2C

Two Wire Controller Interrupt Enable Bit Set to enable Two Wire interrupt. Clear to disable Two Wire interrupt.

0 EMMC

MMC Interface Interrupt Enable Bit Set to enable MMC interrupt. Clear to disable MMC interrupt.

4173E–USB–09/07 AT89C5132 Table 10-1. IPH0 Register IPH0 (S:B7h) – Interrupt Priority High Register 0 Reset Value = X000 0000b 7 6 5 4 3 2 1 0 - IPHAUD – IPHS IPHT1 IPHX1 IPHT0 IPHX0 Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do n ot set this bit.