87CS71F

TMP87CS71F TOSHIBA | Alldatasheet

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TOSHIBA TMP87CM71/N71/P71/S71 CMOS 8-BIT MICROCONTROLLER TMP87CM71F, TMP87CN71F, TMP87CP71F, TMP87CS71F The 87CM71/N71/P71/S71 are the high speed and high performance 8-bit single chip microcomputers. These MCU contain 6-bit A/D conversion inputs and a VFT (Vacuum Fluorescent Tube) driver on a chip. -TMPRICMZIF | _32Kx8-bit | --TMPB7CN71F__|_40KxB-bit | 1.5KxBbIt | Oepg0 p 1420-0808 TMPOTPRTIF _-Tpa7ce7if | _48kx8-bit To |_LIMPRPPSTIF impavcs7iF | 61184xe-bit

FEATURES

@8-bit single chip microcomputer TLCS-870 Series @ instruction execution time : 0.5s (at 8MHz), 122s (at 32.768 kHz) _ | 2°P8-P:1420-0.808 412 basic instructions © Multiplication and Division (8 bits x 8 bits , 16 bits + 8 bits) © Bit manipulations (Set/Clear/Complement/Move/Test/Exclusive or, © 16-bit data operations LN. © 1-byte jump/subroutine-call (Short relative jump/ Vector call) aN $14 interrupt sources (External: 5, Internal: 9) — et © Allsources have independent latches each, &: << and nested interrupt control is available. * ee @ 3 edge-selectable external interrupts with noise reject @ High-speed task switching by register bank changeover TMP87CM71F #10 Input/Output ports (73 pins) TMP87CN71F @ Output: 1 port (8 pins) TMP87CP71F @ Input/Output: 9 ports (65 pins) ‘TMP87CS71F @Two 16-bit Timer/Counters Meares @ Timer, Eventcounter modes Two 8-bit Timer/Counters @ Timer, Event counter, Capture (Pulse width/duty measurement), PWM output, Programmable divider output modes @Time Base Timer (Interrupt frequency: — 1Hzto 16 kHz) @ Divider output function (frequency: 1kHz to 8 kHz) @Watchdog Timer @ Interrupt source/reset output (programmable) 8-bit Serial Interface © With 8 bytes transmit/receive data buffer @ Internal/external serial clock, and 4/8-bit mode @8-bit High Speed Serial Output (rate : max. 1 bit / 1s) @6-bit A/D conversion input (6 channels) @Vacuum Fluorescent Tube Driver (automatic display) @ High breakdown voltage ports @Key scanning function © Key-matrix constructed by segment outputs (1 to 16) and key inputs (1 to 8) @Dual clock operation @ Single/Dual-clock mode (option) @Five Power saving operating modes @ STOP mode : Oscillation stops. Battery/Capacitor back-up. Port output hold/High-impedance. @ SLOW mode: Low power consumption operation using low-frequency clock (32.768 kHz). @ IDLE1 mode : CPU stops, and Peripherals operate using high-frequency clock. Release by interrupts. @ IDLE2 mode: CPU stops, and Peripherals operate using high-and low-frequency clock. Release by interrupts. © SLEEP mode: CPU stops, and Peripherals operate using low-frequency clock. Release by interrupts. (87CM71/N71/P71) @Emulation Pod : BM87CK70FOB 3-71-1

TOSHIBA TMP87CM71/N71/P71/S71 PIN ASSIGNMENTS ‘TOP VIEW) f882Secceneggacessageggee Hooaesessssossssesssssss BESRSSSSSBSIISSRLLELSELS QFP80-P-1420-0.80B PRPRSSRSSSSSSSSERELLERS yesvesvecverie) ' HHAHAHHAB HAA EAHA ROH AEE gorormcarfy SSSSSERERRS RAREST Ee SESS cy VKK = CoOo66 3D <P 65 (G10) (KEYO) P40—<@C—I0 67 3g P64 (G11) (KEY1) P41—<«>Coor}68 37 P63 (612) (KEY2) P4269 3qtI <> P62 (613) (ceva) paar dEo——760 (615) (KEYS) PASC 72 33.0 <voo (CINA/KEY7) P4774 31-06 momen aaa (PWMPDO) PSS<>TITEO we nwnoa SrA MEBERSASa yey ro HOUGOUUUUUOUCUOOOUdC OOOO SEEPAASLEREABRRSEAEAARARL <8 eB Be ~ BLOCK VO Ports Output Ports Wo ports DIAGRAM P97 P87 77 P67)

0 P80 P70 P60

oO ‘a 8 OD Powersupply { YOO [rs] [re] [rs] (Ko [Ko f= i= — A © SR’ > 0 | t 1] J =a Data Memory il ‘System Controller retin Tet > standby Controller [ neer | tf tf eos Tine bare Te oa Sera ollie Resonator XIN High Timer Timer/Counters ||| Timer/Counters Interfaces peconator {A eh Ta [io [ #55] eae ao Pins Low Generator Watchdog Converter (¢ frequ. Timer ( O Cy i 0 O | [ro] [es] Les] | Leak P22 PO7 P17 P37 P55 Pa7 to. to to to to to. P20 POO P10 P30 P50 P40 W/O Ports 3-71-2

TOSHIBA TMP87CM71/N71/P71/S71 PIN FUNCTION Two 8-bit programmable input/output P17, P16, P14 vo ports (tri-state). ee) nneunafen une) | Each bit of these ports can be [TimevCounter 2m P13 (DVO) VO (Output) _| individually configured as an input or an | pivider output . ~ output under software control. External interrupt input 2 or P12 (INT2/TC1) During reset, all bits are configured as | Timer/Counter Linput. P11 (INT1) VO(Input) | INPUTS . External interrupt input 1 i ssssesettnssentensteneees When used as a divider output, the latch [.cs.ccssussssssessesstestsststentseeseneest P10 (INTO) must be set to "1". External interrupt input 0 P22 (XTOUT) VO (Output) . Resonator connecting pins (32.768 kHz). convient] 3ebitinputoutput port with latch. For inputting external clock, XTIN is used P21 (XTIN) vo (input) | When used as an input port, the latch and XTOUTis opened. mune P2O(INTS/STOP) must be set to "1". External interrupt input 5 or STOP mode release signal input P37 (HSO) VO (Output) HSO serial data output P36 vo P35 (HSCK) S-bit input/output port with latch. HS0 serial clock output crmmnanecnnenen] YOCOutpUD | When used as an input port, a HSO fromm PIA (SO) caframnnnnumnneef OUtPUt, a SIO input/output, a |SOserialdataoutput P33 (SI) VO (Input) | timer/counter input, or an interrupt | siQ serial data input snmp} input, the lateh must Be set to "1". prvsstcttssnnvinstistnsssiseieetneenentseeneee P32 (SCK) VO (VO) SIO serial clock input/output P31 (TCA) Timer/Counter 4 input xternal interrupt input 3 or P30 (INT3/TC3) Timer/Counter 3 input P47 (CIN4/ KEY7), i Comparator inputs or Bae (KEYS) rf When used as an input port, the latch : to P40 (KEYO} must be set to "1". Key scan inputs _ ; 8-bit PWM output or p54 vO When used as an input port, a compa- VO (Input “ i to P50 (CIN3} (Input) | latch must be set to “1”. Comparator inputs P67 (G8) to P60 (G15) . Three 8-bit high breakdown voltage V/O | ver digit driver outputs P77(G0)to P70(G7)_| VO (Output) | ports with the latch. When used as a VFT driver output, the latch must be cleared to"0". P97 (515) to P90 (S8) VET segment driver outputs Output 8-bit high breakdown voltage output port with | (Key strobe outputs) P87 (57) to P80 (SO) (Output, _| latch When tied’ as VET eeter‘cutou the latch Jx, xout | input, output | Resonator connecting pins for high-frequency clock. XIN, XOUT Input, Output_| For inputting external clock, XIN is used and XOUT is opened. RESET Reset signal input or watchdog timer output/address-trap-reset output/system-clock- RESET vo reset output. °9 i” if Power Supply 3-71-3

TOSHIBA TMP87CM71/N71/P71/S71 OPERATIONAL DESCRIPTION 1. CPU CORE FUNCTIONS The CPU core consists of a CPU, a system clock controller, an interrupt controller, and a watchdog timer. This section provides a description of the CPU core, the program memory (ROM), the data memory (RAM), and the reset circuit. 1.1. Memory Address Map The TLCS-870 Series is capable of addressing 64K bytes of memory. Figure 1-1 shows the memory address maps of the 87CM71/N71/P71/S71. In the TLCS-870 Series, the memory is organized 4 address spaces (ROM, RAM, SFR, and DBR). It uses a memory mapped I/O system, and all I/O registers are mapped in the SFR/DBR address spaces. There are 16 banks of general-purpose registers. The register banks are also assigned to the first 128 bytes of the RAM address space. 903 64 bytes 903 Gabytes | 4, | Sabytes | oo. | Sabytes : : 0040 0040 Register banks : 128bytes | : 128 bytes 128bytes |: 128 bytes | J (g registers x16 banks) OOBF OOBF OBE | -sssesseseseeeese] OBE eeeeeeesssseeeses ooco 00co 00co 00co RAM): i i : Note : | 1920bytes | : | 1408 bytes 1408 bytes | : | 1408bytes | pom; ReadOnly Memory includes : : H i Program memory H i H RAM; Random Access Memory includes : i : Data memory 083F 063F 063F 063F Stack is a eit zit = General-purpose register banks OF80 [ ] OF80 [ | oFso OF80 SFR; Special Function Register includes : : H A 0 ports DBR i i Peripheral control registers i 128 bytes i 128 bytes 128 bytes 128 bytes Perpheralstatesreguters FFF FFF : System control registers vs are FS aL OFF = Interrupt control registers 1100 ~i-> viF rir >= Program Status Word \\ 4 j H i ni DBR; — Data Buffer Register includes : p00 6900 8900 SIO data buffer i 098 bytesl | a og bytes 740708 bytes 2512 bytes HSO data buffer i i : : VET display data buffer FFOO ~ FFOO ~ “-) FEOO FFOO ROI : i H i H 192 bytes = 192 bytes = E 192 bytes => 192 bytes FFBF FFBE F F FED fom] Beo Pome BEBE foo BEBE freee ) Vectrtableforvecor | sey greater EDF 32 bytes EEE 3abytes | repr]. 32s | eepe|.. 32 bytes] ) instructions i6vectors) | Ore FFEO FFEO Vector table for interrupts/ rere | 32bytes | grep | 32bytes | peep | 32bytes | fe] s2bytes ) wee weeton P| instructions 87CS71 87CP71 87CN71 87CM71 Figure 1-1. Memory Address Maps 3-71-4

TOSHIBA TMP87CM71/N71/P71/S71 1.2. Program Memory (ROM) The 87CM71 has a 32K x8-bit (addresses 8000}4-FFFF}), the 87CN71 has a 40K x 8-bit (addresses 6000}- FFFFy), the 87CP71 has a 48K x 8-bit (addresses 4000}-FFFF}), the 87CS71 has a 60kx8-bit (addresses 1100,4-FFFFY) program memory (mask programmed ROM). Figure 1-2 shows the program memory map. Addresses FFOO}4-FFFF} in the program memory can also be used for special purposes. (1) Interrupt /Reset vector table (addresses FFEO}4-FFFFH) This table consists of a reset vector and 15 interrupt vectors (2 bytes/vector). These vectors store a reset start address and interrupt service routine entry addresses. (2) Vector table for vector call instructions (addresses FFCO4-FFDF}) This table stores call vectors (subroutine entry address, 2 bytes/vector) for the vector call instructions [CALLV n]. There are 16 vectors. The CALLV instruction increases memory efficiency when utilized for frequently used subroutine calls (called from 3 or more locations). (3) Entry area (addresses FFOO}4-FFFFy) for page call instructions This is the subroutine entry address area for the page call instructions [CALLP n]. Addresses FFOO}- FFBFy are normally used because address FFCO}-FFFF} are used for the vector tables. Programs and fixed data are stored in the program memory. The instruction to be executed next is read from the address indicated by the current contents of the program counter (PC). There are relative jump and absolute jump instructions. The concepts of page or bank boundaries are not used in the program memory concerning any jump instruction. Address ROM Example: The relationship between the | 1100, contents jump instructions and the PC. fans {8000 © 5-bit PC-relative jump [JRS cc, $+2+d] Example: me relationship ESC4H: JRS T, $+2+08H Foo andcallgroup When JF = 1, the jump is made to E8CEy, B instructions/Interrupt/ which is 08} added to the contents of the Reset PC. (The PC contains the address of the Bc cccccsscsseeeeeenec] instruction being executed +2; | FFIB Yona CALLP 7BH ; PC<-FF7By therefore, in this case, the PC contents FFBF are E8C4y + 2 = E8C6y.) FFCO 56 CALLV OH ; PC C856y FFC1 | callvector(H) | C8 ® 8-bit PC-relative jump UR cc, $+2+d] FFC2 E8C4H: JR Z, $+2+80H When ZF = 1, the jump is made to E846y, i which is FF804 (-128) added to the | FFDF current contents of the PC. FFEO 68 INTS i PC<—D368q FFE1 [interrupt vector (H)| D3 @ 16-bit absolute jump [JP a] FFE2 | | E8C4H: JP 0C235H An unconditional jump is made to | FFFD address C235y. The absolute jump | FFFE 3 RESET PC CO3Ey instruction can jump anywhere within | FFFF |_resetvector(H) | CO the entire 64K-byte space. Figure 1-2. Program Memory Map In the TLCS-870 Series, the same instruction used to access the data memory (e. g. [LD A, (HL) ] ) is also used to read out fixed data (ROM data) stored in the program memory. The register-offset-PC-relative addressing (PC + A) instructions can also be used, and the code conversion, table look-up and n-way multiple-direction jump processing can easily be programmed. 3-71-5

TOSHIBA TMP87CM71/N71/P71/S71 Example 1 : Loads the ROM contents at the address specified by the HL register pair contents into the accumulator (HL2 4000,): LD A, (HL) ; ACROM (HL) Example 2 : Converts BCD to 7-segment code (common anode LED). When A = 05x, 92 is output to port P3 after executing the following program: ADD A, TABLE-$-4 P3<-ROM (TABLE +A) gi, LD (P3), (PC +A) G i. JRS T, SNEXT ES TABLE: DB OCOH, OFSH, OA4H, OBOH, 99H, 92H, 82H, OD8H, 80H, 98H ef (B SNEXT : Sav oh Notes: “$” isa header address of ADD instruction. f Example 3 : N-way multiple jump in accordance with the contents of accumulator (05 AS 3): SHLC A ; if A=00q then PC-C234y 78. Jp (PC+A) if A=01, then PC-C378, if A=02y then PC—-DA37y if A=03} then PC-E1B04 BO Dw 0C234H, 0C378H, 0DA37H, 0E1B0H ———— 1.3. Program Counter (PC) The program counter (PC) is a 16-bit register which indicates the program memory address where the instruction to be executed next is stored. After reset, the user defined reset vector stored in the vector table (addresses FFFF} and FFFE}) is loaded into the PC ; therefore, program execution is possible from any desired address. For example, when COy and 3Ey are stored at addresses FFFFy and FFFEH, respectively, the execution starts from address CO3Ey after reset. The TLCS-870 Series utilizes pipelined processing (instruction pre-fetch); therefore, the PC always indicates 2 addresses in advance. For example, while a 1-byte instruction stored at address C123} is being executed, the PC contains C125. MsB rr) is1ai92i109 8765-43210 — Pecontents C2 X_a+t X_a+2_ X_a+3_) (a)_ Configuration (b)_ Timing chart of PC Contents and Instruction Execution Figure 1-3. Program Counter

1.4 Data Memory (RAM)

The 87CM71/N71/P71 each have 1.5K x 8-bits (addresses 0040};-063F}) of data memory (static RAM), and the 87CS71 has 2.0kx8-bits (addresses 0040};-083Fy) of data memory. Figure 1-4 shows the data memory map. Addresses 0000}-OOFF} are used as a direct addressing area to enhance instructions which utilize this addressing mode; therefore, addresses 0040}-O0FFy in the data memory can also be used for user flags or user counters. General-purpose register banks (8 registers x 16 banks) are also assigned to the 128 bytes of addresses 0040}-00BFy. Access as data memory is still possible even when being used for registers. For example, when the contents of the data memory at address 0040} is read out, the contents of the accumulator in the bank 0 are also read out. The stack can be located anywhere within the data memory except the register bank area. The stack depth is limited only by the free data memory size. For more details on the stack, see section “1.7 Stack and Stack Pointer”. The 87CM71/N71/P71/S71 cannot execute programs placed in the data memory. When the program counter indicates a data memory address, a bus error occurs and an address-trap-reset applies. The RESET pin goes low during the address-trap-reset. 3-71-6

TOSHIBA TMP87CM71/N71/P71/S71 Example1 : If bit 2 at data memory address 00COy is “1”, 00} is written to data memory at address 00E3y; otherwise, FFy is written to the data memory at address 00E3}: TEST (00COH).2 ; if (004) = 0 then jump JRS T,SZERO CLR (00E3H) j (Q0E3}) 004 JRS T,SNEXT SZERO: Lo (00E3H), OFFH } (Q0E3q) Fy SNEXT: Example 2 : Increments the contents of data memory at address OOF5y, and clears to 004 when 10} is exceeded: INC (OOFSH) j (QOF5y) — (OOF5}) +1 AND (QOFSH), OFH j (QOF5y) — (OOF5y) AOFH The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. Note that the general-purpuse registers are mapped in the RAM ; therefore, do not clear RAM at the current bank addresses. Example : Clears RAM to “004” except the bank 0: (87CM71/N71/P71) LD HL, 0048H ; Sets start address to HL register pair LD AH } Sets initial data (00) to A register Lo BC, O5F7H ; Sets number of byte to BC register pair SRAMCLR: LD (HL+), A DEC BC JRS F, SRAMCLR Address 0123456789 ABCDEF Address 0123456789 ABCDEF 040,,| , Registerbanko _ Register bank 1 ooa0, |, Register banko | Registerbank 1 00s |. Registerbank2 |” Register bank 3” ooso |. Registerbank2 |” Register bank 3 oos0 |. Registerbank 10° |" Register bank 11 0090 |. Registerbank'10 |” Register bank 11 ooao |. Registerbank 12” |" Register bank 13 ooao |. Registerbank 12” |" Register bank 13 Direct addressing area ooso |. Registerbank 14°” |” Register bank 15 oowo |. Registerbank 14" |” Register bank 15 oro fi PtP i pie Ei Ei oro [iP iP EEE EEE PEELE o30 | PPP PPP Pee ono | PPP PPP Pees 87¢S71 87CM71/N71/P71 Figure 1-4. Data Memory Map 3-71-7

TOSHIBA TMP87CM71/N71/P71/S71

1.5 General-purpose Register Banks

The general-purpose registers are mapped into addresses 0040}-O0BFy in the data memory as shown in Figure 1-4. There are 16 register banks, and each bank contains eight 8-bit registers W, A, B, C, D, E, H, and L. Figure 1-5 shows the general-purpose register bank configuration. | bank 15 (00B8~00BF},) bank 14 (00B0~00B7,,) prample : Banko bank 13 (00A8~O0AF}) i wia bank 12 (00A0~00A7,:) (poe HW) Moca # bank 4 (0060~0067})) Do: Ee sessed bank 2 (0050~0057;) Haat HEL bank 1 (0048~004Fy) (004711) :(00461) bank 0 (0040~0047;,) (a)_Configuration (b) Address assignments of registers Figure 1-5. General-purpose Register Banks In addition to access in 8-bit units, the registers can also be accessed in 16-bit units as the register pairs WA, BC, DE, and HL. Besides its function as a general-purpose register, the register also has the following functions: (1) A,WA The A register functions as an 8-bit accumulator and WA the register pair functions as a 16-bit accumulator (W is high byte and A is low byte). Registers other than A can also be used as accumulators for 8-bit operations. Examples: @® ADD A,B ; Adds B contents to A contents and stores the result into A. @ SUB WA, 1234H ; Subtracts 1234} from WA contents and stores the result into WA. J SUB E,A ; Subtracts A contents from E contents, and stores the result into E. (2) HL, DE The HL and DE specify a memory address. The HL register pair functions as data pointer (HL) / index register (HL +d) / base register (HL + C), and the DE register pair function as a data pointer (DE). The HL also has an auto-post- increment and auto-pre-decrement functions. This function simplifies multiple digit data processing, software LIFO (last-in first-out) processing, etc. Example 1: ® LD A, (HL) ; Loads the memory contents at the address specified by HL into A. @ LD A, (HL +52H) ; Loads the memory contents at the address specified by the value obtained by adding 52} to HL contents into A. @ LD A, (HL+C) ; Loads the memory contents at the address specified by the value obtained by adding the register C contents to HL contents into A. @ LDA, (HL+) ; Loads the memory contents at the address specified by HL into A. Then increments HL. 6 LD A, (-HL) ; Decrements HL. Then loads the memory contents at the address specified by new HL into A. The TLCS-870 Series can transfer data directly memory to memory, and operate directly between memory data and memory data. This facilitates the programming of block processing. 3-71-8

TOSHIBA TMP87CM71/N71/P71/S71 Example 2: Block transfer LD B,m } m=n-1(n: number of bytes to transfer) LD HL, DSTA ; Sets destination address to HL LD DE, SRCA j Sets source address to DE SLOOP: LD — (HL), (DE) ; (HL) — (DE) INC HL >; HL@eHL+1 INC DE ; DE@DE+1 DEC B ; BeB-1 JRS F, SLOOP ; IF B20 Then loop (3) B,C, BC Registers B and C can be used as 8-bit buffers or counters, and the BC register pair can be used as a 16-bit buffer or counter. The C register functions as an offset register for register-offset index addressing (refer to example 1 @ above) and as a divisor register for the division instruction [DIV gg, c]. Example 1 : Repeat processing LO ee B OL, ; Sets nas the number of repetitions to B SREPEAT: ; Processing |: (n + 1 times processing) DEC B IRS F, SREPEAT Example2 : Unsigned integer division (16-bit + 8-bit) Div WA, C ; Divides the WA contents by the C contents, places the quotient in A and the remainderinW. The general-purpose register banks are selected by the 4-bit register bank selector (RBS). During reset, the RBS is initialized to “0”. The bank selected by the RBS is called the current bank. Together with the flag, the RBS is assigned to address 003Fy in the SFR as the program status word (PSW). There are 3 instructions [LD RBS, n], [PUSH PSW] and [POP PSW] to access the PSW. The PSW can be also operated by the memory access instruction. Example1 : Incrementing the RBS INC (003FH) ; RBS<RBS +1 Example2 : Reading the RBS LD A, (003FH) ; A@PSW(A3.9 — RBS, A7-4¢-Flags) Highly efficient programming and high-speed task switching are possible by using bank changeover to save registers during interrupt and to transfer parameters during subroutine processing. During interrupt, the PSW is automatically saved onto the stack. The bank used before the interrupt was accepted is restored automatically by executing an interrupt return instruction [RETI]/[RETN] ; therefore, there is no need for the RBS save/restore software processing. The TLCS-870 Series supports a maximum of 15 interrupt sources. One bank is assigned to the main program, and one bank can be assigned to each source. Also, to increase the efficiency of data memory usage, assign the same bank to interrupt sources which are not nested. Example: Saving /restoring registers during interrupt task using bank changeover. PINT1: LD RBS, n ; RBS <n (Bank changeover) RETI ; Maskable interrupt return (Bank restoring) 3-71-9

TOSHIBA TMP87CM71/N71/P71/S71

1.6 Program Status Word (PSW)

The program status word (PSW) consists of a register bank selector (RBS) and four flags, and the PSW is assigned to address 003Fy in the SFR. The RBS can be read and written using the memory access instruction (e. g. [LD A, (003FH)], [LD (003FH), A], however the flags can only be read. When writing to the PSW, the change specified by the instruction is made without writing data to the flags. For example, when the instruction [LD (003FH), 05H] is executed, “5” is written to the RBS and the JF is set to “1”, but the other flags are not affected. [PUSH PSW] and [POP PSW] are the PSW access instructions.

1.6.1 Register Bank Selector (RBS)

The register bank selector (RBS) is a 4-bit register used to 7 Z 6 Z 5 Z 432 Z 19 select general-purpose register banks. For example, when RBS = 2, bank 2 is currently selected. During reset, the RBS —_—_— is initialized to “0”. Figure 1-6. PSW (Flags, RBS) Configuration

1.6.2 Flags

The flags are configured with the upper 4 bits : a zero flag, a carry flag, a half carry flag and a jump status flag. The flags are set or cleared under conditions specified by the instruction. These flags except the half carry flag are used as jump condition “cc” for conditional jump instructions [JR cc, $ +2 + d]/[JRS cc, $+2+d]. After reset, the jump status flag is initialized to “1”, other flags are not affected. (1) Zero flag (ZF) The ZF is set to “1” if the operation result or the transfer data is 00} (for 8-bit operations and data transfers)/0000y (for 16-bit operations); otherwise the ZF is cleared to “0”. During the bit manipulation instruction [SET, CLR, and CPL], the ZF is set to “1” if the contents of the specified bit is “0”; otherwise the ZF is cleared to “0”. This flag is set to “1” when the upper 8 bits of the product are 004 during the multiplication instruction [MUL], and when 00} for the remainder during the division instruction [DIV]; otherwise it is cleared to “0”. (2) Carry flag (CF) The CF is set to “1” when a carry out of the MSB (most significant bit) of the result occurred during addition or when a borrow into the MSB of the result occurred during subtraction; otherwise the CF is cleared to “0”. During division, this flag is set to “1” when the divisor is 00} (divided by zero error), or when the quotient is 1004 or higher (quotient error); otherwise it is cleared. The CF is also affected during the shift/rotate instructions [SHLC, SHRC, ROLC, and RORC]. The data shifted out from a register is set to the CF. This flag is also a 1-bit register (a boolean accumulator) for the bit manipulation instructions. Set/clear/complement are possible with the CF manipulation instructions. Example1 : Bit manipulation XOR CF, (009AH) .0 LD (0001H). 2, CF Example2 : Arithmetic right shift LD CF, A.7 RORC A (3) Half carry flag (HF) The HF is set to “1” when a carry occurred between bits 3 and 4 of the operation result during an 8- bit addition, or when a borrow occurred from bit 4 into bit 3 of the result during an 8-bit subtraction; otherwise the HF is cleared to “0”. This flag is useful in the decimal adjustment for BCD operations (adjustments using the [DAA r], or [DAS r] instructions). 3-71-10

TOSHIBA TMP87CM71/N71/P71/S71 Example: BCD operation (The A becomes 47 after executing the following program when A = 19, B = 28) ADD AB } AC41y, HPO 1,CF=0 DAA A ; AG Aty + 064 = 474 (decimal-adjust) (4) Jump status flag (JF) Zero or carry information is set to the JF after operation (e.g. INC, ADD, CMP, TEST). The JF provides the jump condition for conditional jump instructions [JRS T/F, $+2+d], [JR T/F, $+24+d] (T or Fis a condition code). Jump is performed if the JF is "1" for a true condition (T), or the JF is “0” for a false condition (F). The JF is set to “1” after executing the load/exchange/swap/nibble rotate/jump instruction, so that [URST, $ +2 +d] and [JRT, $ + 2 +d] can be regarded as an unconditional jump instruction. Example: Jump status flag and conditional jump instruction INC A JRS T, SLABLE1 ; Jump when a carry is caused by the immediately : preceding operation instruction. Lo A, (HL) JRS T, SLABLE2 ; JF is set to "1" by the immediately preceding i instruction, making it an unconditional jump instruction. Example: The accumulator and flags will become as shown below after executing the following instructions when the WA register pair, the HL register pair, the data memory at address 00C5, the carry flag and the half carry flag contents being “219A”, “00C5y", "D7", "1" and “0”, respectively. Instruction Instruction ADDC A, (HL) 72 tioiaia INC OA 98 of oi1io suBB_ A, (HL) 2 tioitio ROLC A 35 1: 0:1:50 cmp A, (HL) 9A oioi1tio RORC A co oi 0:00 AND A, (HL) 92 oioitio ADD WA, 0FS08H 16A2 tioi1io LD A, (HL) D7 1ioi1:o MUL W, A 13DA O:0:1:50 ADD A, 66H 00 tiaiaia SET AS BA tenia 0

1.7 Stack and Stack Pointer

1.7.1 Stack

The stack provides the area in which the return address or status, etc. are saved before a jump is performed to the processing routine during the execution of a subroutine call instruction or the acceptance of an interrupt. On a subroutine call instruction, the contents of the PC (the return address) is saved; on an interrupt acceptance, the contents of the PC and the PSW are saved (the PSW is pushed first, followed by PCy and PC,). Therefore, a subroutine call occupies two bytes on the stack; an interrupt occupies three bytes. When returning from the processing routine, executing a subroutine return instruction [RET] restores the contents to the PC from the stack; executing an interrupt return instruction [RETI] / [RETN] restores the contents to the PC and the PSW (the PC, is popped first, followed by PC} and PSW). The stack can be located anywhere within the data memory space except the register bank area, therefore the stack depth is limited only by the free data memory size. 3-71-11

TOSHIBA TMP87CM71/N71/P71/S71

1.7.2 Stack Pointer (SP)

The stack pointer (SP) is a 16-bit register containing the address of the next free locations on the stack. via Bpinw9s7654321 : The SP is postdecremented when a subroutine call or a push instruction is executed, or when an interrupt is accepted; and ack Pointer (SP) the SP is preincremented when a return or a pop instruction is Figure 1-7. Stack Pointer executed. Figure 1-8 shows the stacking order. The SP is not initialized hardware-wise but requires initialization by an initialize routine (sets the highest stack address). [LD SP, mn], [LD SP, gg] and [LD gg, SP] are the SP access instructions (mn ; 16-bit immediate data, gg ; register pair). Example 1 : To initialize the SP (87CM71/N71/P71) LD SP, 063FH ; SPA-063Fy Example 2 : To read the SP LD HL, SP 7 HLe-sP At acceptance of interrupt At execution of or At execution of a CALL/CALLV/CALLP. at execution of Atexecution of a RETURETN instruction a SWI instruction a RET instruction instruction 063C ossc| 063C oesc] 063D 063D) PC, 063D 063D} PC, 063 | PC, ~<tpus, 063} PCH ~<PEY o63e| PCL te, 063E| PCH —pup” seescetsrne] Bu session poset] BO eeccitrthenen O63 | PCH Sp O63 | PSM 063F PCH 063F | PSP 0040 stack depth reer = sar t Bees : SP after, L_063D 063C 063F 063F (a)_ Stacking order b) Stack depth Figure 1-8. Stack

1.8 System Clock Controller

The system clock controller consists of a clock generator, a timing generator, and a stand-by controller. Timing generator control register toe generator i 0036), XIN pL: fe XZ r Ct | High-frequency |“: Timing Oo 1: : Stand-by controller ok clock oscillator | generator xOUT “TE : to i ti H — XTIN Ot i i System clocks i | Oo oT | bowtreauency | | fs 00384 00394 XTOUT : Hi verses . seers? Clock generator control System control registers Figure 1-9. System Clock Controller 3-71-12

TOSHIBA TMP87CM71/N71/P71/S71

1.8.1 Clock Generator

The clock generator generates the basic clock which provides the system clocks supplied to the CPU core and on-chip peripheral hardware. It contains two oscillation circuits: one for the high-frequency clock and one for the low-frequency clock. Power consumption can be reduced by switching of the system clock controller to low-power operation based on the low-frequency clock. The high-frequency (fc) and low-frequency (fs) clocks can be easily obtained by connecting a resonator between the XIN/XOUT and XTIN/XTOUT pins, respectively. Clock input from an external oscillator is also possible. In this case, external clock is applied to the XIN/XTIN pin with the XOUT/XTOUT pin not connected. The 87CM71/N71/P71/S71 are not provided an RC oscillation. FTmEa====""""" High-frequency clock “~~~ —=T TTP PEE====M=M==— Low-frequency clock “~7~===== === ' XOUT XIN XOUT i ' XTIN XTOUT XTIN XTOUT i H Oo hoot oO H ' toot i (open) $3 (open) ' toot H ' toot i (a) Crystal/Ceramic (b) External oscillator (c) Crystal (d) External oscillator ae Figure 1-10. Examples of Resonator Connection Note : Accurate Adjustment of the Oscillation Frequency: Although no hardware to externally and directly monitor the basic clock pulse is not provided, the oscillation frequency can be adjusted by providing a program to output fixed frequency pulses to the port while disabling all interrupts and monitoring this pulse. With a system requiring adjustment of the oscillation frequency, the adjusting program must be created beforehand. Example: To output the high-frequency oscillation frequency adjusting monitor pulse to P13 (BVO) pin. SFCCHK: LD (PICR), 00001000B ; Configures port P13 as an output SET (P1).3 i P13 output latch —1 output waveform LD (TBTCR), 11100000B ; Enables divider output | | | | IRS ,$ ; Loops endless <— fy1024 ——>

1.8.2 Timing Generator

The timing generator generates from the basic clock the various system clocks supplied to the CPU core and peripheral hardware. The timing generator provides the following functions : @® Generation of main system clock ® Generation of divider output (DVO) pulses ® Generation of source clocks for time base timer ® Generation of source clocks for watchdog timer ®© Generation of internal source clocks for timer/counters TC1 - TC4 © Generation of internal clocks for serial interfaces SIO and HSO @ Generation of source clocks for VFT driver circuit ® Generation of warm-up clocks for releasing STOP mode ® Generation of a clock for releasing reset output (1) Configuration of Timing Generator The timing generator consists of a 21-stage divider with a divided-by-4 prescaler, a main system clock generator, and machine cycle counters. An input clock to the 7th stage of the divider depends on 3-71-13

TOSHIBA TMP87CM71/N71/P71/S71 (fc or 1/fs (s} r i lain System Clock | | | l | l | l state Tso Tost sa sa Tso st sess 0.5ys at f¢=8MHz 122 at_fs = 32.768 kHz Figure 1-13. Machine Cycle

1.8.3 Stand-by Controller

The stand-by controller starts and stops the oscillation circuits for the high-frequency and low-frequency clocks, and switches the main system clock. There are two operating modes: single-clock and dual-clock. These modes are controlled by the system control registers (SYSCR1, SYSCR2). Figure 1-14 shows the operating mode transition diagram and Figure 1-15 shows the system control registers. Either the single-clock or the dual-clock mode can be selected by an option during reset. (1) Single-clock mode Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT) pins are used as input/output ports. In the single-clock mode, the machine cycle time is 4/fc [s] (0.5 us at fc=8 MHz). @ NORMAL1 mode In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock. In the case where the single-clock mode has been selected as an option, the 87CM71/N71/P71/S71 are placed in this mode after reset. ® IDLE1 mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however, on-chip peripherals remain active (operate using the high-frequency clock). IDLE1 mode is started by setting IDLE bit in the system control register 2 (SYSCR2), and IDLE1 mode is released to NORMAL1 mode by an interrupt request from the on-chip peripherals or external interrupt inputs. When IMF (interrupt master enable flag) is “1” (interrupt enable), the execution will resume upon acceptance of the interrupt, and the operation will return to normal after the interrupt service is completed. When IMF is “0” (interrupt disable), the execution will resume with the instruction which follows IDLE mode start instruction. @ STOP1 mode In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The internal status immediately prior to the halt is held with the lowest power consumption during this mode. The output status of all output ports can be set to either output hold or high-impedance under software control. STOP1 mode is started by setting STOP bit in the system control register 1 (SYSCR1), and STOP1 mode is released by an input (either level-sensitive or edge-sensitive can be programmably selected) to the STOP pin. After the warming-up period is completed, the execution resumes with the next instruction which follows the STOP mode start instruction. 3-71-15

TOSHIBA TMP87CM71/N71/P71/S71 (2) Dual-clock mode Both the high-frequency and low-frequency oscillation circuits are used in this mode. P21 (XTIN) and P22 (XTOUT) pins cannot be used as input/output ports. The main system clock is obtained from the high-frequency clock in NORMAL2 and IDLE2 modes, and is obtained from the low-frequency clock in SLOW and SLEEP modes. The machine cycle time is 4/fc [s] (0.5 us at fc = 8 MHz) in NORMAL2 and IDLE2 modes, and 4/fs [s] (122 ys at fs = 32.768 kHz) in SLOW and SLEEP modes. Note: 87PP71 and 87PS71 are placed in the single-clock mode during reset. To use the dual-clock mode, the low-frequency oscillator should be turned on by executing [SET (SYSCR2). XTEN] instruction. @® NORMAL2 mode In this mode, the CPU core is operated using the high-frequency clock. The on-chip peripherals are operated on the high-frequency clock and/or low-frequency clock. In case that the dual-clock mode has been selected as an option, the 87CM71/N71/P71/S71 are placed in this mode after reset. ® SLOW mode This mode can be used to reduce power-consumption by turning off oscillation of the high- frequency clock. The CPU core and on-chip peripherals are operated using the low- frequency clock. Switching back and forth between NORMAL2 and SLOW modées is performed by the system control register 2. ® IDLE2 mode In this mode, the internal oscillation circuits remain active. The CPU and the watchdog timer are halted; however, on-chip peripherals operate using the high-frequency clock and/or the low-frequency clock. Starting and releasing of IDLE2 mode are the same as for IDLE1 mode, except that operation returns to NORMAL2 mode. @® SLEEP mode In this mode, the internal oscillation circuit of the low-frequency clock remains active. The CPU, the watchdog timer, and the internal oscillation circuit of the high- frequency clock are halted; however, on-chip peripherals operate using the low-frequency clock. Starting and releasing of SLEEP mode is the same as for IDLE1 mode, except that operation returns to SLOW mode. © STOP2 mode Asin STOP1 mode, all system operations are halted in this mode. 3-71-16

TOSHIBA TMP87CM71/N71/P71/S71 reset release software software IDLE! NORMAL1 sToPt a bP interrupt ‘STOP pin input (a) Single-clock mode reset release software oLe2 NORMAL2 interrupt “a ere STOP pin >) | stor2 input ent mode ae SLEEP on“ stow | 47 -- mode mode j-o7" software interrupt (b) Dual-clock mode Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; STOP1 and STOP2 are called STOP; and IDLE1, IDLE2 and SLEEP are called IDLE. Note2: The 87PP71/PS71 don't have RESET2 mode. Operating mode CPU core High-frequency | Low-frequency Peripherals time 8 7 | tuming on P G [NORMALT | oscillation | turning off operate operate ates] S |ipiet oscillation (Note 1) & i halt oscillation turning on - ¥ oscillation onefrequencY | (uigh and/or Low) afc ts] & |invez turning on (Note 1) a oscillation

3 SLOW turning off Low-frequency | Low-frequency ast

SLEEP oscillation (Note 2) 7 halt turning off h sTor2 oscillation alt Note 1: The High-Speed Serial Output and the Comparator inputs are halted in IDLE1/IDLE2 mode because CPU core is halted. Note 2: The Vacuum Fluorescent Tube driver circuit and the High Speed Serial Output and the Comparator inputs are halted. Figure 1-14. Operating Mode Transition Diagram 3-71-17

TOSHIBA TMP87CM71/N71/P71/S71 System Control Register 1 7 6 5 4 3 2 4.0 (coe) Jecciad (initial value: 0000 00r«) 0 : CPU core and peripherals remain active STOP | STOP modestart 1: CPU core and peripherals are halted (start STOP mode) rei _ | Release method 0 : Edge-sensitive release for STOP mode 1: Level-sensitive release Operating mode 0 : Return to NORMAL mode REM after STOP mode mw outen | Pertoutput control 0 : High-impedance during STOP mode 1: Remain unchanged . 00: 3x2"/fe or 3x2°/fs Is] wut | Warming-up time at 01: -2%/fe or 2° /fs releasing STOP mode 1*: Reserved Note 1: Alwaysset RETM to “0” when transiting from NORMAL1 mode to STOP1 mode and from NORMAL2 mode to STOP2 mode. Always set RETM to "1” when transiting from SLOW mode to STOP2 mode. Note2: When STOP mode is released with RESET pin input, a return is made to NORMAL mode regardless of the RETM contents. Note3: fc ; high-frequency clock [Hz] fs; low-frequency clock [Hz] *; don’t care Note 4: Bits 1 and 0 in SYSCRI1 are read in as undefined data when a read instruction is executed. Note5: When the STOP mode is started by specifying OUTEN = “0”, the internal input of port is fixed to “0” and the interrupt of the falling edge may be set. System Control Register 2 7 6 5 A Bi Beccceeie lh ccceg oes xen [High-frequency oscillator | 0 : Turn off oscillation control 1: Turn on oscillation xTen | Low-frequency oscillator | 0 : Turn off oscillation control 1: Turn on oscillation Main system clock select Rw in sy: . 0 : High-frequency clock SYSCK | (write)/main system clock] + ° Low-frequency clock monitor (read) 0: CPU and watchdog timer remain active IDLE | IDLE mode start 1: CPU and watchdog timer are stopped (start IDLE mode) Note 1: Areset is applied (RESET pin output goes low) if both XEN and XTEN are cleared to “0”. Note2: Donot clear XEN to “0” when SYSCK =0, and do not clear XTEN to “0” when SYSCK = 1. Note3: WDT; watchdog timer, * ; don’t care Note 4: Bits 3-0 in SYSCR2 are always read in as “1” when a read instruction is executed. Note5: An optional initial value can be selected for XTEN. Always specify when ordering ES (engineering sample). operating mode after reset Single-clock mode (NORMAL1) Dual-clock mode (NORMAL2) Note6: The instruction for specifying Masking Option (Operating Mode) in ES Order Sheet is described in ADDITIONAL INFORMATION “Notice for Masking Option of TLCS-870 series” section 8. Figure 1-15. System Control Registers 3-71-18

TOSHIBA TMP87CM71/N71/P71/S71

1.8.4 Operating Mode Control

(1) STOP mode (STOP1, STOP2) STOP mode is controlled by the system control register 1 (SYSCR1) and the STOP pin input. The STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP mode is started by setting STOP (bit 7 in SYSCR1) to “1”. During STOP mode, the following status is maintained. @® Oscillations are turned off, and all internal operations are halted. @ The data memory (except for DBR), registers and port output latches are all held in the status in effect before STOP mode was entered. The port output can be select either output hold or high-impedance by setting OUTEN (bit 4 in SYSCR1). @ The divider of the timing generator is cleared to “0”. @® The program counter holds the address of the instruction following the instruction which started STOP mode. STOP mode includes a level-sensitive release mode and an edge-sensitive release mode, either of which can be selected with RELM (bit 6 in SYSCR1). a. Level-sensitive release mode (RELM = 1 In this mode, STOP mode is released by setting the STOP pin high. This mode is used for capacitor back-up when the main power supply is cut off and for long term battery back-up. When the STOP pin input is high, executing an instruction which starts the STOP mode will not place in the STOP mode but instead will immediately start the release sequence (warm-up). Thus, to start the STOP mode in the level-sensitive release mode, it is necessary for the program to first confirm that the STOP pin input is low. The following method can be used for confirmation: @ Using an external interrupt input INTS (INTS is a falling edge-sensitive input). Example: Starting STOP mode with an INT5 interrupt. PINTS : TEST (P2).0 ; To reject noise, STOP mode does not start if, JRS F, SINTS port P20is at high LD (SYSCR1), 01000000B ; Sets up the level-sensitive release mode. SET (SYSCR1).7 } Starts STOP mode Low (I, 1111011101010111B ;_IL11, 7, 5, 3<-0 (clears interrupt latches) SINTS : RETI STOP pin \\ fj 1H \\ Hi t i XOUT pin | CAAT NORMAL sToP 1 i NORMAL operation —™ Ay operation ~ Ni Warm-up . operation Confirm by program that the STOP mode is released by the hardware. STOP eo prputls low and Always released if the STOP start STOP mode. pin inputis high Figure 1-16. Level-sensitive Release Mode Note1: After warm-up start, even if STOP pin input is low again, STOP mode does not restart. Note2: When changing to the level-sensitive release mode from the edge-sensitive release mode, the release mode is not switched until a rising edge of the STOP pin input is detected. 3-71-19

TOSHIBA TMP87CM71/N71/P71/S71 b. Edge-sensitive release mode (RELM = 0) In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in applications where a relatively short program is executed repeatedly at periodic intervals. This periodic signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high. Example: Starting STOP mode operation in the edge-sensitive release mode LD (SYSCR1), 00000000B ; OUTEN < 0 (specifies high-impedance) DI ; IMF <0 (disables interrupt service) SET (SYSCR1). STOP ; STOP <1 (activates stop mode) (clears interrupt latches) El ; IMF <1 (enables interrupt service) i V STOP pin | Vig yn i i NORMAL H STOP \\ 7 H H STOP __ operation operation ah. Wermup =i ORMAL operation operation STOP mode started by the program. STOP mode is released by the hardware at the rising edge of STOP pin input. Figure 1-17. Edge-sensitive Release Mode STOP mode is released by the following sequence: ® When returning to NORMAL 2, both the high-frequency and low-frequency clock oscillators are turned on ; when returning to SLOW mode, only the low-frequency clock oscillator is turned on. When returning to NORMAL 1, only the high-frequency clock oscillator is turned on. @ Awarming-up period is inserted to allow oscillation time to stabilize. During warm-up, all internal operations remain halted. Two different warming-up times can be selected with WUT ( bits 2 and 3 in SYSCR1) as determined by the resonator characteristics. @ When the warming-up time has elapsed, normal operation resumes with the instruction following the STOP mode start instruction (e.g. [SET (SYSCR1). 7]). The start is made after the divider of the timing generator is cleared to “0”. Table 1-1. Warming-up Time Example 3x2'/fe [s] 375 [ms] 196.6 [ms] 3x2°/fs [s] 750 [ms] 2" / fc 125 65.5 2° /fs 250 Note: The warming-up time is obtained by dividing the basic clock by the divider: therefore, the warming-up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when STOP mode is released. Thus, the warming-up time must be considered an approximate value. STOP mode can also be released by setting the RESET pin low, which immediately performs the normal reset operation. In this case, even if the setting is to return to the SLOW mode, it starts from the NORMAL mode. (If the initial XTEN of 87CM71/N71/P71/S71 are set to “1” by mask option, they start from the NORMAL2 mode. In case of 87PP71/PS71, starts from NORMAL1 mode.) 3-71-20

TOSHIBA TMP87CM71/N71/P71/S71 5 : ° 9 < «| [8 g 9 + & + 7 oO . g s| |e = a 2g & a g | 3 i 2/18 5 #/s a C4 a « s |e & S| 32 & “13 & \\ : N 8 N ~ S Q| 8 \\ 3-71-21

TOSHIBA TMP87CM71/N71/P71/S71 Note: When STOP mode is released with a low hold voltage, the following cautions must be observed. The power supply voltage must be at the operating voltage level before releasing the STOP mode. The RESET pin input must also be high, rising together with the power supply voltage. In this case, if an external time constant circuit has been connected, the RESET pin input voltage will increase at a slower rate than the power supply voltage. At this time, there is a danger that a reset may occur if input voltage level of the RESET pin drops below the non-inverting high-level input voltage (hysteresis input). (2) IDLE mode (IDLE1, IDLE2, SLEEP) IDLE mode is controlled by the system control register 2 and maskable interrupts. The following status is VY maintained during IDLE mode. [Senate mode] IDLE mode @® Operation of the CPU and watchdog timer is by instruction halted. The on-chip peripherals continue to operate. @ The data memory, CPU registers and port output latches are all held in the status in . Yes effect before IDLE mode was entered. Reset @ The program counter holds the address of No (high) the instruction following the instruction which started IDLE mode. te Example: Starting IDLE mode. ( Noemal ) Yes seT (SYSCR2). 4 > IDLER release mode lo IDLE mode includes a normal release mode and an <> interrupt release mode. Selection is made with the Yes f interrupt master enable flag (IMF). Releasing the IDLE Alnterrupt release mode) mode returns from IDLE1 to NORMAL1, from IDLE2 to NORMALZ, and from SLEEP to SLOW mode. a. Normal release mode (IMF = “0") IDLE mode is released by any interrupt source the IDLE mode start enabled by the individual interrupt enable flag instruction (EF) or an external interrupt 0 (INTO pin) request. Execution resumes with the instruction following Y the IDLE mode start instruction (e.g. [SET Figure 1-19. IDLE Mode (SYSCR2).4]). The interrupt latch (IL) of the interrupt source for releasing the IDLE mode must be cleared to “0” by load instruction. b. Interrupt release mode (IMF = “1") IDLE mode is released and interrupt processing is started by any interrupt source enabled with the individual interrupt enable flag (EF) or an external interrupt 0 (INTO pin) request. After the interrupt is processed, the execution resumes from the instruction following the instruction which started IDLE mode. IDLE mode can also be released by setting the RESET pin low, which immediately performs the reset operation. After reset, the 87CM71/N71/P71/S71 are placed in NORMAL mode. The 87PP71/PS71 are placed in NORMAL! mode after reset release. Note: When a watchdog timer interrupt is generated immediately before IDLE mode is started, the watchdog timer interrupt will be processed but IDLE mode will not be started. 3-71-22

TOSHIBA TMP87CM71/N71/P71/S71 3g s ? 3 4 | ot. 8 ir Py g 3 3 5 Ey £ $ 3% 3 8 E 5 5 g € Bd & x] Ys 2 g Fa a) 1s 3 = a E ¥ 4 § . a g 2 Toy 2 s 5 4 & id & od eel a g bd g ® S 2 3 5 = 2 Fry iz a ° 3 = 3 Sg gz] = 2 g 8 ev g Fa 83 * a g o © o $ 3 2% £ a3 oy E 5 4 sport poo 8 --}----]P}---}---S4 £8 ° ® =| ° e¢ Se 2 bc g 4 Sec 2 Be, 28 3 B &, 25 8 ®, &, 28 8 eee & 5 28 BE age 2 5 8S be Bes $393 38 & S83 ef 23 25 SE SES EF Es 25 SE SSS EF Es 23 Sk 3-71-23

TOSHIBA TMP87CM71/N71/P71/S71 (3) SLOW mode SLOW mode is controlled by the system control register 2 and the timer/counter 2. a. Switching from NORMAL2 mode to SLOW mode First, set SYSCK (bit 5 in SYSCR2) to switch the main system clock to the low-frequency clock. Next, clear XEN (bit 7 in SYSCR2) to turn off high-frequency oscillation. Note : The high frequency clock can be continued oscillation in order to return to NORMAL2 mode from SLOW mode quickly. Always turn off oscillation of high frequency clock when switching from SLOW mode to STOP mode. When the low-frequency clock oscillation is unstable, wait until oscillation stabilizes before performing the above operations. The timer/counter 2 (TC2) can conveniently be used to confirm that low-frequency clock oscillation has stabilized. Example1 : Switching from NORMAL2 mode to SLOW mode. SET (SYSCR2) . 5 ; SYSCK@1 (Switches the main system clock to the low-frequency clock) CLR (SYSCR2).7 ; XENCO (turns off high-frequency oscillation) Example2 : Switching to SLOW mode after low-frequency clock oscillation has stabilized. LD (TC2CR), 14H ; Sets TC2 mode (timer mode, source clock : fs) Low (TREG2), 8000H ; Sets warming-up time (according to Xtal characteristics) SET (EIRH). EF14 ; Enable INTTC2 rm) (TC2CR), 34H j Starts TC2 PINTTC2: LD (TC2CR), 10H ; Stops TC2 SET (SYSCR2).5 ; SYSCKA1 CLR (SYSCR2) . 7 3 XENCAO RETI VINTTC2 : Dw PINTTC2 ; INTTC2 vector table b. Switching from SLOW mode to NORMAL2 mode First, set XEN (bit 7 in SYSCR2) to turn on the high-frequency oscillation. When time for stabilization (warm-up) has been taken by the timer/counter 2 (TC2), clear SYSCK (bit 5 in SYSCR2) to switch the main system clock to the high-frequency clock. Note1: After the SYSCK is cleared to “0”, the CPU core operate using low frequency clock when the main system clock is switching from low frequency clock to high frequency clock. Note2: SLOW mode can also be released by setting the RESET pin low, which immediately performs the reset operation. After reset, the 87CM71/N71/P71/S71 are placed in NORMAL2 mode. (The PP71/PS71 are placed in NORMAL! mode) 3-71-24

TOSHIBA TMP87CM71/N71/P71/S71 Example: Switching from SLOW mode to NORMAL2 mode (fc = 8 MHz, warming-up time is about 7.9 ms). SET (SYSCR2).7 ; XEN@1 (turns on high-frequency oscillation) rh) (TC2CR), 10H ; Sets TC2 mode (timer mode, source clock: fc) ia) (TREG2 +1), OFBH — ; Sets the warming-up time (according to frequency and resonator characteristics) SET (EIRN). EF14 ; Enable INTTC2 LD (TC2CR), 30H ; Starts TC2 PINTTC2: ra) (TC2CR), 10H ; Stops TC2 cLR (SYSCR2).5 ; SYSCK-O (Switches the main system clock to the high-frequency clcok) RETI VINTTC2: DW PINTTC2 ; INTTC2 vector table 3-71-25

TOSHIBA TMP87CM71/N71/P71/S71 3 4 = 3 re = =| < : E BC E eS (ies =| ' = = ' = = i = = : E| 8 =| i 4 3 | 1 — [e} =| i = = 4 i | 3 [=] H = 2 =| ; = 2 =| { =| sd = ' = 2|z | ! = $| 5 = io = 2| 3 = os = z| FS 2 t—| S| @ =| s 2 = 2/16 = 8 = $|2 = y) 2 2 = | 2 2 8 | oe} =| os} 5 3) a = 1 oa = 41 |_| 8 = a|s = ; & =| = = ! = = | ' = a = = % = \\ = v = H = Fi | ! [4 a = ! | = al | = = af = n = a] | a 5 =] elt SE ee ee ee a] ena = =| gy 2 3 = = F Bl IE | = a a = > Se 68 > Se 6 g§ ge =F & § ec we 8 Sax gexsex 5 2 33 Sexsexeoy § 2 23 3-71-26

TOSHIBA TMP87CM71/N71/P71/S71

1.9 Interrupt Controller

The 87CM71/N71/P71/S71 each have a total of 14 interrupt sources: 5 externals and 9 internals. Nested interrupt control with priorities is also possible. Two of the internal sources are pseudo non-maskable interrupts; the remainder are all maskable interrupts. Interrupt latches (IL) that hold the interrupt requests are provided for interrupt sources. Each interrupt vector is independent. The interrupt latch is set to “1” when an interrupt request is generated and requests the CPU to accept the interrupt. The acceptance of maskable interrupts can be selectively enabled and disabled by the program using the interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). When two or more interrupts are generated simultaneously, the interrupt is accepted in the highest priority order as determined by the hardware. Figure 1-22 shows the interrupt controller. Table 1-2. Interrupt Sources . Interrupt Vector Table , Interrupt Source Enable Condition Latch ‘Address | Priority PERRY [ewes —*die | tes | h ] Feseat|io—(xenainerunto)——wrasunoever [us [rm [3 | Fiera frig csbrerinerupa) dwretawt [ae | rm [| Feat [ti Geratinerpt2y _|iwres=r | ays | mm [| Fiera [NTT Cine tae Tinerinrond—|awrets=r | ae | rm [| Fiera [rs @bresinerund _|awreeger | ay | re, [| inert [nto Gelivercenerapd [wwe [ty | rec || Finer [wrest Tvinwrap rte | tio | rem | 10 | Fine [nee esaninterapd) ——_—iwrcehast [tw | ot |_| a Pinerar [res satreaemapd ———dietuet [tw |e [| [erat [nis eteratinerapts) ——_[iwrcerset [tos | at | tow | (1) Interrupt Latches (IL 15 to 2) Interrupt latches are provided for each source, except for a software interrupt. The latch is set to “1” when an interrupt request is generated, and requests the CPU to accept the interrupt. The latch is cleared to “0” just after the interrupt is accepted. All interrupt latches are initialized to “0” during reset. The interrupt latches are assigned to addresses 003Cy and 003Dy in the SFR. Each latch can be cleared to “0” individually by an instruction; however, the read-modify-write instruction such as bit manipulation or operation instructions cannot be used (Do not clear the IL2 for a watchdog timer interrupt to “0”). Thus, interrupt requests can be canceled and initialized by the program. Note that interrupt latches cannot be set to “1” by any instruction. The contents of interrupt latches can be read out by an instruction. Therefore, testing interrupt requests by software is possible. Example 1 : Clears interrupt latches Low (IL), 1110100000111111B jlLy2, ILyo~ILge-O 3-71-27

TOSHIBA TMP87CM71/N71/P71/S71 ; if et p g 2 ge #8 © gf 88324 Alo OTo foe ois fois iol i ls — ec a CS a ele [8 CSE tH fg]? 2 2 |g tee 8} 3 8

5 HEH |e |S

Be Wee fee re ree eerie ei z BERGER REEARE | } lx “Le “Ile «Ile =} Le «Ile <JLe <jiLe = Le =I Le =JiLe = J) Le =IiLe =IiLe © a lesllccl calle leal calles les alan eats HE Se te nee i e. Aa Cee ee ie eee us is EERE EEErS | tt tt = A A SS SS Ss SO UF Cre a Oe a A A ai [fs 8 2 a a LC SU B-4 A\\ AA A A A = ae 8 2 ¢ oe «6S a 3 3-71-28

TOSHIBA TMP87CM71/N71/P71/S71 Example 2 : Reads interrupt latches LD WA, (IL) 7 Wetly, ACILL Example 3: Tests an interrupt latch TEST (IL).7 ; if lL7=1 then jump JR F, SSET (2) Interrupt Enable Register (EIR) The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the pseudo non-maskable interrupts (software and watchdog timer interrupts). Pseudo non-maskable interrupts are accepted regardless of the contents of the EIR; however, the pseudo non-maskable interrupts cannot be nested more than once at the same time. For example, the watchdog timer interrupt is not accepted during the software interrupt service. The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). This register is assigned to addresses 003A} and 003By in the SFR, and can be read and written by an instruction (including read-modify-write instructions such as bit manipulation instructions). © Interrupt Master enable Flag (IMF) The interrupt master enable flag (IMF) enables and disables the acceptance of all interrupts, except for pseudo non-maskable interrupts. Clearing this flag to “0” disables the acceptance of all maskable interrupts. Setting to “1” enables the acceptance of interrupts. When an interrupt is accepted, this flag is cleared to “0” to temporarily disable the acceptance of maskable interrupts. After execution of the interrupt service program, this flag is set to “1” by the maskable interrupt return instruction [RETI] to again enable the acceptance of interrupts. If an interrupt request has already been occurred, interrupt service starts immediately after execution of the [RETI] instruction. Pseudo non-maskable interrupts are returned by the [RETN] instruction. In this case, the IMF is set to “1” only when pseudo non-maskable interrupt service is started with interrupt acceptance enabled (IMF = 1). Note that the IMF remains “0” when cleared in the interrupt service program. The IMF is assigned to bit 0 at address 003Ay in the SFR, and can be read and written by an instruction. The IMF is normally set and cleared by the [El] and [DI] instructions, and the IMF is initialized to “0” during reset. Note: Donotset IMF to “1”during non-maskable interrupt service programs. @ Individual interrupt Enable Flags (EF15 to EF4) These flags enable and disable the acceptance of individual maskable interrupts, except for an external interrupt 0. Setting the corresponding bit of an individual interrupt enable flag to “1” enables acceptance of an interrupt, setting the bit to “0” disables acceptance. Example 1 : Sets EF for individual interrupt enable, and sets IMF to “1”. Low (EIR), 1110100010100001B);_—- EF,s~EF;3, EF11, EF7, EFs, IMFe-1 Example 2 : Sets an individual interrupt enable flag to “1”. SET (EIRH).4 ¢ EFi2e1 15 14 13 12 WW 10 9 8 7 6 5 4 3 2 1 0 (ooac'Go3p,) Citas | tae | ag Wag Phy | ig | We Te Py Fig Ts ke Fg J ths (0080) iia value + 60000000, 00000 (coast ban ars rT A 7 Vcr (Initial Value: 00000000 0000+**0) Note1: Do not use any read-modify-write instruction such as bit manipulation for clearing IL. Note2: Do not clear IL2 to “0” by an instruction. Note3: Do not set IMF to 1” during non-maskable interrupt service program. Figure 1-23. Interrupt Latch (IL) and Interrupt Enable Register (EIR) 3-71-29

TOSHIBA TMP87CM71/N71/P71/S71

1.9.1 Interrupt Sequence

An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to “0” by a reset or an instruction. Interrupt acceptance sequence requires 8 machine cycles (4 1s @ fc = 8 MHz in the NORMAL mode) after the completion of the current instruction execution. The interrupt service task terminates upon execution of an interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for pseudo non-maskable interrupts). (1) Interrupt acceptance processing @® The interrupt master enable flag (IMF) is cleared to “0” to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled. @ The interrupt latch (IL) for the interrupt source accepted is cleared to “0”. @ The contents of the program counter (return address) and the program status word are saved (pushed) on the stack. The contents of Stack Pointer is decreased by 3. @ The entry address of the interrupt service program is read from the vector table, and the entry address is loaded to the program counter. © The instruction stored at the entry address of the interrupt service program is executed. Interrupt service task 1 machine cycle be-—_____tiemupt service task _yy ee Os DO Interrupt | ! ' signal H Al i i H

7 H H H

4 ' : t it i ' i 1 <n i t oT re XEN EXE XFS br : XX SFX) 2 Notel: a; return address, b ; entry address, c ; address which the RETI instruction is stored Note2: The maximum response time from when an IL is set until an interrupt acceptance processing starts is 38/fc or 38/fs [s]. (fm = fc or fs) Figure 1-24. Timing Chart of Interrupt Acceptance and Interrupt Return Instruction Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt service program. Vector table address Entry address vt, [OR 203, {oR FFF3y D2y D204, | 06, A maskable interrupt is not accepted until the IMF is set to “1” even if a maskable interrupt of higher priority than that of the current interrupt being serviced. When nested interrupt service is necessary, the IMF is set to “1” in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. However, an acceptance of external interrupt 0 cannot be disabled by the EF; therefore, if disablement is necessary, either the external interrupt function of the INTO pin must be disabled with the INTOEN in the external interrupt control register (EINTCR) or interrupt processing must be avoided by the program. When INTOEN =0, the interrupt latch IL3 is not set, therefore, the falling edge of the INTO pin input cannot be detected. 3-71-30

TOSHIBA TMP87CM71/N71/P71/S71 Example 1 : Disables an external interrupt 0 using INTOEN rn) (EINTCR), 000000008 ;_ INTOENe-O Example 2 : Disables the processing of external interrupt 0 under the software control (using bit 0 at address OOFO as the interrupt processing disable switch) PINTO: TEST (00FOH) .0 ; Return without interrupt processing if (00FO}4)o = 1 IRS T, SINTO RETI SINTO: interrupt processing, : RETI VINTO : Dw PINTO (2) General Purpose register save / restore processing During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but not the accumulator and other registers. These registers are saved by the program if necessary. Also, when nesting multiple interrupt services, it is necessary to avoid using the same data memory area for saving registers. The following method is used to save/restore the general-purpose registers: @® General-purpose register save/restore by register bank changeover: The general-purpose registers can be saved at high-speed by switching to a register bank that is not in use. Normally, bank 0 is used for the main task and banks 1 to 15 are assigned to interrupt service tasks. To increase the efficiency of data memory utilization, the same bank is assigned for interrupt sources which are not nested. The switched bank is automatically restored by executing an interrupt return instruction [RETI] or [RETN]. Therefore, it is not necessary for a program to save the RBS. Example: Register Bank Changeover PINTxx : LD RBS) ; Switches to bank n (1 4s at 8 MHz) RETI ; Restores bank and Returns main task main task acceptance of interrupt acceptance of interrupt bank m interrupt service task interrupt service task WRIA Switch to bank n by \\ \\ saving [LD RBS, n] or registers time [INC (GRBS) ] os eee restore bank | m interrupt return automatically by \\X restoring (RETI]/[RETN] \\ registers instruction eee S interrupt return (a) Saving/Restoring by register bank changeover (b). Saving/Restoring using push/pop or data transfer instructions Figure 1-25. Saving/Restoring General-purpose Registers ® General-purpose register save/restore using push and pop instructions: To save only a specific register, and when the same interrupt source occurs more than once, the general-purpose registers can be saved/restored using push/pop instructions. 3-71-31

TOSHIBA TMP87CM71/N71/P71/S71 Example: Register save using push and pop instructions PINTxx = PUSH WA ; Save WA register pair POP WA ; Restore WA register pair RETI 3 Return ee eesseeeeeeessnee sesseeneeeeee sesssssssessese| Address (example) sp | 063Ay A 063B Pe ee sp foe prsmemnne e PC, PC, PC, 063D PCy PCy PCy 063E enh ae 2 PSW PSM SPRY 068 At acceptance Atexecution At execution At execution of an ofaninterrupt ) ofapush = ofapop ) interrupt return instruction instruction instruction @ General-purpose registers save/restore using data transfer instructions: Data transfer instructions can be used to save only a specific general-purpose register during processing of a single interrupt. Example: Saving/restoring a register using data transfer instructions PINTxx : LD. AGSAVA), A ; Save A register interrupt processing : LD A, (GSAVA) ; Restore A register RETI ; Return from interrupt service The interrupt return instructions [RETI] / [RETN] perform the following operations. [RETI] Maskable interrupt return [RETN] Non-maskable interrupt return @ The contents of the program counter and the |( The contents of the program counter and program status word are restored from the program status word are restored from the stack. stack. @ The stack pointer is incremented 3 times. @® The stack pointer is incremented 3 times. @ The interrupt master enable flag is set to "1" @ The interrupt master enable flag is set to “1” only when a non-maskable interrupt is accepted in interrupt enable status. However, the interrupt master enable flag remains at “0” when so clear by an interrupt service program Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed. Note: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. 3-71-32

TOSHIBA TMP87CM71/N71/P71/S71

1.9.2 External Interrupts

The 87CM71/N71/P71/S71 each have five external interrupt inputs (INTO, INT1, INT2, INT3, and TNTS). Three of these are equipped with digital noise rejection circuits (pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with INT1, INT2 and INT3. The INTO/P10 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset. Edge selection, noise rejection control and INTO/P10 pin function selection are performed by the external interrupt control register (EINTCR). When INTOEN =0, the IL3 will not be set even if the falling edge of INTO pin input is detected. Table 1-3. External Interrupts [source [ein [sine | enableconditions | tage | digtalncisereiecion Pulses of less than 15/fc or 63/fc [s] . are eliminated as noise. Pulses INT1 INT1 P11 IMF + EFs=1 fallingedge | equal to or more than 48/f¢ [3] or or 192/fc [s] are regarded as signals. rising edge INT2 INT2 Pr2iTct IMF EF7=1 eliminated as noise. Pulses of equal Note 1: The noise rejection function is turned off in SLOW and SLEEP modes. Also, the noise reject times are not constant for pulses input while transiting between operating modes (NORMAL2@SLOW) Note2: The noise rejection function is also affected for timer/counter input (TC1 and TC3 pins). Note3: The pulse width (both “H” and “L” level) for input to the INTO and INTS pins must be over 1 machine cycle. INTO/INTS input l J tint tintH > teye (Note: tcyc= 4/fm[s]) <_< ‘tnTL ‘NTH : Note4: If a noiseless signal is input to the external interrupt pin in the NORMAL 1/2 or IDLE 1/2 mode, the maximum time from the edge of input signal until the IL is set is as follows : © INT1 pin 49/fc [s] (INTINC=1), 193/fc [s] (INTINC=0) ® INT2,INT3 pins 25/fc [s] Note 5: When INTOEN =O, interrupt latch IL3 is not set even if a falling edge is detected for INTO pin input. Note 6: When high-impedance is specified for port output in stop mode, port input is forcibly fixed to low level internally. Thus, interrupt latches of external interrupt inputs except INTS (P20/STOP) which are also used as ports may be set to “1”. To specify high-impedance for port output in stop mode, first disable interrupt service (IMF =0) , activate stop mode. After releasing stop mode, clear interrupt latches using load instruction, then, enable interrupt service. Example : Activating stop mode LD (SYSCR1), 010000008 ; OUTEN <0 (SOECUFUES HIGH-IMPEDANCE) DI ; IMF <0 (disabkes ubterryot servuce) SET — (SYSCR1). STOP ; STOP <1 (activates stop mode) LOW (IL), 11110111010101118 ; IL11,7,5, 30 (clears interrupt lateges) El IMF <1 (ebables interrupt service) 3-71-33

TOSHIBA TMP87CM71/N71/P71/S71 7 6 5 4 3 2 1 0 lect th 0 : Pulses of less than 63/fc [s] are eliminated as noise ANTO oj - 0 : P10 input/output port INT3 ES. . ony INT2ES | INT3 to INT1 edge select 0 : Rising edge INT1 ES 1: Falling edge Note1: fc ; High-frequency clock[Hz] * ; don't care Note2: — Edge detection during switching edge selection is invalid. Note3: Do not change EINTCR when IMF =1. After changing EINTCR, interrupt latches of external interrupt inputs must be cleared to “0” using load instruction. Note4: — Inorder to change of external interrupt input by rewriting the contents of INT2ES and INT3ES during NORMAL1/2 mode, clear interrupt latches of external interrupt inputs (INT2 and INT3) after 8 machine cycles from the time of rewriting. During SLOW mode, 3 machine cycles are required. Note5: — Inorder to change an edge of timer counter input by rewriting the contents of INT2ES and INT3ES during NORMAL1/2 mode, rewrite the contents after timer counter is stopped (TC*s = 0), that is, interrupt disable state. Then, clear interrupt laches of external interrupt inputs (INT2 and INT3) after 8 machine cycles from the time of rewriting to change to interrupt enable state. Finally, state timer counter. During SLOW mode, 3 machine cycles are required. Example: When changing TC1 pin inputs edge in external trigger timer mode from rising edge to falling edge. LD (TC1CR),01001000B =; +TC1S<-00 (stop TC1) DI ; IMF < 0 (disable interrupt service) LD (EINTCR),00000100B ; INT2ES <1 (change edge selection) t NOP “Smachine — to cycles. NOP

1 LD (ILL),01111111B ; IL7€0 (clear interrupt latch)

EI ; IMF <1 (enable interrupt service) LD (TC1CR) ,01111000B ; TCLS —11 (start TC1) Note6: — If changing the contents of INT1ES during NORMAL1/2 mode, interrupt latch of external interrupt input INT1 must be cleared after 14 machine cycles (when INT1NC = 1) or 50 machine cycles (when INT1NC =0) from the time of changing. During SLOW mode, 3 machine cycles are required. Figure 1-26. External Interrupt Control Register 3-71-34

TOSHIBA TMP87CM71/N71/P71/S71

1.9.3 Software Interrupt (INTSW)

Executing the [SWI] instruction generates a software interrupt and immediately starts interrupt processing (INTSW is highest prioritized interrupt). However, if processing of a non-maskable interrupt is already underway, executing the SWI instruction will not generate a software interrupt but will result in the same operation as the [NOP] instruction. Thus, the [SWI] instruction behaves like the [NOP] instruction. Note : Software interrupt generates during non-maskable interrupt processing to use SWI instruction for software break in a development tool. Use the [SWI] instruction only for detection of the address error or for debugging. ® Address Error Detection FFy is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent memory address. Code FFy is the SWI instruction, so a software interrupt is generated and an address error is detected. The address error detection range can be further expanded by writing FFy to unused areas of the program memory. the address trap reset is generated in case that an instruction is fetched from RAM or SFR areas. Note: The fetch data from addresses 3F80} to 3FFF} (test ROM area) is not “FF”. @® Debugging Debugging efficiency can be increased by placing the SWI instruction at the software break point setting address. 3-71-35

TOSHIBA TMP87CM71/N71/P71/S71

1.10 Watchdog Timer (WDT)

The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either as a reset output or a non- maskable interrupt request. However, selection is possible only once after reset. At first, the reset output is selected. When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals.

1.10.1 Watchdog Timer Configuration

MPX reset release signal from T.G. fe/2? or fs/2'° ——>|A Binary Counters fo/ 2" or fs/2°——>|B | clock overflow reset fc/2" or fs/2"" ——>|C _ Y [) WDT output output fc/2” or 3/23 ——> ° clear [| >) >—Direset 2 (\\ ID interrupt request INTWDT internal reset pL_ enable fa writing writing clear WpToUT wor tT | disable code_|code wore] | was] | Watchdog Timer Control Registers Figure 1-27. Watchdog Timer Configuration

1.10.2 Watchdog Timer Control

Figure 1-28 shows the watchdog timer control registers (WDTCR1, WDTCR2). The watchdog timer is automatically enabled after reset. (1) Malfunction detection methods using the watchdog timer The CPU malfunction is detected as follows: @® Setting the detection time, selecting output, and clearing the binary counter. @ Repeatedly clearing the binary counter within the setting detection time. If a CPU malfunction occurs for any cause, the watchdog timer output will become active on the rise of an overflow from the binary counters unless the binary counters are cleared. At this time, when WDTOUT = 1 a reset is generated, which drives the RESET pin low to reset the internal hardware and the external circuits. When WDTOUT =0, a watchdog timer interrupt (INTWDT) is generated. The watchdog timer temporarily stops counting in STOP mode (including warm-up) or IDLE mode, and automatically restarts (continues counting) when STOP/IDLE mode is released. 3-71-36

TOSHIBA TMP87CM71/N71/P71/S71 Example: Sets the watchdog timer detection time to 221/fc [s] and resets the CPU malfunction. LD (WDTCR2), 4EH ; Clears the binary counters LD (WDTCR1), 000011018; WDTT<-10, WDTOUT<1 LD (WOTCR2), 4EH ; Clears the binary counters Within 3/4 of WOT i (always clear immediately after changing WDTT) detection time i LD (WDTCR2), 4EH ; Clears the binary counters Within 3/4 of WOT i detection time : ra) (WDTCR2), 4EH ; Clears the binary counters Watchdog Timer Control Register 1 7 6 5 4 3 2 1 t) woten | Watchdog timer 0 : Disable (itis necessary to write the disable code to WDTCR2) enable/disable 1: Enable 00:2%/fc or 2'7/fs [s] Watchdog timer 01:28/fe or — 2'°/fs write WOTT | detection time 10: 2°/fc or — 2"/fs only 11:2%/fe or — 2"/fs Watchdog timer 0 : Interrupt request WOTOUT | output select 1: Reset output Note 1 : WDTOUT cannot be set to “1” by program after clearing WOTOUT to "0". Note2: fe ; High-frequency clock [Hz] fs ; Low-frequency clock [Hz] * ; don’t care Note3 : WDTCR1 isa write-only register and must not be used with any of the read-modify-write instructions. Note4: Disable the watchdog timer or clear the counter just before switching to STOP mode. When the counter is cleared just before switching to STOP mode, clear the counter again subsequently to releasing STOP mode. Watchdog Timer Control Register 2 7.6 5S 4 3 2 1 0 (0035u) nitial value : | 4E, : Watchdog timer binary counter clear (clear code) Watchdog timer control : " write WOTCR2 | code write register Bi, : Watchdog timer disable (disable code) only others : Invalid Note! : The disable code is invalid unless written when WDTEN =0. Note2 : *;don’tcare Note3: — Since WDTCR2 isa write-only register, read-modify-write instructions (e.g., bit manipulating instructions such as SET or CLR and arithmetic instructions such as AND or OR) cannot be used for read / write to this register. Note4: — To clear binary counter doesn’t initialize the source clock, therefore, it is recommended to clear binary counter within 3/4 of the detection period. Figure 1-28. Watchdog Timer Control Registers Table 1-4. Watchdog Timer Detection Time At fs= 32.768 kHe 2 1c [s]_ | 2° /fc, 27 / fs 2" / fs 4.1945 4s 23 /fc 2 /fe, 2°/ 45 2° /f5 1.048 s 1s 2 /fc 2 /fe, 29/5 — 262.1 ms 250 ms 2° /fc 2° / fc, 2" 45 — 65.5 ms 62.5 ms 3-71-37

TOSHIBA TMP87CM71/N71/P71/S71 (2) Watchdog Timer Enable The watchdog timer is enabled by setting WDTEN (bit 3 in WDTCR1) to “1”. WDTEN is initialized to “1" during reset, so the watchdog timer operates immediately after reset is released. Example : Enables watchdog timer LD (WDTCR1), 00001000B ; WDTEN@1 (3) Watchdog Timer Disable The watchdog timer is disabled by writing the disable code (B1}) to WDTCR2 after clearing WDTEN (bit 3 in WDTCR1) to “0”. The watchdog timer is not disabled if this procedure is reversed and the disable code is written to WDTCR2 before WDTEN is cleared to “0”. The watchdog timer is halted temporarily in STOP mode (including warm-up) and IDLE mode, and restarts automaticallyafter STOP or IDLE mode is released. During disabling the watchdog timer, the binary counters are cleared. Example : Disables watchdog timer Low (WDTCR1), 0B101H ; WDTEN€@0, WDTCR2 disable code

1.10.3 Watchdog Timer Interrupt (INTWDT)

This is a pseudo non-maskable interrupt which can be accepted regardless of the contents of the EIR. Ifa watchdog timer interrupt or a software interrupt is already accepted, however, the new watchdog timer interrupt waits until the previous interrupt processing is completed (the end of the [RETN] instruction execution). The stack pointer (SP) should be initialized before using the watchdog timer output as an interrupt source with WDTOUT. Example : Watchdog timer interrupt setting up. LD SP, 063FH ; Sets the stack pointer rn) (WDTCR1) , 000010008 ; WDTOUTO

1.10.4 Watchdog Timer Reset

If the watchdog timer output becomes active, a reset is generated, which drives the RESET pin (sink open drain output) low to reset the internal hardware and the external circuits. The reset output time is 220/fc [s] (131 ms at fc = 8 MHz). The high-frequency clock oscillator also turns on when a watchdog timer reset is generated in SLOW mode. Note : The high-frequency clock oscillator also turns on when a watchdog timer reset is generated in SLOW mode. Thus, the reset output time is 220/fc. The reset output time include a certain amount of error if there is any fluctuation of the oscillation frequency when the high-frequency clock oscillator turns on. Thus, the reset, the reset output time must be considered approximate value. : 2c Is] : Bo 2c: i —— : Clock | l l \\WDTT = 118) Binary counter 1X2 X3X 9 X 1 XK 2 X 3 XX 9 Overflow i INTWOT interrupt : WoTresetoutput rr Cr TD TTT TT ee output) writes 4E,, to WDTCR2 Figure 1-29. Watchdog Timer Interrupt / Reset 3-71-38

TOSHIBA TMP87CM71/N71/P71/S71

1.11 Reset Circuit

The 87CM71/N71/P71/S71 each have four types of reset generation procedures: an external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Table 1-5 shows on-chip hardware initialization by reset action. The internal source reset circuit (watchdog timer reset, address trap reset, and system clock reset) is not initialized when power is turned on. Thus, output from the RESET pin may go low (22%/fc [s] (131 ms at 8 MHz) ) when power is turned on. Table 1-5. Initializing Internal Status by Reset Action Register bank selector (RBS) 0 Interrupt individual enable flags (EF) 0 Teh not

1.11.1 External Reset Input

When the RESET pin is held at low for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the a operating voltage range and oscillation stable, a reset is VDD ' vob applied and the internal state is initialized. RESET ' typ. 220k When the RESET pin input goes high, the reset operation is released and the program execution starts at the vector * H address stored at addresses FFFEy - FFFFH. 7 te The RESET pin contains a Schmitt trigger (hysteresis) with an internal pull-up resistor. A simple power-on-reset can Figure 1-30. Simple Power-on- be applied by connecting an external capacitor and a Reset Circuitry diode.

1.11.2 Address Trap Reset

If a CPU malfunction occurs and an attempt is made to fetch an instruction from the RAM or the SFR area (addresses 0000}, - 063F}), an address-trap-reset will be generated. Then, the RESET pin output will go low. The reset time is 220/fc [s] (131 ms at 8 MHz). execution i H RESET output Lite output te 2 \\ i i i ' Pe [s] ‘Re! fet ! Mtoe! ! Note1: 05a=063Fy 241 Note2: — During reset release, reset vector “r” is read out, and an instruction at address r is fetched and decoded. Figure 1-31. Address-Trap-Reset

1.11.3 Watchdog Timer Reset

Refer to Section “1.10 Watchdog Timer”.

1.11.4 System-Clock-Reset

Clearing both XEN and XTEN (bits 7 and 6 in SYSCR2) to “0” stops both high-frequency and low- frequency oscillation, and causes the MCU to deadlock. This can be prevented by automatically generating a reset signal whenever XEN = XTEN =0 is detected to continue the oscillation. Then, the RESET pin output goes low from high-impedance. The reset time is 220/fc [s] (131 ms at 8 MHz). 3-71-39

TOSHIBA TMP87CM71/N71/P71/S71 2. ON-CHIP PERIPHERALS FUNCTIONS

2.1 Special Function Registers (SFR) and Data Buffer Registers (DBR)

The TLCS-870 Series uses the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function registers (SFR) and data buffer registers (DBR). The SFR are mapped to addresses 0000} - 003Fy, and the DBR to addresses OF80q — OFFFH. Figure 2-1 shows the 87CM71/N71/P71/S71 SFRs and DBRs. Address Read Write Address Read Write 0000, PO port 00204 [siosR (si0 status) SIOCRT 02 Poon ccccccseeeeeeeeennenttenn sn ee fOr ce cose 22 Pann cccseneeseeeeeeennneseesess f@SOUEG oo ceecsnnssnnnsnsnennneney 03 Pann cccccsccceeeeneneeneens sss POM ccccceeenee en 2B Yo cceceosesssseeseseecceecenseseess fOSOIMEG. os cosesesstseseeeeeessesessneeeee

08 Yee reeeeneere eee E eee REN OR cesses 24 |HSOsR(HsO status) HSOCR(HSO contro)

D5 Pooccccssssceeceeeeenneneneen isnt eC Oet ccesmnnnnnnnnnnnnsssnnsssey 25 Lc cccsssceseeeeeeeennesesenss f@SOIMEG ccnnssnnnsnanennnnnea 06 seseeesennesenseeen POPE. csecses sess , 26 coovsereetecceeecensnsesns rf @SOIMEG oc cceeneeeeeesee coool OF Ya cccccsssssesseenenseseeseeesese eT POT cosets sooo 27 | occcccscseesessesessecsecsensesees st @SOMEG oc occsessteeeeeeeeesensessneeeee 9 Ya eeccccccsssseneeeeeeeseesenesnsnn POM cc ccssosugesmeienteseeseenensensseey 29 |METSRIVET status). cseseesees| METORZeccesessveeecsnsneesesesee DA Yn ccccsseseeeseeeeetTeettnnsssnnesesneseefPOCR POO COMED cc sssee 2A |KEYSR (Key sean status) ss saDeossseeccseeesesesTinsssnnessnsennneney OB accesses Tenseeceeeennseeeef SLERIPLMO control) | 2B Yc cccecsneeceenennneeeee A @SOIVEG oe cssaseeemnnenneeennsns oc eseeeeseeetnee snssefPACR (PA contro) 7 2c eeccnseecnseeerseereneeseof QSOS, a ccecesseeeenee seve OD Yon c cc ccceesseceeteesneeeeee ss MOSMEG cssscetesseeeeensnnsesee 2D Yee essseceenennseceen A OSOIVEG cccsseeemennnneeeessnt De oon aiceenenel MPR Comemetor neat ered | DE Pc cccsscsecceeceeseeetstensnnss A @SOMEG ee cccscsnnnsanesssnennneney OF ‘CMPDR (Comparator input data register). 2F reserved 10 an [FREG). rimer regi 30 a ‘reserved TT Lc cccssseeeeeeeentreentnnsnes fing mer coer] BT Pac ccccccseceeeeeseeettetensnnns A @SOMEG, cc cceetsmnnnnnnesssneneeeney V2 Yo ccccseeeesenneeeeennneneee fee nc cccseeunnneeeeeessne BZ Yn cccscccetennneeeenennneseee A @SOIVOG cseaeeeemnnnnneeeessnse TB | accsssssseeceeeeesenessnnsssnsn sn eSeMEScccsssteeen seseee , BB Parcsessssesseseeceesessninnssnss sn A@SOMUEG, sssseccsseessnnnnnnnnnanenseseee Vac cccsceee TeceteeestsnnsssssseafUCHERITCH Contrada BA oo cccccccccsee Tosssenemeeseesseesenef WOTERY,, ntrol) === TT eee tesa mer ener | a7 [Pemex dterupt ented VB faa cccceeseceeeeeeeTREGBA (Timer register 3A) casa BBY ecccceccceceen SYSERT costteneeseesenesnsnsse 1A ws |TC3CR(TC3 control) 3A . EIR . ig [ose ea timerregster a) °°") ag Pre nemaptenablregine 4 1c ws |TCACR (TC4 control) 3c 1 : 1D [ened ap PESTS. lnteroraten) TE Ye ceccscecesnnneeeeenneseee fe ccceeeunnneeeeeensn BE Yc ccseceeecnnneecetennneceers ef @SOIVOG,.cccsessnseeemenenneeeeesns 1F reserved 3F LPSW (Program status word RBS (Register bank selector) (a) Special Function Registers Address Read Write OFBOH Lecce coososneeeeseesee Note? : Do not access reserved areas by the program. VET Note2: —- : Cannot be accessed. Display data buffer Note3 : When defining address 003Fy with assembler symbols, use GPSW and GRBS. . Note4 : Write-only registers and interrupt OFOF latches cannot use the read-modify- reserved write instructions (bit manipulation OFFO Fee nn instructions such as SET, CLR, etc. _and an ne sevsnetenssees logical operation instructions such as F2 Joven gig cesseeeenneteee AND, OR, etc.) g Transmit and receive . Note5 : KEYDRisa read-only register. orrg[ = dS transmitdatabutfer | reserved OFFF (b)_ Data Buffer Registers Figure 2-1. SFR & DBR 3-71-40

TOSHIBA TMP87CM71/N71/P71/S71

2.2 W/O Ports

The 87CM71/N71/P71/S71 each have 10 parallel input/output ports (73pins) each as follows: [remeron [Sensors 8-bit /O port Po 8-bit I/O port External interrupt input, timer/counter input, and divider output Port P2 3-bit I/O port Low-frequency resonator connections, external interrupt input, and STOP mode release signal input 8-bit I/O port Serial interface, external interrupt input, and timer/counter input 8-bit I/O port Key scan input and compartor input 6-bit I/O port Compartor input and timer/counter output 8-bit I/O port VFT digit driver output 8-bit I/O port VFT digit driver output 8-bit output port VFT segment driver output or key strobe output 8-bit I/O port VFT segment driver output or key strobe output Ports P1, P2, P3, P4, P5, P6, P7, P8 and P9 can also use secondary function. Each output port contains a latch, which holds the output data. Input ports excluding P4 do not have latches, so the external input data should either be held externally until read or reading should be performed several times before processing. Figure 2-2 shows input/output timing examples. External data is read from an I/O port in the $1 state of the read cycle during execution of the read instruction. This timing can not be recognized from outside, so that transient input such as chattering must be processed by the program. Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O port. fetchcycle fetchcycle read cycle fetchcycle fetchcycle write cycle Instruction ___S0 0 0 _-- Instruction--30 0 0 --- cycle-~ aaa cycle" aad Input strobe =} L.______._Outputlateh.. CL pulse (a) Input Timing (b) Output Timing Note: The positions of the read and write cycles may vary, depending on the instruction. Figure 2-2. Input/Output Timing (Example) When reading an I/O port except programmable I/O ports PO and P1, whether the pin input data or the output latch contents are read depends on the instructions, as shown below: (1) Instructions that read the output latch contents @ XCH r, (sre) ® LD (pp) . b, CF @ CLRISET/CPL (src).b © ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), n @ CLR/SET/CPL (pp).g @ (src) side of ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), (HL) @ (src).b, CF (2) Instructions that read the pin input data ® Instructions other than the above (1) ® (HL) side of ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), (HL) 3-71-41

TOSHIBA TMP87CM71/N71/P71/S71

2.2.1 Port PO (P07 - POO)

Port PO is an 8-bit general-purpose input/output port which can be configured as either an input or an output in one-bit unit under software control. Input/output mode is specified by the corresponding bit in the port PO input/output control register (POCR). Port PO is configured as an input if its corresponding POCR bit is cleared to “0”, and as an output if its corresponding POCR bit is set to “1”. During reset, POCR is initialized to “0”, which configures port PO as input. The PO output latches are also initialized to “0”. Data is written into the output latch regardless of POCR contents. Therefore initial output data should be written into the output latch before setting POCR. Note 1: Ports set to the input mode read the pin states. When input pin and output pin exist in port PO together, the contents of the output latch of ports set to the input mode may be rewritten by executing the bit manipulation instructions. Pins set to the output mode read a value of the output latch. Note2: The POCR is a write-only register. It can not be operated by the read-modify instruction (Bit manipulation instructions of SET, CLR, etc. and Arithmetic instructions of AND, OR, etc.) STOP OUTEN { data output 4 <} data output ——-[p 4] > {| Poi output latch Note : i=7to0 7 6 5 4 3 2 1 ) {0000,9 (initia value + 0000 0000) 7 6 5 4 3 2 1 0 0: input mode write Figure 2-3. Port PO and POCR Example: Setting the upper 4 bits of port PO as an input port and the lower 4 bits as an output port (Initial output data are 10103). LD (PO), 00001010B ; Sets initial data to PO output latches LD (POCR),00001111B ; Sets the port PO input/output mode 3-71-42

TOSHIBA TMP87CM71/N71/P71/S71

2.2.2 Port P1 (P17 - P10)

Port P1 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. Input/output mode is specified by the corresponding bit in the port P1 input/output control register (P1CR). Port P1 is configured as an input if its corresponding P1CR bit is cleared to “0”, and as an output if its corresponding P1CR bit is set to “1”. During reset, P1CR is initialized to “0”, which configures port P1 as an input . The P1 output latches are also initialized to “0”. Data is written into the output latch regardless of P1CR contents. Therfore initial output data should be written into the output latch before setting P1CR. Port P1 is also used as an external interrupt input, a timer/counter input, and a divider output. When used as a secondary function pin, the input pins should be set to the input mode, and the output pins should be set to the output mode and beforehand the output latch should be set to “1”. It is recommended that pins P11 and P12 should be used as external interrupt inputs, timer/counter input, or input ports. The interrupt latch is set on the rising or falling edge of the output when used as output ports. Pin P10 (INTO) can be configured as either an I/O port or an external interrupt input with INTOEN (bit 6 in EINTCR). During reset, the pin P10 (INTO) is configured as an input port P10. Note 1: Ports set to the input mode read the pin states. When input pin and output pin exist in port P1 together, the contents of the output latch of ports set to the input mode may be rewritten by executing the bit manipulation instructions. Pins set to the output mode read a value of the output latch. Note2: The PICR is a write-only register. It can not be operated by the read-modify instruction (Bit manipulation instructions of SET, CLR, etc. and Arithmetic instructions of AND, OR, etc.) STOP OUTEN {_» data input - << data output fd Cy ii output latch control output control input Note : i=7to0 z 6 5 4 2 1 0 Pt P17 : P16: PIS ; P14 : P13: P12: P11 : P10 (00014) i Tez: ‘pvo | ‘NI?! nt1 INTO | (Initial value: 0000 0000) Zz 6 4 2 1 0 picr | /Ocontrol for port P1 0: Input mode write (Set for each bit individually) | _1 : Output mode only Figure 2-4. Port P1 and P1CR Example: Sets P17, P16 and P14 as output ports, P13 and P11 as input ports, and the others as function pins. Internal output data is “1” for the P17 and P14 pins, and “0” for the P16 pin. ra) (EINTCR), 010000008 —_; INTOENe~1 LD (P1), 101111118 ;PI7CA1, P14e-1, P16AO ra) (P1CR), 110100008 3-71-43

TOSHIBA TMP87CM71/N71/P71/S71

2.2.3 Port P2 (P22 - P20)

Port P2 is a 3-bit input/output port. It is also used as an external interrupt] SET/CLR/CPL/others CMP/MCMP/TEST/ others input, and low-frequency crystal |Data input IJ <4 <I connection pins When used as an wont] input port, or the secondary function |,.43 output [| P20 (INTS/STOP) pin, the output latch should be set to |contro} pout [e_| ee U “1". During reset , the output latches |pata input PH are initialized to “1”. LS Osc. enable A low-frequency crystal (32.768 kHz) is iy connected to pins P21 (XTIN) and P22 |>at@ output [el L> ll LJ P21 oxtiny (XTOUT) in the dual-clock mode. In . Data input the single-clock mode, pins P21 and p Let TL] U) 4 P22 can be used as normal » input/output ports. Data output {> 9 > 1 [] P22 (xrour) It is recommended that the P20 pin { ) should be used as an external stop , "| Note 1: * ; don’t care interrupt input, a STOP mode release| OUTEN I> Note 2: XTENis bit 6in signal input, or an input port. If used] yen SYSCR2. as an output port, the interrupt latch] fs <{ isset on the falling edge of the output 7 6 5 4 3 2 1 0 Pulse. ; ; ; p2 i i ; i i P22: p21 :_P20 When a read instruction for port P2 is (0002) | i i E E xrour: xm AS executed, bits 7 to 3 in P2 read in as wa : s 5 £ - sror undefined data. (Initial value: **** *111) 2.2.4 Port P3 (P37 - P30) Figure 2-5. Port P2 Port P3 is an 8-bit input/output port, and is also used as serial interface i « Control input YY input/output, an external interrupt CMP /MCMP/TEST /others} input, and a timer/counter input. Data input <| When used as an input port or a SET/CLR/CPL/others secondary function pin, the output <] latch should be set to “1". The output Data output [oa] [> t> ] P3i latches are initialized to “1" during Output latch reset. c ' t Example 1: Output the immediate data ontrol outpu 5An to the P3 port. STOP 6 Note :i=7too LD (P3), SAH ) PIC SAy OUTEN >, Example 2: Inverts the output of the upper 4bits (P37 - P34) of the 7 6 5 4 3 2 ' } P3 port. XOR —_(P3), 11110000B P3 P37 | P36 | P35 | P34 | P33 | P32; P31 ING : (00034) | HSO : HSCK: SO : Sl | SCK | Tc4 : T¢3 P37~P34e-P37~P34 (Initial value: 1111 1111) Figure 2-6. Port P3 3-71-44

TOSHIBA TMP87CM71/N71/P71/S71 2.2.5Port P4 (P47 - P40) Port P4 is an 8-bit input/output port, and EKEY is also used as a key scan input and a iD Key scan input latch (KEYDR) comparator input. When used as an input <q fo >| port or a secondary function pin, the CMP /MCMP TEST h should be set to “1". The 9 corners output latch sl be set t ~ The Data input I <4 << output latches are initialized to “1 SET/CLR/CPL during reset. < Jothers When used key scan function, all of the Data output fo] > C] pai port P4 bits must be used as key scan Outputlatch epi inputs or comparator inputs. When used STOP Hi-Z control in PCR as both comparator inputs and key scan OUTEN Jd) inputs, the P47 and P46 pins are used as CIN} only comparator inputs. Bits 7 and 6 are read in as “0” when a read instruction is Note :i=7to0, j=5to4 executed for the key scan input latches (KEYDR). Built-in pull-down resistors can also be connected for each bit using the 7 6 5 43 21 0 port P4 control register (refer to section P4 na tte P45 : Pad : P43 : PAZ : PAT ! PaO “2.12.6 (2) Key scan input pins”) (0004) | KEY7 | KEY6 | KEYS | KEY4/ KEY3 | KEY2 | KEY1 | KEYO (Initial value: | 1111 1111) Figure 2-7. Port P4

2.2.6 Port P5 (P55 - P50)

Port P5 is a 6-bit input/output port, and is also used as a comparator input, an 8-bit PWM (Pulse Width Modulation) output and an 8-bit programmable divider output. When used as an input port or a secondary function pin, the output latch should be set to “1”. The output latches are initialized to “1” during reset. Bits 6 and 7 are read in as “1” when a read instruction is executed for the port P5. CMP /MCMP/TEST/others: CMP /MCMP/TEST/others <] CPL/others <] others Data output {> a] >—+HL] Pin Data output [ool (451 pin Output latch Output latch STOP Hiz Control Control output OUTEN = » stor . 5 Hi-Z Control CIN} OUTEN d_) (a) P50 to P53 (b) P54to PSS 7 6 5 4 3 2 1 0 Note: j=3 00, * ; don’t care P5 : : PSS _: P54 : P53 : P52 : P51 : P50 (00054) : PDO : ECINO :CIN1 :CIN2:CIN3| (Initialvalue: **11 1111) Figure 2-8. P5 Port 3-71-45

TOSHIBA TMP87CM71/N71/P71/S71

2.2.7 Ports P6 (P67 - P60) and P7 (P77 - P70)

Ports P6 and P7 are 8-bit high-breakdown voltage input/output ports, and are also used as digit outputs, which can directly drive vacuum fluorescent tube (VFT). When used as an input port or a digit output, the output latch should be cleared to “0”. Pins which are not set for digit output can be used as normal I/O port (refer to section “2.12.6 Port Function”). The output latches are initialized to “0” during reset. CMP /MCMP/TEST /others OUTEN —d—, stor 1 7 6 5 4 3 2 1 0 PS P67 | PGG | PGS | PGA : PES | P62 | PGI : PEO Data input < <I (0006,) | G8 | G9 | G10: G11 | G12: G13 | G14: G15 SET/CLR/CPL /others = ~ = = ol (Initial value: 0000 0000) Data output P - - - = - ° , jutput latch P7 i i i i i E Digit output J (00074) | GO : G1 : G2: GB: G4: GS : G6: G7 VKK (Initial value; 0000 0000) Figure 2-9. PortsP6 and P7

2.2.8 Port P8 (P87 - P80)

Port P8 is an 8-bit high-breakdown voltage output port, and also used as a segment output (or a key strobe output), which can directly drive vacuum fluorescent tube (VFT). When used as an input port or a segment (key strobe) output, the output latch should be cleared to “0”. The output latches are initialized to “0” during reset. OUTEN —d sTOP {| _» Data input pawourpt —f> et 4th py, 2 8 5s 4 2 Output latch PB P87 | P86 | PBS | P84 | P83 | PB2 | PBI | P8O Segment output (0008) | $7 | S6 : SS | SA; SB: $2: SI: SO (key strobe output) 4 - - - - - - VkK (initial value: 0000 0000) Figure 2-10. Port P8

2.2.9 Port P9 (P97 - P90)

Port P9 is an 8-bit high-breakdown voltage input/output port, and also used as a segment output (or a key strobe output), which can directly drive vacuum fluorescent tube (VFT). When used as an input port or a segment (key strobe) output, the output latch should be cleared to “0”. Pins which are not set for segment output can be used as normal I/O port (refer to section “2.12.6 Port Function”). The output latches are initialized to “0” during reset. CMP 7MCMP TEST others OUTEN {_» Data input <] <} SET/CLR/CPL/others| Output latch P9 P97 : P96 | PIS : P94 | P93 | P92 : POI : PID Segment output } i : i i (key strobe output) VKK (Initial value: 0000 0000) Figure 2-11. Port P9 3-71-46

TOSHIBA TMP87CM71/N71/P71/S71

2.3 Time Base Timer (TBT)

The time-base timer is used to generate the base time for key scan and dynamic display processing. For this purpose, it generates a time-base timer interrupt (INTTBT) at predetermined intervals. This interrupt is generated beginning with the first rising edge of the source clock (the timing generator’s divider output selected by TBTCK) after the time-base timer is enabled. Note that since the divider cannot be cleared by a program, the first interrupt only may occur earlier than the set interrupt period. (See Figure 2-12. (b).) When selecting the interrupt frequency, make sure the time-base timer is disabled. (Do not change the selected interrupt frequency when disabling the active timer either.) However, you can select the interrupt frequency simultaneously when enabling the timer. Example : Sets the time base timer frequency to fc/216 [Hz] and enables an INTTBT interrupt. rm) (TBTCR) , 000010108 SET (EIRL). 6 px INTTBT fc/223 or 5/219 A interrupt fc/22" or 5/213 B request fc/2"® or 3/28 c_ |source clock fc/2"4 or 5/26 Dy Rising fe28 or fe/25 IE LY edge Source clock] 1 1 T fc/2"? or 5/24 F detector Z fc/2"" or fs/23 G TBTEN i c/29 or 5/2 Hi 3 ' f INTTBT i l TBTEK oN 1 *< “interrupt TBTCR Enable T3T period Time Base Timer Control Register (a) Configuration (b) Time Base Timer Interrupt Figure 2-12. Time Base Timer 7 6 5 4 3 2 1 t) to038) (initial value: 0¥#0 Ox») Time base timer 0: Disable TRTEN | enablerdisable 000 : fc/ 223 or fs/2'5 [Hz] 001 : fc/ 22" or fs/2'3 write 010 : fe/2!°or f5/2% only TeTcK | Time base timer interrupt 011 : fe/2"4or 5/26 frequency select 100 : fc/2"3 or 5/25 101 : fc/2'? or f5/24 110 : fc/2"' or 5/23 111 : fc/29 or f5/2 Note1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz], * ; don’t care Note2: TBTCR isa write-only register and must not be used with any of the read-modify-write instructions. Figure 2-13. Time Base Timer and Divider Output Control Register 3-71-47

TOSHIBA TMP87CM71/N71/P71/S71 Table 2-1. Time Base Timer Interrupt Frequency TBTCK SLOW, SLEEP mode 000 fc 223 5/215 5/215 0.95 Hz 1 Hz 001 fc/ 22! 5/213 5/213 3.81 4 010 fc/2'6 5/28 - 122.07 128 o1t fc/2"4 5/26 - 488.28 512 100 f/2"3 5/25 - 976.56 1024 101 fe/2'? 5/24 - 1953.12 2048 110 fc/2"! 5/23 - 3906.25 4096 111 fc/ 2° fs/2 - 15625 16384

2.4 Divider Output (DVO)

A50% duty pulse can be output using the divider output circuit, which is useful for piezo-electric buzzer drive. Divider output is from pin P13 (BVO). The P13 output latch should be set to “1” and then the P13 should be configured as an output mode. Divider output circuit is controlled by the control register (TBTCR) shown in Figure 2-14.Note that TBTCR is a write-only register, and must not be used with any of the read-modify-write instructions. 7 6 5 4 #3 2 1 0 03s) (initial value: 0¥#0 Ov+s) DVOEN | Divider output enable/disable ©: Disable 1: Enable 00 : fc/2"? or fs/25 [Hz] we Divider output (DVO) 01: fc/2! or f5/24 only DVOCK | + equency selection 10: fc/2"" or f5/23 11: fc/2'° or fs/2? Note: fc; High-frequency clock [Hz], fs ; Low-frequency clock [Hz], * ; don’t care Figure 2-14. Divider Output Control Register Example: 1kHz pulse output (at fc = 8 MHz) SET (P1).3 ; P13 output latch -1 LD (P1CR), 000010008 ; Configures P13 as an output mode LD (TBTCR), 100000008 ; DVOEN€1, DVOCKe-00 Table 2-2. Frequency of Divider Output pvock Frequency of At fc=8Mbz | At fs=32 kHz Divider Output 00 fe/2" or 3/2 0.97 [kHz] 1 [kHz] 10 fe/2" 5/2 3.90 4 3-71-48

TOSHIBA TMP87CM71/N71/P71/S71 output latch output enable data output [oa] | 4-3 ovo MPX A fe/2'3 or fs/25 A a fc/212 or fs/24 B fc/211 or fs/23 c P13 output latch | fe/ 210 or fs /22 D. : : 5 : Dvock DVOEN PVOEN | i L DVS Mrmr . . DVO Divider output control register (a) Configuration (b) Timing Chart Figure 2-15. Divider Output 2.5 16-bit Timer/Counter 1 (TC1)

2.5.1 Configuration

; 3 b> Tc1pin O ry De TT VU fo2" or fs/2? A leer fa? lc Source clock Ly Match S detect INTTC1

3 Comparator interrupt

TCICK Tc1s | Timer/counter 1 control register 16-bit timer register 1 Figure 2-16. Timer/Couter 1 3-71-49

TOSHIBA TMP87CM71/N71/P71/S71

2.5.2 Control

The timer/counter 1 is controlled by a timer/counter 1 control register (TC1CR) and a 16-bit timer register (TREG1). Reset does not affect TREG1. i 4 #13 +12 #«11 +10 9 8 7 6 5S 4 3 2 1 0 TREG! TREG1} (0011 REG 1, (0010, (0010, 0011,) H Hy u H 7 6 5 4 3 2 1 t) Write only TCICR pipe epee sogtaeeettase 00 : Internal clock fc/2" or fs/2? [Hz] teick | Timer/counter 1 01 : Internal clock fc/2” source clock select 10 : Internal clock fe/ 2? write 11 : External clock (TC1 pin input) only Timer/counter 1 0 : Stop and counter clear TCIS | start control 1: Command start Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz], *; don’t care Note2: Always write “0” to bits 0, 1, 5, 6and 7 in TCICR. Note3: Writing to the low-byte of timer register (TREG1,), the comparison is inhibited until the high-byte (TREG1),) is written. After writing to the high-byte, the comparison of 1 machine cycle (during instruction execution) is ignored. Note4: Set the mode, the source clock and the edge (INT2ES) when the TC1 stops (TC1S = 0). Note5: Values to be loaded to the timer register must satisfy the following condition. TREG1>0 Note 6: TCICR and TREG! are write-only registers which cannot be accessed by any read-modify-write instructions such as bit operate, etc. Figure 2-17. Timer Register 1 and TC1 Control Register

2.5.3 Function

Timer/counter 1 has two operating modes: timer mode and event counter mode. (1) Timer Mode In this mode, counting up is performed using the internal clock. The contents of TREG1 are compared with the contents of up-counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared to"0”. Counting up resumes after the counter is cleared. Table 2-3. Timer/Counter 1 Source Clock (Internal Clock) NORMAL1/2, IDLE1/2 modes SLOW, SLEEP modes = = = = fe/2? [Hz] fe/23[Hz] - 1s 65.5 ms fc/2? fc/2? - 16 ys 1.0 s fc/2" 5/2? fs/2? [Hz] 256 ps 244.14 ys 16.7 5 3-71-50

TOSHIBA TMP87CM71/N71/P71/S71 2.6 16-bit Timer/Counter 2 (TC2)

2.6.1 Configuration

MPX [> Te2pin O H U) fcl223 or f9/215 A seer 28 c Source clock f23>—>|D fe E letect INTTC2 s Comparator interrupt

3 Tc2s

Timer/counter 2 control register 16-bit timer register 2 Figure 2-20. Timer/Counter 2

2.6.2 Control

The timer/counter 2 is controlled by a timer/counter 2 control register (TC2CR) and a 16-bit timer register 2 (TREG2). Reset does not affect TREG2. 15 1413127 10 9S 2 1 0 TREG2 TREG2, (0017, TREG2, (0016 (0016, 0017,) H Hl : q 7 write only reocr 7.6 5 4 3 2 1 0 (0015,) "0". ;."0" | Te2s C2CK “on: "0": (Initial value: 00 00) 000 : Internal clock fc/2 or fs/2"° [Hz] 001 : Internal clock fc/2" or fs/2° 010 : Internal clock fc/ 2 TC2ck | Timer/counter 2 011 : Internal clock fc/2? write source clock select 100 : Internal clock fe (Note 5) 101 : Internal clock fs only 110 : Reserved 111: External clock (TC2 pin input) tc2g_| Timer/counter 2 0 : Stop and counter clear start control 1: Start Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz], *; don't care Note2: When writing to the low-byte of timer register 2 (TREG2,), the comparison is inhibited until the high-byte (TREG2,) is written. After writing to the high-byte, any match during 1 machine cycle (instruction execution cycle) is ignored. Note 3: Set the mode and source clock when timer/counter stop (TC2S = 0). Note4: Values to be loaded to the timer register must satisfy the following condition. TREG2 > 0 (TREG215 ¢9 11>0 when warm-up). Note5: “fc” canbe selected as the source clock only in the timer mode during SLOW mode. Note 6: Always write “0” to bit 0, 1,6 and 7 in TC2CR. Note 7: TC2CR and TREG2 are write-only registers and must not be used with any of read-modify- write instructions. Figure 2-21. Timer Register 2 and TC2 Control Register 3-71-52

TOSHIBA TMP87CM71/N71/P71/S71

2.6.3 Function

The timer/counter 2 has two operating modes: timer and event counter mode. Also timer/counter 2 is used for warm-up when switching from SLOW mode to NORMAL2 mode. (1) Timer Mode In this mode, the internal clock is used for counting up. The contents of timer register 2 (TREG2) are compared with the contents of the up-counter. If a match is found, a timer/ counter 2 interrupt (INTTC2) is generated, and the counter is cleared. Counting up is resumed after the up-counter is cleared. Also, when fc is selected as the source clock during SLOW mode, the lower 11 bits of TREG2 are ignored and an INTTC2 interrupt is generated by matching the upper 5 bits. Thus, in this case, only the TREG2q setting is necessary. Table 2-4. Source Clock (Internal Clock) for Timer/Counter 2 Resolution Maximum time setting SLOW mode | SLEEP mode fe/2[Hz] | fs/2"[Hz] | fs/2'°[Hz]| fs/2"(Hz]} 1.05 s 1 os 19.1 h 18.2 h fe/2” 5/2? 5/2? 5/2? 1.02 ms 1 ms 1.1 min 1 min fc/28 fc/2 - - 32s - 210s - fc/2? fc/2? - - 1 os - 65.5 ms - - - fc (Note) - 125 ns - 7.9 ms - fs fs - - - 30.5 4s - 26s Note: “fc” can be used only in the timer mode when switching from the SLOW mode to the NORMAL2 mode. Example: Sets the timer mode with source clock fc/23 [Hz] and generates an interrupt every 25 ms (at fc = 8 MHz). LD (TC2CR), 000011008 i Sets the TC2 mode and source clock Low (TREG2), 6148H ; Sets TREG2 (25 ms + 23/fc = 61A8}) LD (TC2CR), 001011008 j Starts TC2 (2) Event Counter Mode In this mode, events are counted on the rising edge of the TC2 pin input. The contents of TREG2 are compared with the contents of the up-counter. If a match is found, an INTTC2 interrupt is generated, and the counter is cleared. The maximum frequency applied to the TC2 pin is fc/24 [Hz] in NORMAL1/2 or IDLE1/2 mode, and fs/24 [Hz] in SLOW or SLEEP mode. Example: Sets the event counter mode and generates an INTT2 interrupt 640 counts later. LD (TC2CR), 000111008 ; Sets the TC2 mode LOW (TREG2), 0280H ; Sets TREG2 LD (TC2CR), 001111008 j Starts TC2 3-71-53

TOSHIBA TMP87CM71/N71/P71/S71 2.7 8-Bit Timer/Counter 3 (TC3)

2.7.1 Configuration

Edge Capture |) —-> detector control INTTC3 teas >] > ¥ INT3ES clear s re3pin O Ay) Sole D fel22 or fs24 lA y source clock overflow f0/2"9 or fs/22 iB ‘fci27 —— Es 2 i) [ match TC3CK capture coptur DS a Teas scap 8-bit Timer Register 3A, 3B | fi Timer/Counter 3 Control Register Figure 2-22. Timer/Counter 3

2.7.2 Control

The timer/counter 3 is controlled by a timer/counter 3 control register (TC3CR) and two 8-bit timer registers (TREG3A and TREG3B). Reset does not affect these timer registers. TREG3A 7 6 5 4 3 2 1 0 (0019,,) Read only 7. 6 5 4 3 2 1 0 TO3CR oe (O01As) sesandSCAP]... [teas] regex] [ream (Initial value: *0*0 00*0) Timer/counter 3 0 : Timer/event counter TOM . operation mode set 1: Capture 00 : Internal clock fc/2” or fs/2* [Hz] te3ack | Timer/counter 3 01 : Internal clock fc/2 or fs/2? source clock select 10 : Internal clock fc/2 write 11: External clock (TC3 pin input) only t¢35_| Timer/counter 3 0: Stop & clear start select 1: Start 0: = Note 1: fc, High-frequency clock [Hz] fs; Low-frequency clock [Hz] * ; don’t care Note2: Set the mode, the source clock and the edge when the TC3 stops (TC3S = 0). Note3: Values to be loaded into timer register 3A must satisfy the following condition. TREG3A > 0 (in the timer/event counter mode) Note 4: TC3CR isa write-only register and must not be used with any of read-modify-write instructions. Figure 2-23. Timer Register 3 and TC3 Control Register 3-71-54

TOSHIBA TMP87C446/846/H46/447/847/H47/847L/H47L

2.7.3 Function

The timer/counter 3 has three operating modes : timer, event counter, and capture mode. (1) Timer Mode In this mode, the internal clock is used for counting up. The contents of TREG3A are compared with the contents of up-counter. If a match is found, a timer/counter 3 interrupt (INTTC3) is generated, and the up-counter is cleared. Counting up resumes after the up-counter is cleared. The current contents of up-counter are loaded into TREG3B by setting SCAP (bit 6 in TC3CR) to “1”. SCAP is automatically cleared after capturing. Table 2-5. Source Clock (Internal Clock) for Timer Counter 3 fc/2” or fs/2* [Hz] fs/2* [Hz] 512 ys 488.28 ys 131.1. ms fc/2" or fs/2? - 128 us 122.07 4s 32.8 ms fe/2” - 16 ps - 4.1 ms (2) Event Counter Mode In this mode, the TC3 pin input pulses are used for counting up. Either the rising or falling edge can be selected with INT3ES (bit 3 in EINTCR). The contents of TREG3A are compared with the contents of the up-counter. If a match is found, an INTTC3 interrupt is generated and the counter is cleared. The maximum applied frequency is fc/2* [Hz] in the NORMAL1/2 or IDLE1/2 mode, and fs/2* [Hz] in SLOW or SLEEP mode. Two or more machine cycles are required for both the “H” and “L” levels of the pulse width. The current contents of up-counter are loaded into TREG3B by setting SCAP (bit 6 in TC3CR) to “1”. SCAP is automatically cleared after capturing. Example: Generates an interrupt every 0.5 s, inputing 50 Hz pulses to the TC3 pin. LD (TC3CR), 00001100B ; Sets TC3 mode and source clock LD (TREG3A), 19H ; 0.5841/50=25=194 SET — (EIRH). EF8. ; Enables INTTC3 EI LD (TC3CR), 00011100B ; Start TC3 (3) Capture Mode The pulse width, period and duty of the TC3 pin input are measured in this mode, which can be used in decoding the remote control signals, etc. The counter is free running by the internal clock. On the rising (falling) edge of the TC3 pin input, the current contents of counter is loaded into TREG3A, then the up-counter is cleared and an INTTC3 interrupt is generated. On the falling (rising) edge of the TC3 pin input, the current contents of the counter is loaded into the TREG3B. In this case, counting continues. At the next rising (falling) edge of the TC3 pin input, the current contents of counter are loaded into TREG3A, then the counter is cleared again and an interrupt is generated. If the counter overflows before the edge is detected, FFy is set to the TREG3A and an overflow interrupt (INTTC3) is generated. During interrupt processing, it can be determined whether or not there is an overflow by checking whether or not the TREG3A value is FFy. Also, after an interrupt (capture to TREG3A, or overflow detection) is generated, capture and overflow detection are halted until TREG3A has been read out; however, the counter continues. After TREG3A has been read out, capture and overflow detection are resumed, usually, TREG3B is read out first. 3-46-66

TOSHIBA TMP87C446/846/H46/447/847/H47/847L/H47L Internal clock J J | | J J | | J Upcounter OOOO OKO EX DCO XEODEXED C3 pin input \\ | P| TREG3A > > TREG3B es ee ed i. capture fq capture 1 overflow INTTC3 interrupt l Reading TREG3A J Figure 2-27. Timing Chart for Capture Mode (INT3ES = 0) 3-46-67

TOSHIBA TMP87CM71/N71/P71/S71

2.8.2 Control

The timer/counter 4 is controlled by a timer/counter 4 control register (TC4CR) and an 8-bit timer register 4(TREG4). Reset does not affect TREG4. 7 6 5 4 3 2 1 i) TREG4 . 7 6 5 4 3 2 1 0 TCACR poe oa oor) : TCACK TcaM (Initial value: 00*0 0000) 00 : Timer/event counter mode . 01 : Reserved Team | Tc4 it lect . operating mode selec 10 : Programmable divider output (PDO) mode 11 : Pulse width modulation (PWM) output mode 00 : Internal clock f¢/2"' or fs/2°[Hz] . 01: Internal clock f¢/2’ write TC4CK | TC4 source clock select 10: Internal clock fe/ 23 only 11 : External clock (TC4 pin input) 0 : Stop & clear T Toa 00 : Clear , 01 : Toggle TFF4 | Timer F/F 4 control 10 .Set 11: - (Note 3) 7 6 5 4 3 2 1 () EINTCR ee - ae - (oo) CEO) CS TORIC TY] nitial vatue: 000 000) 0 : Rising edge write TC4ES | TC4 input edge select 1 : Falling edge only Note1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz], *; don’t care Note2: Set the operating mode, the source clock selection and, the timer F/F 4 control and the edge (TC4ES) when the TC4 stops (TC4S = 0). Note3: TFF4 must be set to “11” in the timer and event counter modes. Note4: Values to be loaded to the timer register must satisfy the following condition. TREG4>0 Note 5: TC4CR and TREG4 are write-only registers and must not be used with any of read-modify- write instructions. Figure 2-26. Timer Register 4 and TC4 Control Register

2.8.3 Function

The timer/counter 4 has four operating modes : timer, event counter, programmable divider output, and PWM output mode. (1) Timer Mode In this mode, the internal clock is used for counting up. The contents of timer register 4 (TREG4) are compared with the contents of the up-counter. If a match is found, a timer/counter 4 interrupt (INTTC4) is generated and the counter is cleared. Counting up resumes after the up-counter is cleared. 3-71-57

TOSHIBA TMP87CM71/N71/P71/S71 Table 2-6. Source Clock (Internal Clock) for Timer/Counter 4 fc/2" fs/2? [Hz] fs/2? [Hz] 256 us 244.14 ys 65.536 ms 62.5 ms fc/27 fc/2? - 16 ys - 4.096 ms - fc/2? fc/2? - 1 us - 256 1s - (2) Event Counter Mode In this mode, the TC4 pin input (external clock) pulse is used for counting up. Either the rising or falling edge can be selected with TC4ES (bit 4in EINTCR). The contents of TREG4 are compared with the contents of the up-counter. If a match is found, an INTTC4 interrupt is generated and the counter is cleared. The maximum applied frequency is fo/24 [Hz] in NORMAL1/2 or IDLE1/2 mode, and fs/2* [Hz] in SLOW or SLEEP mode. Two or more machine cycles are required for both the high and low levels of the pulse width. (3) Programmable Divider Output (PDO) Mode The internal clock is used for counting up. The contents of TREG4 are compared with the contents of the up-counter. Timer F/F 4 output is toggled and the counter is cleared each time a match is found. Timer F/F 4 output is inverted and output to the PDO (P55) pin. This mode can be used for 50% duty pulse output. Timer F/F 4 can be initialized by program, and it is initialized to “0” during reset. An INTTC4 interrupt is generated each time the PDO output is toggled. Example: Output a 1024 Hz pulse (At fc = 4.194304 MHz) LD (TC4CR), 000001108 ; Initializes the TC4 mode, source clock and timer F/F 4. LD (TREG4), 10H i (11024 27/fc) +2=10H LD (TC4CR), 000101108 j Starts TC4 Up-counter oX1X2X 4) abe debemeieid dulembenbed d OX mat NG \\ SN Timer F/F 4 1 1 t t PDO pin output l INTTC4 interrupt l | | Figure 2-27. Timing Chart for PDO Mode 3-71-58

TOSHIBA TMP87CM71/N71/P71/S71 (4) Pulse Width Modulation (PWM) Output Mode PWM output with a resolution of 8 bits is possible. The internal clock is used for counting up. The contents of the TREG4 are compared with the contents of the up-counter. If a match is found, the timer F/F 4 output is toggled. The counter continues counting. And, when an overflow occurs, the timer F/F4 output is again toggled and the counter is cleared. Timer F/F 4 output is inverted and output to the PWM (P55) pin. An INTTC4 interrupt is generated when an overflow occurs. TREG4 is configured a 2-stage shift register and, during output, will not switch until one output cycle is completed even if TREG4 is overwritten; therefore, output can be altered continuously. Also, the first time, TREG4 is shifted by setting TC4S (bit 4 in TC4CR) to “1” after data is loaded to TREG4. Note1: Do not overwrite TREG4 only when an INTTC4 interrupt is generated. Usually, TREG4 is overwritten in the routine of INTTC4 interrupt service. Note 2: PWM output mode can be used only in the NORMAL 1, 2, and IDLE 1, 2 mode. Internal clock | | J J J | | J J Up-counter 9X AK GK OK K XE XK KKK XX XK Kno) iil mie laminas Cie TREG4 Kon Xf Xm Timer F/F 4 i t i i i PWM pin output 1 1 INTTC4 interrupt | Figure 2-28. Timing Chart for PWM Mode Table 2-7._ PWM Output Mode Resolution Repeat cycle SLOW, SLEEP mode fc/2" [Hz] fs/2? [Hz] fs/2° [Hz] 256 us 244.14 us 65.536 ms fe/2? fe?’ - 16 ps - 4.096 ms fe/ 2? fo/2 - 1s - 256 s 3-71-59

TOSHIBA TMP87CM71/N71/P71/S71

2.9 Serial Interface (SIO)

The 87CM71/N71/P71/S71 each have a clocked-synchronous 8-bit serial interface (SIO). The SIO has an 8- byte transmit and receive data buffer that can automatically and continuously transfer up to 64 bits of data. The SIO is connected to external devices via pins P32 (SCK), P33 (SI) and P34 (SO). The serial interface pins are also used as port P3. When used as serial interface pins, the P34-P32 output latches should be set to “1". In the transmit mode, pin P33 is used as a normal I/O port, and in the receive mode, pin P34 is used as anormal I/O port.

2.9.1 Configuration

$10 control register 1/ S10 control Status register register 2 Transmit and receive data buffer (8 bytes in DBR) “ Buffer control Control circuit circuit shitt Shift register if Clock so U serial data input INTSIO interrupt request Serial clock SCK pin Serial clock /O Figure 2-29. Serial Interface

2.9.2 Control

The SIO is controlled by two SIO control registers (SIOCR1 and SIOCR2). The serial interface status can be determined by reading a SIO status register (SIOSR). The transmit and receive data buffer is controlled by the SIOCR2. The data buffer is assigned to addresses OFFOy - OFF7} in the DBR (data buffer registers) area, and can continuously transfer up to 8 words (bytes or nibbles) at one time. When the specified number of words has been transferred, a buffer empty (in the transmit mode) or a buffer full (in the receive mode or transmit/receive mode) interrupt (INTSIO) is generated. When the internal clock is used as the serial clock in the 8-bit receive mode and the 8-bit transmit/receive mode, a fixed interval wait can be applied to the serial clock for each word transferred. Four different wait times can be selected with SIOCR2. 3-71-60

TOSHIBA TMP87CM71/N71/P71/S71 SIO Control Register 1 7 6 5 4 3 2 1 0 aes, (sos[aZ som, [Sek , _] initia value: 0000 0000) . 0: Stop if | fe . 0: Continue transfer | sows | Continue/abort transfer 1 : Abort transfer (automatically cleared after abort) 000 : 8-bit transmit mode 010 : 4-bit transmit mode write Transfer mode select 100 : 8-bit transmit/receive or receive mode (Note 1) only 110 : 4-bit receive mode *#1: reserved 000 : Internal clock fc/2"or fs/2° [Hz] 001 : Internal clock fc/2° ‘Output on! SCK _ | Serial clock select 010 : Internal clock fc/2° SCK pin 011 : Internal clock fc/2° 111: External clock (input from SCK pin) Note 1; Transmit/receive or receive mode are selected with ERM in SIOCR2. Note2: Set SIOS to “0” and SIOINH to "1” when setting the transfer mode or serial clock. Note3: fc; High-frequency clock [Hz], fs ; Low-frequency clock [Hz] Note 4: SIOCR1 is write-only register, which can not access any of in read- modify-write instruction such as bit operate, etc. SIO Status Register 7 5 4 2 1 SIOSR Ee peeesheseegeenons 8, Co Serial transfer operating 0 : Transfer terminated After SIOS is cleared to "0", SIOF *) status monitor 1: Transfer in process See eo chang ont” /| read Shift operating status 0 : Shift operation terminated only monitor 1: Shift operation in process SIO Control Register 2 siocr2 7.6 SO oon) [erm] war [eur | (Initial value: | **00 0000) 8-bit transmit/receive mode 0 : Transmit/receive mode / Always set to “0” except in ) control 1: Receive mode the 8-bit receive mode. 00:T = Tp (no waits) O1:T; = 2p WAIT | Wait control 10:1 = 4Tp | (waits) W1:T; = 8Tp write Buffer addresses used only 000 : 1-word transfer OFFO, 001 : 2-word transfer OFFO — OFF1y Number of transfer words | 010 : 3-word transfer OFFO — OFF2y 011: 4-word transfer OFFO - OFF3 100 : 5-word transfer OFFO - OFF4, 101 : 6-word transfer OFFO - OFFS} 110 : 7-word transfer OFFO - OFF6, 111: 8-word transfer OFFO — OFF7y, 3-71-61

TOSHIBA TMP87CM71/N71/P71/S71 ® External Clock An external clock connected to the SCK pin is used as the serial clock. In this case, the P32 ‘SCK) output latch must be set to “1”. To ensure shifting, a pulse width of at least 4 machine cycles is required. Thus, the maximum transfer speed is 244K-bit/s. (at fe = 8 MHz). SCK pin input l l tsckL tsckH Alfs (In the SLOW, SLEEP modes) b. Shift edge The leading edge is used to transmit, and the trailing edge is used to receive. @® Leading Edge Transmitted data are shifted on the leading edge of the serial clock (falling edge of the SCK pin input/output). @ Trailing Edge Received data are shifted on the trailing edge of the serial clock (rising edge of the SCK pin input/output). SCK pin t 1 1 1 (a) Leading Edge (b) Trailing Edge . Figure 2-32. Shift Edge (2) Number of Bits to Transfer Either 4-bit or 8-bit serial transfer can be selected. When 4-bit serial transfer is selected, only the lower 4 bits of the transmit/receive data buffer register are used. The upper 4 bits are cleared to “0” when receiving. The data is transferred in sequence starting at the least significant bit (LSB). (3) Number of Words to Transfer Up to 8 words consisting of 4 bits of data (4-bit serial transfer) or 8 bits (8-bit serial transfer) of data can be transferred continuously. The number of words to be transferred is loaded to BUF in SIOCR2. An INTSIO interrupt is generated when the specified number of words has been transferred. If the number of words is to be changed during transfer, the serial interface must be stopped before making the change. 3-71-63

TOSHIBA TMP87CM71/N71/P71/S71 sxn LE LILI SOpin VeXa X= Xe INTSIO interrupt (a) 1 Word Transmit SCK pin LLL LS LLY LS LS LY LS LI SO pin \\22X 2X 22 X23 X bo X bi Xb X 3 Ko Ka Ka Xe INTSIOinterrupt, (b) 3 Words Transmit Sipin (20 X21 X 22 X 23 X bo X bi X bz X bs Xo Ka X2Xa / INTSIOinterrupt, CSF (©) 3 Words Receive Figure 2-33. Number of Bits to Transfer (Example : 4-bit serial transfer)

2.9.3 Transfer Mode

SIOM (bits 5 - 3 in SIOCR1) and ERM (bit 5 in SIOCR2) are used to select the transmit, receive, or transmit/receive mode. (1) 4-bit and 8-bit Transmit Modes In these modes, SIOCR1 and SIOCR2 are set to the transmit mode and then the data to be transmitted first are written to the data buffer registers (DBR). After the data are written, the transmission is started by setting SIOS to “1”. The data are then output sequentially to the SO pin in synchronous with the serial clock, starting with the least significant bit (LSB). As soon as the LSB has been output, the data are transferred from the data buffer register to the shift register. When the final data bit has been transferred and the data buffer register is empty, an INTSIO (buffer empty) interrupt is generated to request the next transmitted data. When the internal clock is used, the serial clock will stop and an automatic-wait will be initiated if the next transmitted data are not loaded to the data buffer register by the time the number of data words specified with BUF has been transmitted. Writing even one word of data cancels the automatic-wait; therefore, when transmitting two or more words, always write the next word before transmission of the previous word is completed. Note: The wait is also canceled by writing to a DBR not being used as a transmit data buffer register; therefore, during SIO do not use such DBR for other applications. When an external clock is used, the data must be written to the data buffer register before shifting next data. Thus, the transfer speed is determined by the maximum delay time from the generation of the interrupt request to writing of the data to the data buffer register by the interrupt service program. When the transmit is started, after the SIOF goes "1” output from the SO pin holds final bit of the last data until falling edge of the SCK. The transmission is ended by clearing SIOS to “0” or setting SIOINH to “1” in buffer empty interrupt service program. That the transmission has ended can be determined from the status of SIOF (bit 7 in SIOSR) because SIOF is cleared to “0” when a transfer is completed. When an external clock is used, it is also necessary to clear SIOS to “0" before shifting the next data; otherwise, dummy data will be transmitted and the operation will end. When SIOINH is set, the transmission is immediately ended and SIOF is cleared to “0”. If it is necessary to change the number of words, SIOS should be cleared to “0”, then BUF must be rewritten after confirming that SIOF has been cleared to “0”. 3-71-64

TOSHIBA TMP87CM71/N71/P71/S71 : Clear SIO sios : SIOF : i SCK pin (output) H J l J | J l l H SO pin WX 2oX 2X 2X 23X 24X 25% 26X 27K boX biX ba baX baX bsX be X br/ INTSIO interrupt > | DBR X a Xe ‘4 (a) Internal Clock Write transmitted data L Clear S105 : sios ' : i SIOF i ! SEF Hi SCK pin (input) 4 SO pin WX aX aX aX 2X 24K 25h 26K a7 boX biX be baX ba bsX bs XOr/ INTSIO interrupt > DBR X a X b tt (b) External Clock Write transmitted data 5K pin l SIOF i SO pin Bits tsopy =min. 3.5/f¢ [s] (NORMAL1/2, IDLE 1/2 mode) = min. 3.5/fs [s] (SLOW, SLEEP mode) (¢)_ Transmitted Data Hold Time at End of Transmit/Receive Figure 2-34. Transmit Mode (Example : 8 bit, 1 Word Transmit) Example: The way of the transfer stopped (8-bit Transmit mode, External clock). STEST1: TEST (SIOCR1).SEF ; IFSEF = 1 then loop JRS F,STEST1 STEST2: TEST (P3).2 ; If5CK = 0 then loop JRS T,STEST2 LD (SIOCR1),00100111B — ; SIOS-0 When to clear SIOS to “0”, that it is also necessary to check SEF = 0 and SCK = 1. 3-71-65

TOSHIBA TMP87CM71/N71/P71/S71 (2) 4-bit and 8-bit Receive Modes After setting the control registers to the receive mode, set SIOS to “1” to enable receiving. The data is then transferred to the shift register via the SI pin synchronous with the serial clock. When one word of data has been received, it is transferred from the shift register to the data buffer register (DBR). When the number of words specified with BUF has been received, an INTSIO (buffer full) interrupt is generated to request that these data be read out. The data are then read from the data buffer registers by the interrupt service program. When the internal clock is used, and the previous data are not read from the data buffer register before the next data are received, the serial clock will stop and an automatic-wait will be initiated until the data are read. A wait will not be initiated if even one data word has been read. Note: The wait is also canceled by reading a DBR not being used as a received data buffer register is read; therefore, during SIO do not use such DBR for other applications. When an external clock is used, the shift operation is synchronized with the external clock; therefore, the previous data are read before the next data are transferred to the data buffer register. If the previous data have not been read, the next data will not be transferred to the data buffer register and the receiving of any more data will be canceled. When an external clock is used, the maximum transfer speed is determined by the delay between the time when the interrupt request is generated and when the data received have been read. The receiving is ended by clearing SIOS to “0” or setting SIOINH to “1” in buffer full interrupt service program. When SIOINH is set, the receiving is immediately ended and SIOF is cleared to “0”. When SIOS is cleared, the current data are transferred to the buffer in 4-bit or 8-bit blocks. The receiving mode ends when the transfer is completed. SIOF is cleared to “0” when receiving is ended and thus can be sensed by program to confirm that receiving has ended. If it is necessary to change the number of words in external clock operation, SIOS should be cleared to “0” then BUF must be rewritten after confirming that SIOF has been cleared to “0”. If it is necessary to change the number of words in internal clock, during automatic-wait operation which occurs after completion of data receive, BUF must be rewritten before the received data is read out. Note: The buffer contents are lost when the transfer mode is switched. If it should become necessary to switch the transfer mode, end receiving by clearing SIOS to “0”, read the last data and then switch the transfer mode. 3-71-66

TOSHIBA TMP87CM71/N71/P71/S71 sios ns SIOF SEF 1 ( Spin input VL 9X 2 XK 22K 23K 24X asX aX ax)X boX biXb2X baXbaX bsXosX br] | INTSIO interrupt fot per ee Reado Read out Figure 2-35. Receive Mode (Example: 8-bit, 1 Word, Internal Clock) (3) 8-bit Transmit/Receive Mode After setting the control registers to the 8-bit transmit/receive mode, write the data to be transmitted first to the data buffer registers (DBR). After that, enable transceiving by setting SIOS to “1". When transmitting, the data are output from the SO pin at leading edges of the serial clock. When receiving, the data are input to the SI pin at the trailing edges of the serial clock. 8-bit data are transferred from the shift register to the data buffer register. An INTSIO interrupt is generated when the number of data words specified with BUF has been transferred. The interrupt service program reads the received data from the data buffer register and then writes the data to be transmitted. The data buffer register is used for both transmitting and receiving; therefore, always write the data to be transmitted after reading the received data. When the internal clock is used, a wait is initiated until the received data is read and the next data is written. A wait will not be initiated if even one data word has been written. Note: The wait is also canceld by reading a DBR not being used as a received data buffer register is read ; therefore, during SIO do not use such DBR for other applications. When an external clock is used, the shift operation is synchronized with the external clock; therefore, it is necessary to read the received data and write the data to be transmitted next before starting the next shift operation. When an external clock is used, the transfer speed is determined by the maximum delay between generation of an interrupt request and the received data are read and the data to be transmitted next are written. When the transmit is started, after the SIOF goes "1” output from the SO pin holds final bit of the last data until falling edge of the SCK. The transmit / receive operation is ended by clearing SIOS to “0” or setting SIOINH to “1” in interrupt service program. When SIOS is cleared, the current data are transferred to the data buffer register in 8-bit blocks. The transmit mode ends when the transfer is completed. SIOF is cleared to “0” when receiving is ended and thus can be sensed by program to confirm that receiving has ended. When SIOINH is set, the transmit / receive operation is immediately ended and SIOF is cleared to “0”. If it is necessary to change the number of words in external clock operation, SIOS should be cleared to “0”, then BUF must be rewritten after confirming that SIOF has been cleared to “0”. 3-71-67

TOSHIBA TMP87CM71/N71/P71/S71 2.10 8-bit High-speed Serial Output (HSO) The 87CM71/N71/P71/S71 each have a clock-synchronous 8-bit serial output (HSO). The HSO has a 1-byte transmit data buffer register (HSODR). The HSODR is assigned to address OFF8} in the DBR area. The HSO is connected to the external devices via pins P35 (HSCR) and P37 (HSO). These pins are also used as the port P3. When used as pins HSCK/HSO, the P35/P37 output latches should be set to “1”. 2.10.1_Configuration transmit data vr 4 teas 7h coe ror HSODR pin fc/26 B y| Control O Serial data output

25 Ic circuit —

aisck nn t Serial clock output Figure 2-38. High-speed Serial Output

2.10.2 Control

The HSO is controlled by a HSO control register (HSOCR). The transfer status can be determined by reading a HSO status register (HSOSR). HSO Control Register 7 6 5 4 3 2 1 0 HSOCR eos esnnpasettenegeee ese (0024) : SL ck] (initiatvalue: *0** *+00) A 0 : Continue transfer fm fromm | Soeur” 00: Internal clock fc/2° — [Hz] we | 01: Internal clock fc/2° only SCK [Serial clock select 10:: Internal clock fe/2° 11: Internal clock fc/2? Note: fc; High-frequency clock [Hz], * ; don’t care HSO Status Register HSOSR ore OF Se Rsetce ccnp ee Qos (0024) "1" eae age age ae age SEF Shift operating status 0: Shift operation terminated (enable write to buffer) read monitor 1: Shift operation in process (disable write to buffer) | only Figure 2-39. HSO Control Register and Status Register

2.10.3 Transmit Operations

SCK (bits 1 and 0 in HSOCR) is used to select the transfer rate. Transmission is started by writing one byte of data to the HSODR. The transmit data are output sequentially to the HSO pin in synchronized with the falling edges of the serial clock, starting with the least significant bit (LSB). Writing to the buffer is disabled by the hardware during data transfers. The shift register is empty after one byte of data has been transferred, so writing to the buffer is again enabled at that point. SEF (bit 6 in HSOSR) is set to “1” during transfers (write to buffer disabled) and is cleared to “0” when a transfer is completed (write to buffer enabled); therefore, whether or not a transfer has been completed can be confirmed with a program that reads SEF. The HSCK pin is raised to “high” at the start and end of transfers. 3-71-69

TOSHIBA TMP87CM71/N71/P71/S71 Note: To continue a transfer without sensing SEF, write the next data to be transferred after 9 cycles (11 cycles when fc/23 [Hz] is selected only) at the transfer rate selected with SCK after writing to the buffer. HSODR ne HSO pin output ) PETE TERI? I oy Cry SEF Figure 2-40. High-speed Serial Output Timing Chart 2.11 6-bit A/D Conversion (Comparator) Inputs The comparator input is an analog input to discriminate key input or AFC (Auto Frequency Control) signal input, etc. The analog input voltage level (pins CINS - CINO) can be detected as 64-stage by setting reference voltage. The comparator input pins CIN5-CINO can also be used as ports P46, P47 and P53 - P50. When used as a comparator input, the output latch should be set to “1”. Note that the built-in pull- down resistances of the pins P47 and P46 must be cut off by clearing EPD (bits 7 and 6 in P4CR) to “0” when used as pins CIN4 and CINS.

2.11.1 Configuration

Comparator input control register SCIN 3 ECMP ‘ z Comparison result register P47 (CIN4) I-45 = rsovens) EE] 3 Ltt tt P51 (CIN2) FH co \\ COUTS to COUT i Comparator P53 (CINO) O TT ‘SVREF Comparator input refrence voltage setting register Figure 2-41. 6-bit A/D Conversion (Comparator) Input

2.11.2 Control

A/D conversion (comparator) inputs are controlled by a comparator input control register (CMPCR) and a comparator input data register (CMPDR). The CMPDR contains a reference voltage setting register (write-only) and a comparison result register (read-only). 3-71-70

TOSHIBA TMP87CM71/N71/P71/S71 Comparator Input Control Register cmPcr Dn GacssgneuDasessgvse sess Boose u 9 | 0 : Disable Comparator input ECMP | Comparator input control 1: Enable Comparator input 000 : 1 channel (CINO) 001 : 2 channels (CINO to 1) write Number of Comparator 010 : 3 channels (CINO to 2) only SCIN | input channels select 011 : 4 channels (CINO to 3) 100 : 5 channels (CINO to 4) 101 : 6 channels (CINO to 5) 11": Reserved Note! : The CMPCRisa write-only register and must not be used with any of the read-modify-write instructions. Note2 : Donotset the ECMP to “1” in the SLOW mode. Comparator Input Data Register 7 6 5 4 3 2 1 0 CMPDR i SVREF (Initial value: **00 0000) (000F) NNOINIIIIIE Reference voltage (Ver) write VREF Vrer= Vi VREF +1 V] (SVREF = B setting ner = Voo x (SVREF + 1)/64[V] (SVREF = 0 to 63) only cOUTS i . i i

10 Comparison result Result of comparing the CINS - CINO pin analog input voltage | read

couTO with the reference voltage. only Note: * ; don’t care Figure 2-42. Comparator Input Control Register and Data Register

2.11.3 Function

Reference voltage (Vper) is set with SVREF (bits 5 - 0 in CMPDR). The number of comparator input channels is selected with SCIN (bits 2 - 0 in CMPCR). Sequential comparison of the selected number of channels is started by setting ECMP (bit 7 in CMPCR) to "1". The comparison of one channel requires two machine cycles; therefore, the comparison result register (COUTS - COUTO) should be read out at an interval equal to [number of channels x 2 machine cycles] after setting the reference voltage (Vref). COUT5 - COUTO are set to “1” if the input voltage (pins CIN5 - CINO) is higher than the reference voltage (Vref) ; otherwise those are cleared to “0”. Note 1: When entering STOP and SLOW modes, ECMP is automatically cleared and SCIN/SVREF are held. And, COUTS - COUTO are always set to “1”. Note2: Any pins specified for comparator input with SCIN can no longer be used for normal digital input or key scan input, and are read out as“0”. Note 3: COUTS - COUTO are read out as “1” when not used as a comparator input. For example, bits 7 to 3 in CMPDR are always read out as “1” when SCIN =0105. 3-71-71

TOSHIBA TMP87CM71/N71/P71/S71 Example : Comparates the CIN3-CINO inputs with Vref = 2.5 V (At Vpp =5 V). Lo (P5), 111111118 ; Sets port P5 output latches to "1" LD (CMPDR), 00011111B ; Sets Vpep=2.5V LD (CMPCR), 10000011B ; Sets SCIN to 4 channels and Enables comparator input : } 4chx2 machine cycles -2 H = 6 machine cycles wait. LD A, (CMPDR) ; Reads CMPDR (COUTO to COUT3). Table 2-9. Reference Voltage (at Vpp = 5V) CR OR OO A Add 4922 a a a 5.000

2.12 Vacuum Fluorescent Tube Driver Circuit

The 87CM71/N71/P71/S71 each have 32 high-breakdown voltage output buffers that directly drive the Vacuum Fluorescent Tube (VFT) and its control circuit.

2.12.1 Configuration

Figure 2-43 shows the VFT driver circuitry configuration. Key scan status register DIG if it ary p STCK y ¥ y wait Digit control circuit Display data butter Key scan control wen (32 bytes in DBR) register O Oo O a Fy 4 G15 Go S15 * $0 KEY7 ~ KEYO Figure 2-43. VFT Driver Circuitry 3-71-72

TOSHIBA TMP87CM71/N71/P71/S71 2.12.2. Function @® 32 high-breakdown voltage output buffers. © 16 digit output buffers (GO to G15) @ 16segment output buffers (SO to $15) The VKK pin is provided for the VFT drive power supply. @® 8-16segments x 1 - 16 digits can be selected by program using the dynamic display. @ Pins not used for the VFT driver can be used as general-purpose ports. @ The display data is automatically transferred to the high-breakdown voltage output buffers from the display data buffer memory (32 bytes in the DBR). © Brightness level adjustment (8 levels) is available with a dimmer function. © An automatic key scan function is available. It is possible to use the segment outputs for key strobe outputs.

2.12.3 Control

The VFT driver circuit is controlled by two VFT control registers (VFTCR1 and VFTCR2). The VFT operational status can be determined by reading a VFT status register (VFTSR). Switching from NORMAL 1 or NORMAL 2 mode to SLOW or STOP mode, BLK is set to “1” and EKEY is cleared to “0” ; therefore, the VFT driver circuit is placed into the blanking state. The contents of the VFT control registers (except BLK, EKEY) are held. Also segment outputs and digit outputs are cleared to “0”; therefore, the ports P6, P7, P8 and P9 function as normal I/O ports with pull-down. VFT Control Register 1 VeTCR1 7 6 5 4 3 2 1 0 (0028, (initial value: 1000 0111) . 0: Enable - 0: Disable 00: fc/2" or fs/2° [Hz] (once every 4 tsec) Key scan strobe source clock 01: fe/2" or fs/2° (once every 8 tse) STCK | select 10: fc/2" or 5/27 (once every 16 tseq) 11: fc/2" or fs/2° (once every 32 tseg) 0111: 8-segmentdisplay mode (outputs $0 to $7) we 1000: 9-segment display mode (outputs $0 to $8) ¥ 1001: 10-segment displaymode (outputs $0 to $9) 1010: 11-segment display mode (outputs $0 to $10) 1011: 12-segment displaymode (outputs $0 to $11) SEG | Number of segmentsselect | 1109: 13.segment display mode (outputs $0 to $12) 1101: 14-segment displaymode (outputs $0 to $13) 1110: 15-segment displaymode (outputs $0 to $14) 1111: 16-segment displaymode (outputs $0 to $15) O*«0 : Reserved 0*0x : Reserved 00+» : Reserved Figure 2-44 (a). VFT Control Registers Note! : fc ;High-frequency clock [Hz], fs ; Low-frequency clock [Hz], Note2 : VFTCR1 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc. 3-71-73

TOSHIBA TMP87CM71/N71/P71/S71 VFT Control Register 2 veTcr2 J... 6 5 4 3 2 41 0 (0029) (initial value: *000 0000) 000: (14/16) x tseg Is] 001 : (12/16) x tseg 010: (10/16) x tseg . 011: (8/16) x tseg Dimmer time select 100: (6/16) x tere 101: (4/16) x tseG 110: (2/16) x tseG 111: (1/16) x tseG 0000: 1-digit display mode (outputs GO) 0001: 2-digit display mode (outputs GO to G1) 0010: 3-digit display mode (outputs GO to G2) write 0011: 4-digit display mode (outputs GO to G3) only 0100: 5-digit display mode (outputs GO to G4) 0101: 6-digit display mode (outputs GO to G5) a 0110: 7-digit display mode (outputs G0 to G6) Number of digits select 0111: 8-digit display mode (outputs GO to G7) 1000: 9-digit display mode (outputs GO to G8) 1001 : 10-digit display mode (outputs G0 to G9) 1010 : 11-digit display mode (outputs G0 to G10) 1011: 12-digit display mode (outputs G0 to G11) 1100 : 13-digit display mode (outputs G0 to G12) 1101 : 14-digit display mode (outputs G0 to G13) 1110: 15-digit display mode (outputs G0 to G14) 1111: 16 -digit display mode(outputs G0 to G15) During NORMAL 2 mode (DV7CK =1) 02... 000c0cc00seeeeeeeeeeeeeeeteeeeeeeee 235 VFT Status Register 7 6 5 a wait _ | VFT display operational 0: VET display in operation read status monitor 1: VET display operation disabled (or key scan operation) | only Key Scan Status Register KEYSR oie eect Bocce dosnt ey 2 2 1 9 Figure 2-44 (b). VFT Control Registers/Status Registers (1) Display Mode Setting The number of segments is selected with SEG (bits 3-0 in VFTCR1) and the number of digits is selected with DIG (bits 3-0 in VFTCR2) when BLK (bit 7 in VFTCR1) = 1 and EKEY (bit 6 in VFTCR1)=0. The dimmer time (digit output time) is selected with DIM (bits 6-4 in VFTCR2). Example : Sets display mode (8-seg. x 16-dig., (14/16) x tse) LDW (VETCR1), OF87H =; ~ BLKe~1, EKEY¢-0, STCKe-00, SEG-0111, DIM<-000, DIG-1111 (2) Display Data Setting Normally, the conversion of data to VFT display data is performed by instructions. The converted data which stored to the display data buffer memory (addresses OF80} - OF9Fy in the DBR) is 3-71-74

TOSHIBA TMP87CM71/N71/P71/S71 automatically transferred to the VFT driver circuit and output to the high-breakdown voltage output buffers. Thus, display patterns can be varied by merely changing the data in the data buffer memory. The VFT segments (dots) and display data area bits have a one-to-one correspondence. A “1” bit lights the corresponding segment and a “0” bit turns off the corresponding segment. Areas of the display data buffer not used for display purposes can be used as normal data memory. The display data buffer is assigned to the DBR area shown in Figure 2-45 (a) but, in the 8-segment display mode only, the assignment is as shown in Figure 2-45 (b) for more effective utilization of data memory. Bit 7654321076543210 Digit 76543210 Digit i i ! Poy ' i i ' Pot ee (a) 9 to 16-segment Display Mode (b) 8segment Display Mode Figure 2-45. VFT Display Data Buffer Memory (DBR)

2.12.4 Display Operation

After setting the display mode and storing the display data, VFT display is started by clearing BLK to “0”. Figure 2-46 shows the VFT drive waveform. Dimmer time -+¥——| Gl | Go l | $7.50 tse [s] Figure 2-46. VFT Drive Waveform (Example : 8-segment x 3-digit Display)

2.12.5 Key Scan Function

The key strobe signal can be output automatically. The output latch should be set to “1” to use the port P4 (KEY) for key scan input. Setting EKEY (bit 6 in VFTCR1) to “1”, the key scan timing is inserted into the display operation synchronizes with the scan rate selected with STCK. A key strobe pulse is output at the key scan timing from the pin Sn (one of the scan segment output pins selected with SEG). The segment pin number “n" is decremented at each key scan timing. For example, in the 8-segment display mode, the output would be from the S7-S6— «> S0—S7 pins. 3-71-75

TOSHIBA TMP87CM71/N71/P71/S71 The KEY7 - KEYO pin input data synchronized with the key strobe output are latched to the key scan input latches (KEYDR) ; therefore, key scan can be performed by configuring a key matrix with the segment output pins and KEY 7 - KEYO pins. The key scan interrupt request (INTKEY) is generated in synchronized with key data latching; therefore, the key strobe bit can be identified by sensing the key scan status register (002Ay) with an interrupt service routine and reading the stored key data (return code) from the key scan input latches (KEYDR). The following key scan timing is canceled until KEYDR has been read out. they sr ED GED AW ay AD, ED, GED AW 2 a A (key strobe) output ED AV Ey A CD DAW INTKEY interruptrequest, PE Key data read Figure 2-47. Key Scan Timing (8-digit Display) 87CM71/N71/P71 G0~G15 digit outputs key strobe outputs Key returns bb BG P40~P47 P—P DP—H DO—P D—P Figure 2-48. Key Matrix Example

2.12.6 Port Function

(1) High-Breakdown Voltage Buffer When a VFT is being driven, the output latch is cleared to “0”. The port output latch is initialized to “0” during reset). When using as a normal input/output pin, caution is required because of being pulled down to the VKK pin voltage internally. 3-71-76

TOSHIBA TMP87CM71/N71/P71/S71 INPUT/OUTPUT CIRCUITRY The instruction for specifying Masking Option (I/O code) in ES Order Sheet is described in ADDITIONAL INFORMATION “Notice for Masking Option of TLCS-870 series” section 8. (1) Control pins The input/output circuitries of the 87CM71/N71/P71/S71 control pins are shown below. Please specify either the single-clock mode (oscillation only XIN/XOUT) or the dual-clock mode (oscillation both XIN/XOUT and XTIN/XTOUT) by a code (NM1 or NM2) as an option for an operating mode during reset. Osc. enable fe Resonator connecting pins (high-frequency) XIN Input VDD Re R vod Ry =1.2MQ (typ) XOUT Output ° Ro =1.5k2 (typ) R =1kQ (typ.) XIN XOUT Osc. enable XTEN Resonator connecting pins fs (low-frequency) XTIN (P21) Input | Refer Re =6MQ. (typ.) XTOUT (P22) Output | to Re Ro =220kQ = (typ.) R ‘0 YP. Port P2 ° R =1k2 — (typ) XTIN XTOUT VDD Sink open drain output Rin Hysteresis input — R RESET VO | Address-trap-reset Pull-up resistor Wathog-merrese=—=]_>—— Rin =220k2 — (typ.) System-clock-reset R =1ka (typ.) a R Hysteresis input STOP /INTS Input (P20) P20 R =1kQ (typ) STOP/INTS VoD R Pull-down resistor test Input Rin =70kQ — (typ.) R "N R =1k0 (typ.) Note! : The TEST pin of the 87PP71/PS71 does not have a pull-down resistor. Fix the TEST pin at low level in MCU mode. Note2 : The 87PP71/PS71 are placed in the single-clock mode during reset, and the input/output circuitries are the code M1 type. 3-71-78

TOSHIBA TMP87CM71/N71/P71/S71 (2) Input/Output Ports The input/output circuitries of the 87CM71/N71/P71/S71 input / output ports are shown below. A mask option code is only “A”. INPUT/ OUTPUT CIRCUITRY (CODE _A) REMARKS. initial “Hi-2" VDD Tri-state VO vo disable a R R=1k0 (typ.) al "Hi7 VDD initial "Hi-Z Tri-state VO Hysteresis input vo : Le disable R R=1k0 (typ.) initial “Hi-z Sink open drain output vo o— R R=1kQ Sink open drain output initial “Hi-2" [>o. Hysteresis input vo R R=1k9 (typ.) Sink open drain output initial “Hi-2" —>o— iN Hysteresis input vo %y Riv = 70kO (typ.) ——— Riy is programable pull-down. digital input R=1k0 (typ.) initial “Hi-2" Sink open drain output P5 vo R R=1k digital input 2 Cyp) To be continued. 3-71-79

TOSHIBA TMP87CM71/N71/P71/S71 INBUT/ OUTPUT CIRCUITRY (CODE_A) initial "Hi-2” VDD Source open drain output P6 R Rk vo High-breakdown voltage P7 VKK > Rx = 80 kA (typ.) R=1k0 (ty P9 at (typ.) VOD Source open drain output initial "Hi-Z" Output R High-breakdown voltage K Rx = 800 (typ.) VK R=1k0 (typ.) 3-71-80

TOSHIBA TMP87CM71/N71/P71/S71

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS (Vss=0V) PARAMETER SYMBOL CONDITIONS RATINGS Input Voltage Povw fo = 0.3 t0V00 +03 P2, P3, P4, PS, XOUT, RESET =0.3t0 Vop + 0.3 Output Voltage ouTt DD v | ours [Po, Pi, p2,P3p4ps | 82 Output Current (Per 1 pin) P8, P9 (segment outputs) [ -12 | sma P6, P7 (digit outputs) Output Current (Total) Slours_|PO 3, 5 0 mA (1) 87CM71/N71/P71 RECOMMENDED OPERATING CONDITIONS (Vss=0V, Topr= - 30 to 70°C) fe=8MHz IDLE1, 2 modes fe= NORMAL1, 2 modes Supply Voltage Voo 42MHe v ee ec Vpp24.5V Except hysteresis input Vpp x 0.30 Vpp24.5V ee Clock Frequency 3-71-81

TOSHIBA TMP87CM71/N71/P71/S71 (2) 87¢S71 RECOMMENDED OPERATING CONDITIONS (Vss=0V, Topr= - 30 to 70°C) fe=8MHz IDLE1, 2 modes Supply Voltage Vo fs= v 32.768 kHz 27 nc Except hysteresis input _ Vpp24.5V ce ee eT] Except hysteresis input Vop24.5V Pe fen xoor | voo-asiossv | clockFrequeney | e | «| 80 |e 3-71-82

TOSHIBA TMP87CM71/N71/P71/S71 D.C. CHARACTERISTICS (Vsg=0V, Topr= ~ 300 70°C) Hysteresis Voltage | Vas [Hysteresisinput | dT = To | - Tv Voo=5.5V Input Current Open drain ports, Tri-state ports £2 | yA Input Resistance —— RESET po 100 | 220 | 50 | kn Sink open drain ports Voo=5.5V,Vour=55V | - | - | 2 | Output Leakage Source open drain ports Voo=55V, Vour=-30V_ | - | - | -2 | pA Current [is Pisatepors—|Von05V-vouressvow | [= [a2 Output High Voltage | VOH2 4 state por's DO oH ma [ai [ - | - | v [Wows [P68 No v.igne Sma D2 || | mA Supply Current in fs = 32.768 kHz IDLE 1, 2 modes Vin = 5.3V/0.2V 45 Supply Current in SLOW mode Vp =3.0V 30 fs = 32.768 kHz yA Supply Current in SLEEP mode Viv=2.8V/0.2V 15 Supply Current in Vpp=5.5V STOP mode Vi =5.3V/0.2V a Note 1: Typical values show those at Topr =25 °C, Vop =5V. Note2: Input Current liv ling; The current through resistor is not included, when the input resistor (pull- uplpull-down) is contained. Note 3: Typical current consumption during A/D conversion is 1.2 mA. ‘AID CONVERSION CHARACTERISTICS (Vsg=0V, Vpp =2.7/4.5 to 5.5V, Topr= - 30 to 70°C) Ce 3-71-83

TOSHIBA TMP87CM71/N71/P71/S71 In NORMAL, 2 modes Machine Cycle Time ty “s In SLOW mode 117.6 High Level Clock Pulse Width For external clock operation Low Level Clock Pulse Width (XIN input), fe= 8 MHz High Level Clock Pulse Width For external clock operation 47 . 14. s Low Level Clock Pulse Width OCTIN input), fs = 32.768 kHz RECOMMENDED OSCILLATING CONDITIONS | (Vss=0V, Vpp=2.7/4.5to 5.5V, Topr= -30to 70°C) ae Recommended Constant PARAMETER Oscillator Oscillation Recommended Oscillator Ceramic Resonator KYOCERA —_KBR4.0MS 30 pF 4MHz High-frequency MURATA CSA 4.00MG Oscillation 8 MHz TOYOCOM —210B 8.0000 Crystal Oscillator 20 pF 4MHz TOYOCOM — 2048 4.0000 Low-frequency 1 Oscill 2.768 kH NDK MX-38T 15 pF Oscillation Crystal Oscillator 32.768 kHz 5pl XTIN XTQUT XIN XOUT a W Poy G Co (1) High-frequency Oscillation (2) Low-frequency Oscillation Note : An electrical shield by metal shield plate on the surface of the IC package should be recommendable in order to prevent the device from the high electric fieldstress applied for continuous reliable operation. 3-71-84