8745BYILFT

ICS8745BI RENESAS | Alldatasheet

Document overview

• Manufacturer or author: pieczonkae
• PDF pages: 21

Technical content

Features

• Five differential LVDS outputs designed to meet or exceed the requirements of ANSI TIA/EIA-644
• Selectable differential clock inputs
• CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Output frequency range: 31.25MHz to 700MHz
• Input frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• External feedback for “zero delay” clock regeneration with configurable frequencies
• Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Cycle-to-cycle jitter: 30ps (maximum)
• Output skew: 40ps (maximum)
• Static phase offset: 25ps ± 125ps
• Full 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6) packages HiPerClockS™ ICS ICS8745BI 32-Lead LQFP 7mm x 7mm x 1.4mm package body Top View Block Diagram PLL_SEL CLK0 nCLK0 CLK1 nCLK1 CLK_SEL FB_IN nFB_IN SEL0 SEL1 SEL2 SEL3 MR nQ0 nQ1 nQ2 nQ3 nQ4 PLL 1:2, 1:4, 1:8 ÷1, ÷2, ÷4, ÷8, ÷16, ÷32, ÷64 Pullup Pullup Pulldown Pullup Pulldown Pullup Pulldown Pulldown Pullup Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Pin Assignment 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL MR nQ3 VDDO nQ2 GND nQ1 VDD nFB_IN FB_IN SEL2 GND nQ0 VDDO PLL_SEL VDDA SEL3 VDDO nQ4 GND VDD

ICS8745BYI REVISION D JUNE 11, 2009 2 ©2009 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics SEL2 SEL3 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. 3 CLK0 Input Pulldown Non-inverting differential clock input. 4 nCLK0 Input Pullup Inverting differential clock input. 5 CLK1 Input Pulldown Non-inverting differential clock input. 6 nCLK1 Input Pullup Inverting differential clock input. nCLK0. LVCMOS / LVTTL interface levels.

8 MR Input Pulldown

causing the true outputs Qx to go low and the inverted outputs nQx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. 13, 19, 25 GND Power Power supply ground. 14, 15 nQ0/Q0 Output Differential outp ut pair. LVDS interface levels. 16, 22, 28 V DDO Power Output supply pins. 17, 18 nQ1/Q1 Output Differential outp ut pair. LVDS interface levels. 20, 21 nQ2/Q2 Output Differential outp ut pair. LVDS interface levels. 23, 24 nQ3/Q3 Output Differential outp ut pair. LVDS interface levels. 26, 27 nQ4/Q4 Output Differential outp ut pair. LVDS interface levels. 30 V DDA Power Analog supply pin. dividers. When LOW, selects reference clock. LVCMOS/LVTTL interface levels.

ICS8745BYI REVISION D JUNE 11, 2009 3 ©2009 Integrated Device Technology, Inc. ICS8745BI Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Function Tables Table 3A. Control Input Function Table *NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz. Inputs Outputs PLL_SEL = 1 PLL Enable Mode SEL3 SEL2 SEL1 SEL0 Reference Freque ncy Range (MHz)* Q[0:4], nQ[0:4] 0z 0 0 0 250 - 700 ÷1 0001 1 2 5 - 3 5 0 ÷ 1 0010 6 2 . 5 - 1 7 5 ÷ 1 0011 3 1 . 2 5 - 8 7 . 5 ÷ 1 0100 2 5 0 - 7 0 0 ÷ 2 0101 1 2 5 - 3 5 0 ÷ 2 0110 6 2 . 5 - 1 7 5 ÷ 2 0111 2 5 0 - 7 0 0 ÷ 4 1000 1 2 5 - 3 5 0 ÷ 4 1001 2 5 0 - 7 0 0 ÷ 8 1010 1 2 5 - 3 5 0 x 2 1011 6 2 . 5 - 1 7 5 x 2 1100 3 1 . 2 5 - 8 7 . 5 x 2 1101 6 2 . 5 - 1 7 5 x 4 1110 3 1 . 2 5 - 8 7 . 5 x 4 1111 3 1 . 2 5 - 8 7 . 5 x 8

ICS8745BYI REVISION D JUNE 11, 2009 4 ©2009 Integrated Device Technology, Inc. ICS8745BI Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Table 3B. PLL Bypass Function Table Inputs Outputs PLL_SEL = 0 PLL Bypass Mode SEL3 SEL2 SEL1 SEL0 Q[0:4], nQ[0:4] 0 z 000 ÷ 4 0001 ÷ 4 0010 ÷ 4 0011 ÷ 8 0100 ÷ 8 0101 ÷ 8 0110 ÷ 1 6 0111 ÷ 1 6 1000 ÷ 3 2 1001 ÷ 6 4 1010 ÷ 2 1011 ÷ 2 1100 ÷ 4 1101 ÷ 1 1110 ÷ 2 1111 ÷ 1

ICS8745BYI REVISION D JUNE 11, 2009 5 ©2009 Integrated Device Technology, Inc. ICS8745BI Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. LVDS Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, θ JA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 128 mA IDDA Analog Supply Current 18 mA IDDO Output Supply Current 62 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current CLK_SEL, SEL[0:3], MR VDD = VIN = 3.465V 150 µA PLL_SEL V DD = VIN = 3.465V 5 µA IIL Input Low Current CLK_SEL, SEL[0:3], MR V DD = 3.465V, VIN = 0V -5 µA PLL_SEL V DD = 3.465V, VIN = 0V -150 µA

ICS8745BYI REVISION D JUNE 11, 2009 6 ©2009 Integrated Device Technology, Inc. NOTE 2: For single-ended applications, the maximum input voltage for CLKx, nCLKx is VDD + 0.3V. Table 5. Input Frequency Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C

ICS8745BYI REVISION D JUNE 11, 2009 7 ©2009 Integrated Device Technology, Inc. Table 6. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C has been reached under these conditions.. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. the PLL is locked and the input reference frequency is stable. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Characterized at VCO frequency of 622MHz. NOTE 7: Measured from the 20% to 80% points. Guaranteed by characterization. Not production tested.

ICS8745BYI REVISION D JUNE 11, 2009 8 ©2009 Integrated Device Technology, Inc. ICS8745BI Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Parameter Measurement Information 3.3V LVDS Output Load AC Test Circuit Phase Jitter and Static Phase Offset Cycle-to-Cycle Jitter Differential Input Level Output Skew Output Rise/Fall Time SCOPE Qx nQx 3.3V±5% POWER SUPPL Y +–Float GND LVDS VDDA, VDDO VDD, nCLK[0:1] CLK[0:1] nFB_IN FB_IN ➤ ➤t(Ø) VOH VOL VOH VOL ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

Q[0:4] nQ[0:4] VDD nCLK[0:1] CLK[0:1] GND VCMR Cross Points VPP tsk(o) Qx nQx Qy nQy 20% 80% 80% 20% tR tF VOD Q[0:4] nQ[0:4]

ICS8745BYI REVISION D JUNE 11, 2009 9 ©2009 Integrated Device Technology, Inc. ICS8745BI Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Parameter Measurement Information, continued Output Duty Cycle Offset Voltage Setup Propagation Delay Differential Output Voltage Setup tPW tPERIOD tPW tPERIOD odc = x 100% Q[0:4] nQ[0:4] out out LVDSDC Input ➤ VOS/∆ VOS VDD nQ[0:4] Q[0:4] nCLK[0:1] CLK[0:1] tPD 100 out out LVDSDC Input VOD/∆ VOD VDD

ICS8745BYI REVISION D JUNE 11, 2009 12 ©2009 Integrated Device Technology, Inc. resistance is not required but can be added for additional protection. additional protection, a 1kΩ resistor can be tied from CLK to ground. recommended to terminate the unused outputs. Figure 4. Typical LVDS Driver Termination

ICS8745BYI REVISION D JUNE 11, 2009 13 ©2009 Integrated Device Technology, Inc. ICS8745BI Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Schematic Example The schematic of the ICS8745BI layout example is shown in Figure 5A. The ICS8745BI recommended PCB board layout for this example is shown in Figure 5B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P .C. board. Figure 5A. ICS8745BI LVDS Zero Delay Buffer Schematic Example 8745 SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL MR VDD nFB_IN FB_IN SEL2 GND nQ0 VDDO nQ1 GND nQ2 VDDO nQ3 VDD PLL_SEL VDDA SEL3 VDDO nQ4 GND SP = Space (i.e. not intstalled) C16 10u CLK_SEL 0.1uF VDDO=3.3V C11 0.01u RD3 SP VDD (U1-9) VDD=3.3V SEL[3:0] = 0101, Divide by 2 RU3 Zo = 50 Ohm (77.76 MHz) RU4 RU5 SP SEL0 RD4 SP (155.5 MHz) SEL2 RU6 0.1uF 0.1uF RU7 SP 3.3V PECL Driver CLK_SEL RD2 RD5 VDDO SEL1 VDDO (U1-28) SEL3 R8A Zo = 50 Ohm 100 Decoupling capacitor located near the power pins R10 SEL3 RU2 SP RD6 SP 100 VDD SEL0 (U1-32) SEL2 0.1uF RD7 Zo = 50 Ohm SEL1 3.3V (U1-16) PLL_SEL VDD VDD VDDA (U1-22) 0.1uF PLL_SEL Zo = 50 Ohm LVDS_input

ICS8745BYI REVISION D JUNE 11, 2009 14 ©2009 Integrated Device Technology, Inc. ICS8745BI Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR The following component footprints are used in this layout example. All the resistors and capacitors are size 0603. Power and Grounding Place the decoupling capacitors as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the V DDA pin as possible. Clock Traces and Termination Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces.  The differential 50 Ω output traces should have the same length.  Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines.  Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity.  To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace.  Make sure no other signal traces are routed between the clock trace pair.  The matching termination resistors should be located as close to the receiver input pins as possible. Figure 5B. PCB Board Layout for ICS8745BI C16 GND

50 Ohm

ICS8745BYI REVISION D JUNE 11, 2009 15 ©2009 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS8745BI. Equations and example calculations are also provided. The total power dissipation for the ICS8745BI is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. maximum recommended junction temperature for HiPerClockS devices is 125°C. flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 7below. Table 7. Thermal Resitance θJA for 32 Lead LQFP, Forced Convection NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

ICS8745BYI REVISION D JUNE 11, 2009 16 ©2009 Integrated Device Technology, Inc. Table 8. θJA vs. Air Flow Table for a 32 Lead LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

ICS8745BYI REVISION D JUNE 11, 2009 17 ©2009 Integrated Device Technology, Inc. Table 9. Package Dimensions for 32 Lead LQFP

ICS8745BYI REVISION D JUNE 11, 2009 18 ©2009 Integrated Device Technology, Inc. ICS8745BI Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Ordering Information

Table 10. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

ICS8745BYI REVISION D JUNE 11, 2009 19 ©2009 Integrated Device Technology, Inc. ICS8745BI Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Revision History Sheet Rev Table Page Description of Change Date B T4D 5 LVDS DC Characteristics Table - m odified VOS 0.90V min. to 1.05V min, C T6 7 AC Characteristics Table - changed tPD max limit from 3.9ns to 4.0ns. Added Power Considerations section. Updated format throughout the datasheet. 4/16/07 D T4C T10 Pin Assignment - corrected pin 14 from Q0 to nQ0. Missed error when converted to new format on April 16, 2007 from March 17, 2004. Differential DC Characteristics Table - replaced NOTE 1 with new note. AC Characteristics Table - added thermal note. Updated Differential Clock Input Interface section. Ordering Information Table - Part/Order Number - deleted “ICS” prefix. Updated Header/Footer throughout the document and contact page. 6/4/09

ICS8745BI Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.

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