863532

LC863532A SANYO | Alldatasheet

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Technical content

D2700 RM (IM) Shindo No.6844-1/19 Ver.1.00 00000 Preliminary Overview The LC863532/28/24/20/16A are 8-bit single chip microcontrollers with the following on-chip functional blocks: - CPU : Operable at a minimum bus cycle time of 0.424µs - On-chip ROM capacity Program ROM : 32K/28K/24K/20K/16K bytes CGROM : 16K bytes - On-chip RAM capacity : 512 bytes - OSD RAM : 352 × 9 bits - Closed-Caption TV controller and the on-screen display controller - Four channels × 6-bit AD Converter - Three channels × 7-bit PWM - Two channels × 16-bit timer/counter, 14-bit base timer - IIC-bus compliant serial interface circuit (Multi-master type) - ROM correction function - 12-source 8-vectored interrupt system - Integrated system clock generator and display clock generator Only one X’tal oscillator (32.768kHz) for PLL reference is used for both generators TV control and the Closed Caption function All of the above functions are fabricated on a single chip. Note : This product includes the IIC bus interface circuit. If you intend to use the IIC bus interface, please notify us of this in advance of our receiving your program ROM code order. Purchase of SANYO IIC components conveys a license under the Philips IIC Patents Rights to use these components in an IIC system, provided that the system conforms to the IIC Standard Specification as defined by Philips. Trademarks IIC is a trademark of Philips Corporation. 8-Bit Single-Chip Microcontroller LC863532A/28A/24A/20A/16A Ordering number : ENN*6844 CMOS IC

No.6844-2/19

Features

(1) Read-Only Memory (ROM) : 32768 × 8 bits / 28672 × 8 bits / 24576 × 8 bits 20486 × 8 bits / 16384 × 8 bits for program 16128 × 8 bits for CGROM (2) Random Access Memory (RAM) : 384 × 8 bits (working area) 128 × 8 bits (working or ROM correction function) 352 × 9 bits (for CRT display) (3) OSD functions - Screen display : 36 characters × 16 lines (by software) - RAM : 352 words (9 bits per word) Display area : 36 words × 8 lines Control area : 8 words × 8 lines - Characters Up to 252 kinds of 16 × 32 dot character fonts (4 characters including 1 test character are not programmable) Each font can be divided into two parts and used as two fonts (Ex. 16 × 16 dot character font × 2) At least 111 characters need to be divide between a 16 ×18 dot and 8 × 9 dot character font to display the caption fonts. - Various character attributes Character colors : 16 colors (analog mode: lv p-p output) / 8 colors (digital/mode) Character background colors : 16 colors (analog mode: lv p-p output) / 8 colors (digital/mode) Fringe / shadow colors : 16 colors (analog mode: lv p-p output) / 8 colors (digital/mode) Full screen colors : 16 colors (analog mode: lv p-p output) / 8 colors (digital/mode) Rounding Underline Italic character (slanting) - Attribute can be changed without spacing - Vertical display start line number can be set for each row independently (Rows can be overlapped) - Horizontal display start position can be set for each row independently - Horizontal pitch (bit 9 - 16) *1 and vertical pitch (bit-32) can be set for each row independently - Different display modes can be set for each row independently Caption  Text mode / OSD mode 1 / OSD mode 2 (Quarter size) / Simplifed graphic mode - Ten character sizes *1 - Shuttering and scrolling on each row - Simplified Graphic Display *1 Note : range depends on display mode : refer to the manual for details. (4) Bus Cycle Time / Instruction-Cycle Time Bus cycle time Instruction cycle time Clock divider System clock oscillation Oscillation Frequency Voltage 0.424µs 0.848 µs 1/2 Internal VCO (Ref : X’tal 32.768kHz) 14.156MHz 4.5V to 5.5V 7.5µs 15.0 µs 1/2 Internal RC 800kHz 4.5V to 5.5V (5) Ports - Input / Output Ports : 4 ports (24 terminals) Data direction programmable in nibble units : 1 port (8 terminals) (If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.) Data direction programmable for each bit individually : 3 ports (16 terminals)

No.6844-3/19 (6) AD converter - 4 channels × 6-bit AD converters (7) Serial interfaces - IIC-bus compliant serial interface (Multi-master type) Consists of a single built-in circuit with two I/O channels. The two data lines and two clock lines can be connected internally. (8) PWM output - 3 channels × 7-bit PWM (9) Timer - Timer 0 : 16-bit timer/counter With 2-bit prescaler + 8-bit programmable prescaler Mode 0 : Two 8-bit timers with a programmable prescaler Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter Mode 2 : 16-bit timer with a programmable prescaler Mode 3 : 16-bit counter The resolution of timer is 1 tCYC. - Timer 1 : 16-bit timer/PWM Mode 0 : Two 8-bit timers Mode 1 : 8-bit timer + 8-bit PWM Mode 2 : 16-bit timer Mode 3 : a variable-bit PWM (9 to 16 bits) In mode 0/1, the resolution of timer/PWM is 1 tCYC In mode 2/3, the resolution of timer/PWM is selectable by program; tCYC or 1/2 tCYC - Base timer Generate every 500ms overflow for a clock application (using 32.768kHz crystal oscillation for the base timer clock) Generate every 976µs, 3.9ms, 15.6ms, 62.5ms overflow (using 32.768kHz crystal oscillation for the base timer clock) Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler output of Timer 0 (10) Remote control receiver circuit (connected to the P73/INT3/T0IN terminal) - Noise rejection function - Polarity switching (11) Watchdog timer External RC circuit is required Interrupt or system reset is activated when the timer overflows (12) ROM correction function Max 128 bytes / 2 addresses

No.6844-4/19 (13) Interrupts - 12 sources 8 vectored interrupts 1. External Interrupt INT0 2. External Interrupt INT1 3. External Interrupt INT2, Timer/counter T0L (Lower 8 bits) 4. External Interrupt INT3, base timer 5. Timer/counter T0H (Upper 8 bits) 6. Timer T1H, Timer T1L 7. Vertical synchronous signal interrupt ( VS ), horizontal line ( HS) 8. IIC - Interrupt priority control Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high priority can be assigned to the interrupts from 3 to 8 listed above. For the external interrupt INT0 and INT1, low or highest priority can be set. (14) Sub-routine stack level - A maximum of 128 levels (stack is built in the internal RAM) (15) Multiplication/division instruction - 16 bits × 8 bits (7 instruction cycle times) - 16 bits / 8 bits (7 instruction cycle times) (16) 3 oscillation circuits - Built-in RC oscillation circuit used for the system clock - Built-in VCO circuit used for the system clock and OSD - X’tal oscillation circuit used for base timer, system clock and PLL reference (17) Standby function - HALT mode The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped. This mode can be released by the interrupt request or the system reset. - HOLD mode The HOLD mode is used to stop the oscillations; RC (internal), VCO, and X ’tal oscillations. This mode can be released by the following conditions.  Pull the reset terminal ( RES ) to low level.  Feed the selected level to either P70/INT0 or P71/INT1. (18) Package - MFP36S - DIP36S (19) Development tools - Flash EEPROM: LC86F3548A - Evaluation chip: LC863096 - Emulator: EVA86000 (main) + ECB863400 (evaluation chip board) + POD36-CABLE (cable) + POD36-DIP (for DIP36S) or POD36-MFP (for MFP36S)

No.6844-5/19 System Block Diagram Interrupt Control Standby Control Clock Generator X’tal VCO RC PLL IR PLA ROM PC ACC B Register C Register ALU PSW RAR RAM Stack Pointer Port 0 Watch Dog Timer ROM Correct Control XRAM Bus Interface Port 1 Port 3 Port 7 OSD Control Circuit VRAM CGROM IIC Timer 0 Base Timer ADC INT0-3 Noise Rejection Filter PWM Timer 1

No.6844-6/19 Pin Assignment Package Dimension (unit : mm) 3204 SANYO : MFP-36S Package Dimension (unit : mm) 3170 SANYO : DIP-36S P03 P02 P01 P00 P17 P16/PWM3 P15/PWM2 P14/PWM1 P73/INT3/T0IN P72/INT2/T0IN P71/INT1 P70/INT0 P32 P31 BL B G R P10/SDA0 P11/SCLK0 P12/SDA1 P13/SCLK1 VSS XT1 XT2 VDD P04/AN4 P05/AN5 P06/AN6 P07/AN7 RES FILT P33 P30 VS HS

No.6844-7/19 Pin Description Pin Description Table Terminal I/O Function Description Option VSS - Negative power supply XT1 I Input terminal for crystal oscillator XT2 O Output terminal for crystal oscillator VDD - Positive power supply RES I Reset terminal FILT O Filter terminal for PLL VS I Vertical synchronization signal input terminal HS I Horizontal synchronization signal input terminal R O Red (R) output terminal of RGB image output G O Green (G) output terminal of RGB image output B O Blue (B) output terminal of RGB image output BL O Fast blanking control signal Switch TV image signal and caption/OSD image signal Port 0 P00 to P07 I/O 8-bit input/output port, Input/output can be specified in nibble unit (If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.) Other functions AD converter input port (P04 to P07: 4 channels) Pull-up resistor provided/not provided Output Format CMOS/Nch-OD Port 1 8-bit input/output port Input/output can be specified for each bit (programmable pull-up resister provided) Other functions P10 P11 P12 P13 P14 P15 P16 P17 IIC0 data I/O IIC0 clock output IIC1 data I/O IIC1 clock output PWM1 output PWM2 output PWM3 output Timer 1 (PWM) output P10 to P17 I/O Output Format CMOS/Nch-OD Port 3 P30 to P33 I/O 4-bit input/output port Input/output can be specified for each bit (CMOS output/input with programmable pull-up resister)

No.6844-8/19 Terminal I/O Function Description Option Port 7 4-bit input/output port Input or output can be specified for each bit P70: I/O with programmable pull-up resister P71 to P73: CMOS output/input with programmable pull-up resister Other function P70 P71 P72 P73 INT0 input/HOLD release input/ Nch-Tr. output for wachdog timer INT1 input/HOLD release input INT2 input/Timer 0 event input INT3 input (noise rejection filter connected)/ Timer 0 event input Interrupt receiver format, vector addresses rising falling rising/ falling H level L level vector INT0 enable enable disable enable enable 03H INT1 enable enable disable enable enable 0BH INT2 enable enable enable disable disable 13H P70 P71 to P73 I/O INT3 enable enable enable disable disable 1BH Note: A capacitor of at least 10µF must be inserted between VDD and VSS when using this IC.  Output form and existance of pull-up resistor for all ports can be specified for each bit.  Programmable pull-up resistor is always connected regardless of port option, CMOS or N-ch open drain output in port 1.  Port status in reset Terminal I/O Pull-up resistor status at selecting CMOS output option Port 0 I Pull-up resistor OFF, ON after reset release Port 1 I Programmable pull-up resistor OFF

No.6844-9/19 1. Absolute Maximum Ratings at VSS=0V and Ta=25°C Ratings Parameter Symbol Pins Conditions VDD[V] min. typ. max. unit Supply voltage VDDMAX VDD -0.3 +7.0 Input voltage VI(1)  RES , HS , VS , CVIN -0.3 VDD+0.3 Output voltage VO(1) R, G, B, BL, FILT -0.3 VDD+0.3 Input/output voltage VIO Ports 0, 1, 3, 7 -0.3 VDD+0.3 V IOPH(1) Ports 0, 1, 3, 7 CMOS output For each pin. -4 Peak output current IOPH(2) R, G, B, BL CMOS output For each pin. ∑ IOAH(1) Ports 0, 1 The total of all pins. -20 ∑ IOAH(2) Ports 3, 7 The total of all pins. -10 High level output current Total output current ∑ IOAH(3) R, G, B, BL The total of all pins. -12 IOPL(1) Ports 0, 1, 3 For each pin. 20 IOPL(2) Port 7 For each pin. 15 Peak output current IOPL(3) R, G, B, BL For each pin. 5 ∑ IOAL(1) Ports 0, 1 The total of all pins. ∑ IOAL(2) Ports 3, 7 The total of all pins. Low level output current Total output current ∑ IOAL(3) R, G, B, BL The total of all pins. mA MFP36S 340 Maximum power dissipation Pdmax DIP36S Ta=-10 to +70°C 500 mW Operating temperature range Topg -10 +70 Storage temperature range Tstg -55 +125

No.6844-10/19 2. Recommended Operating Range at Ta=-10°C to +70°C, VSS=0V Ratings Parameter Symbol Pins Conditions VDD[V] min. typ. max. unit VDD(1) 0.844µs ≤ tCYC ≤ 0.852µs 4.5 5.5 Operating supply voltage range VDD(2) VDD 4µs ≤ tCYC ≤ 400µs 4.5 5.5 Hold voltage VHD VDD RAMs and the registers data are kept in HOLD mode. 2.0 5.5 VIH(1) Port 0 Output disable 4.5 to 5.5 0.6VDD VDD VIH(2) Ports 1,3 (Schumitt) Port 7 (Schumitt) port input/interrupt  HS , VS , RES (Schumitt) Output disable 4.5 to 5.5 0.75VDD VDD High level input voltage VIH(3) Port 70 Watchdog timer input Output disable 4.5 to 5.5 VDD-0.5 VDD VIL(1) Port 0 Output disable 4.5 to 5.5 VSS 0.2VDD VIL(2) Ports 1,3 (Schumitt) Port 7 (Schumitt) port input/interrupt  HS , VS , RES (Schumitt) Output disable 4.5 to 5.5 VSS 0.25VDD Low level input voltage VIL(3) Port 70 Watchdog timer input Output disable 4.5 to 5.5 VSS 0.6VDD V tCYC(1) All functions operating tCYC(2) AD converter operating OSD is not operating 4.5 to 5.5 0.844 30 Operation cycle time tCYC(3) OSD, AD converter is not operating 4.5 to 5.5 0.844 400 µs Oscillation frequency range FmRC Internal RC oscillation

No.6844-11/19 3. Electrical Characteristics at Ta=-10°C to +70°C, VSS=0V Ratings Parameter Symbol Pins Conditions VDD[V] min. typ. max. unit IIH(1) Ports 0, 1, 3, 7 Output disable Pull-up MOS Tr. OFF VIN=VDD (including the off- leak current of the output Tr.) 4.5 to 5.5 1 High level input current IIH(2)  RES  HS , VS VIN=VDD 4.5 to 5.5 1 IIL(1) Ports 0, 1, 3, 7 Output disable Pull-up MOS Tr. OFF VIN=VSS (including the off- leak current of the output Tr.) 4.5 to 5.5 -1 Low level input current IIL(2)  RES  HS , VS VIN=VSS 4.5 to 5.5 -1 µA VOH(1) CMOS output of ports 0,1,3,71-73 IOH=-1.0mA 4.5 to 5.5 VDD-1 High level output voltage VOH(2) R, G, B, BL IOH=-0.1mA R.G.B: digital mode 4.5 to 5.5 VDD-0.5 VOL(1) Ports 0,1,3,71-73 IOL=10mA 4.5 to 5.5 1.5 VOL(2) Ports 0,3,71-73 IOL=1.6mA 4.5 to 5.5 0.4 VOL(3) R, G, B, BL Port 1 IOL=3.0mA R.G.B: digital mode 4.5 to 5.5 0.4 Low level output voltage VOL(4) Port 70 IOL=1mA 4.5 to 5.5 0.4 V Pull-up MOS Tr. resistance Rpu Ports 0, 1, 3, 7 VOH=0.9VDD 4.5 to 5.5 13 38 80 kΩ Bus terminal short circuit resistance (SCL0-SCL1, SDA0-SDA1) RBS P10-P12 P11-P13 4.5 to 5.5 130 Ω Hysteresis voltage VHIS Ports 1, 3, 7  RES  HS , VS Output disable 4.5 to 5.5 0.1VDD V Pin capacitance CP All pins f=1MHz Every other terminals are connected to VSS. Ta=25°C 4.5 to 5.5 10 pF

No.6844-12/19 4. IIC Input/Output Conditions at Ta=-10°C to +70°C, VSS=0V Standard High speed Parameter Symbol min. max. min. max. unit SCL Frequency f SCL 0 100 0 400 kHz BUS free time between stop - start t BUF 4.7 - 1.3 - µs HOLD time of start, restart condition t HD;STA 4.0 - 0.6 - µs L time of SCL t LOW 4.7 - 1.3 - µs H time of SCL t HIGH 4.0 - 0.6 - µs Set-up time of restart condition t SU;STA 4.7 - 0.6 - µs HOLD time of SDA t HD;DAT 0 - 0 0.9 µs Set-up time of SDA t SU;DAT 250 - 100 - ns Rising time of SDA, SCL t R - 1000 20+0.1Cb 300 ns Falling time of SDA, SCL t F - 300 20+0.1Cb 300 ns Set-up time of stop condition t SU;STO 4.0 - 0.6 - µs Refer to figure 7 (Note) Cb : Total capacitance of all BUS (unit : pF) 5. Pulse Input Conditions at Ta=-10°C to +70°C, VSS=0V Ratings Parameter Symbol Pins Conditions VDD[V] min. typ. max. unit tPIH(1) tPIL(1) INT0, INT1 INT2/T0IN Interrupt acceptable Timer0-countable 4.5 to 5.5 1 tPIH(2) tPIL(2) INT3/T0IN (1 tCYC is selected for noise rejection clock.) Interrupt acceptable Timer0-countable 4.5 to 5.5 2 tPIH(3) tPIL(3) INT3/T0IN (16 tCYC is selected for noise rejection clock.) Interrupt acceptable Timer0-countable 4.5 to 5.5 32 tPIH(4) tPIL(4) INT3/T0IN (64 tCYC is selected for noise rejection clock.) Interrupt acceptable Timer0-countable 4.5 to 5.5 128 t CYC tPIL(5) RES Reset acceptable 4.5 to 5.5 200 High/low level pulse width tPIH(6) tPIL(6) HS , VS Display position controllable (Note) The active edge of HS and VS must be apart at least 1 t CYC. Refer to figure 6. 4.5 to 5.5 8 µs Rising/falling time tTHL tTLH HS Refer to figure 6. 4.5 to 5.5 500 ns

No.6844-13/19 6. AD Converter Characteristics at Ta=-10°C to + 70°C, VSS=0V Ratings Parameter Symbol Pins Conditions VDD[V] min. typ. max. unit Resolution N 6 bit Absolute precision ET (Note) ±1 LSB Conversion time tCAD Vref selection to conversion finish 1 bit conversion time = 2 × Tcyc 1.69 µs Analog input voltage range VAIN VSS VDD V IAINH VAIN=VDD 1 Analog port input current IAINL AN4 - AN7 VAIN=VSS 4.5 to 5.5 µA (Note) Absolute precision does not include quantizing error (1/2LSB). 7. Analog Mode RGB Characteristics at Ta=-10°C to +70°C, VSS=0V Ratings Parameter Symbol Pins Conditions VDD[V] min. typ. max. unit Low level output 0.45 0.5 0.55 Intensity output 0.90 1.0 1.10 Analog output voltage R.G.B Analog output mode Hi lebel output 1.35 1.5 1.65 V Time setting R.G.B 70% 10pf load 5.0 50 ns

No.6844-14/19 8. Sample Current Dissipation Characteristics at Ta=-10°C to +70°C, VSS=0V The sample current dissipation characteristics is the measurement result of Sanyo provided evaluation board when the recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally. The currents through the output transistors and the pull-up MOS transistors are ignored. Ratings Parameter Symbol Pins Conditions VDD[V] min. typ. max. unit IDDOP(1) VDD FmX’tal=32.768kHz X’tal oscillation System clock : VCO VCO for OSD operating OSD is Digital mode Internal RC oscillation stops 4.5 to 5.5 14 25 IDDOP(2) VDD FmX’tal=32.768kHz X’tal oscillation System clock : VCO VCO for OSD operating OSD is Analog mode Internal RC oscillation stops 4.5 to 5.5 23 37 mA Current dissipation during basic operation (Note 3) IDDOP(3) VDD FmX’tal=32.768kHz X’tal oscillation System clock : X’tal VCO for system VCO for OSD, internal RC oscillation stop Data slicer, AD converters stop 4.5 to 5.5 100 300 µA IDDHALT(1) VDD HALT mode FmX’tal=32.768kHz X’tal oscillation System clock : VCO VCO for OSD stops Internal RC oscillation stops 4.5 to 5.5 5 10 mA IDDHALT(2) VDD HALT mode FmX’tal=32.768kHz X’tal oscillation VCO for system stops VCO for OSD stops System clock : Internal RC 4.5 to 5.5 360 1000 Current dissipation in HALT mode (Note 3) IDDHALT(3) VDD HALT mode FmX’tal=32.768kHz X’tal oscillation VCO for system stops VCO for OSD stops System clock : X’tal 4.5 to 5.5 40 200 µA Current dissipation in HOLD mode (Note 3) IDDHOLD VDD HOLD mode All oscillation stops. 4.5 to 5.5 0.05 20 µA (Note 3) The currents through the output transistors and the pull-up MOS transistors are ignored.

No.6844-15/19 Recommended Oscillation Circuit and Sample Characteristics The sample oscillation circuit characteristics in the table below is based on the following conditions:

• Recommended circuit parameters are verified by an oscillator manufacturer using a Sanyo provided oscillation evaluation board.
• Sample characteristics are the result of the evaluation with the recommended circuit parameters connected externally. Recommended oscillation circuit and sample characteristics (Ta = -10 to +70°C) Recommended circuit parameters Oscillation stabilizing time Notes Frequency Manufacturer Oscillator C1 C2 Rf Rd Operating supply voltage range typ. max Notes The oscillation stabilizing time period is the time until the VCO oscillation for the internal system becomes stable after the following conditions. (Refer to Figure 2.) 1. The VDD becomes higher than the minimum operating voltage after the power is supplied. 2. The HOLD mode is released. The sample oscillation circuit characteristics may differ applications. For further assistance, please contact with oscillator manufacturer with the following notes in your mind.
• Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the oscillation frequency on the production board.
• The above oscillation frequency and the operating supply voltage range are based on the operating temperature of -10 °C to +70°C. For the use with the temperature outside of the range herein, or in the applications requiring high reliability such as car products, please consult with oscillator manufacturer.
• When using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with Sanyo sales personnel. Since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed with low gain in order to reduce the power dissipation, refer to the following notices.
• The distance between the clock I/O terminal (XT1 terminal XT2 terminal) and external parts should be as short as possible.
• The capacitors’ VSS should be allocated close to the microcontroller’s GND terminal and be away from other GND.
• The signal lines with rapid state changes or with large current should be allocated away from the oscillation circuit. Figure 1 Recommended oscillation circuit. Rd X’tal XT2 XT1 Rf

No.6844-16/19 <Reset time and oscillation stabilizing time> <HOLD release signal and oscillation stabilizing time> Figure 2 Oscillation stabilizing time Power supply RES Internal RC Resonator Oscillation XT1,XT2 VCO for system Operation mode Reset time VDD VDD limit Unfixed Instruction execution mode Reset tmsVCO stable tmsVCO stable Valid Instruction execution mode HOLD HOLD release signal XT1,XT2 VCO for system Operation mode Internal RC Resonator Oscillation

No.6844-19/19 memo : PS