Logic IC

85C51SND3B1

ATMEL Corporation

Single-Chip Digital Audio Decoder - Encoder with USB 2.0 Interface

Manufacturer: ATMEL Corporation

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Technical content

Features

Audio Processor – Proprietary Digital Signal Processor – MP3 (Full MPEG I/II-Layer 3) Decoder (1) – Windows Media ® Audio (WMA) Decoder (1) – OGG (Vorbis) Decoder (2) – WAV PCM Decoder/Encoder – ADPCM Decoder/Encoder (G726: 40, 32, 24, 16 Kbps) Audio Codec – 16-bit Stereo D/A Converters(3) – Headphone Amplifier with Analog Volume Control(3) – Microphone Pre-Amplifier with Bias Control – 16-bit Mono A/D Converter: Microphone or Line Inputs Recording – Stereo Lines Input for FM Playback or Mono Recording – Baseband Sound Processor with Digital Volume Control, Bass, Medium, and Treble Control, Bass Boost and Virtual Surround Effects Digital Audio DAC Interface –P C M / I2S Format Compatible USB Rev 2.0 Controller – High Speed Mode (480 Mbps) – Full Speed Mode (12 Mbps) – On The Go Full Speed Mode Data Flow Controller – 16-bit Multimedia Bus with 2 DMA Channels for high speed transfer with USB Nand Flash Controller – Up to four Memories with Page Size: 512B, 1KB, 2KB or 4KB – Built-in ECC and Hardware Write Protection – xD-Picture Card™ and SmartMedia ® Card Interface MultiMediaCard® Controller – MultiMediaCard 1-bit / 4-bits Modes (V4.0 compatible) – Secure Digital Card 1-bit / 4-bit Modes Man Machine Interface – Glueless Generic LCD Interface – Keyboard Interface Remote Controlled / Streaming – PSI I80 Slave Interface (EBI Compatible) up to 6Mbyte/s – SPI Master and Slave Modes – Full Duplex UART with Baud Rate Generator up to 6 Mbit/s (Rx, Tx, RTS, CTS) Control Processor – Enhanced 8-bit MCU C51 Core (FMAX = 24 MHz) – 64K Bytes of Internal RAM for application code and data – Boot ROM Memory: Secured Nand Flash Boot Strap (standard), USB Boot Loader – Two 16-bit Timers/Counters – Hardware Watchdog Timer Power Management – 1.8V 40 mA Single AAA or AA Battery Powered(4) – Direct USB VBUS Supply – 3V - 50 mA Regulator Output – 1.8V - 50 mA Regulator Output – Battery Voltage Monitoring – Power-on Reset – Software Programmable MCU Clock – Idle, Power-Down, Power-Off Modes On Chip Debug Operating Conditions – Supply 0.9V to 5V – 25 mA Typical Operating at 25°C (estimation to be confirmed) – Temperature Range: -40°C to +85°C Single-Chip Digital Audio Decoder - Encoder with USB 2.0 Interface AT85C51SND3B1 AT85C51SND3B2 AT85C51SND3B3 Preliminary

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7632A–MP3–03/06 Packages – LQFP100, BGA100, Dice Notes: 1. See Ordering Information 2. Future product 3. AT85C51SND3B2 & AT85C51SND3B3 only 4. AT85C51SND3B3 only Description Digital Music Players, Mobile Phones need ready to use low-cost solutions for very fast time to market. The AT85C51SND3Bx with associated firmware embeds in a single chip all features, hardware and software, for Digital Music Players, Mobile Phones and Car Audio Systems: MP3 decoder, WMA decoder, Display interface, serial interface, parallel interface, USB high speed and USB host. Close to a plug and play solution for most applications, the AT85C51SND3Bx drastically reduces system development for the best time to market. The AT85C51SND3Bx han dles full file system management with Nand Flash and Flash Cards, including full detection and operation of a thumb drive. The AT85C51SND3A is used either as a mas ter controller, or as a slave controller interfacing easily with most of the base-band or host processors available on the market. In addition to the MP3 and WMA format, the AT85C51SND3Bx associated firmware will also later support, the OGG format, basic MIDI features for low cost mobile phones and JPEG still pictures decoding. The AT85C51SND3B is ideally fitting mass production markets. The AT85C51SND3Bx includes Power Management with: 5V USB VBUS direct supply, Nand Flash or Flash Card can be supplied by the AT85C51SND3B at 1.8V or 3V. The AT85C51SND3Bx supports many applications including: mobile phones, music players, portable navigation, car audio, music in shopping centers, applications includ ing MMC/SD Flash Cards in Industrial applications. To facilitate custom applications with the AT85C51SND3Bx, a development kit AT85DVK-07 is available with hardware and firmware database. Key Features Firmware to support –M P 3 –W M A – ADPCM/WAV voice or line recording – and coming soon OGG, MIDI and JPEG Decoder Audio Codec – Internal DAC – FM inputs Memory Support – Up to 4x Nand-Flash – SD/MMC cards U S B – High Speed, Full Speed – OTG (reduced Host)

Figure 1. AT85C51SND3Bx Block Diagram

AT85C51SND3B2 & AT85C51SND3B3 only

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7632A–MP3–03/06

Application Information

The AT85C51SND3Bx allow design of 2 typical applications which differentiate by the power supply voltage: The Very Low Voltage System The player operates at 1.8V and allows very low power consumption. The Low Voltage System The player operates at 3V and allows low power consumption. Very Low Voltage 1.8V System Figure 2. Typical Very Low Voltage 1.8V Application

Figure 3. Typical Low Voltage 3V Application

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Figure 4. AT85C51SND3Bx 100-pin QFP Package

Leave these pins unconnected for AT85C51SND3B1 product

Table 2. Ports Signal Description to be reset by connecting a capacitor between this pin and VSS . returns the chip to normal operation. reaches its time-out period. P2 is an 8-bit bidirectional I/O port with internal pull-ups. P3 is a 7-bit bidirectional I/O port with internal pull-ups.

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Table 3. Timer 0 and Timer 1 Signal Description P4 is a 7-bit bidirectional I/O port with internal pull-ups. P5 is a 4-bit bidirectional I/O port with internal pull-ups.

Table 6. Nand Flash / SmartMedia Card Controller Signal Description pin. X1 is the clock source for internal timing. this pin. If an external oscillator is used, leave X2 unconnected. signal and SDDAT3:1 are not used and can be reused as I/O ports. the card is present in its slot. Note: This signal is generated by the SD/MMC card connector. indicates the card is write protected. Note: This signal is generated by the SD/MMC card connector.

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7632A–MP3–03/06 USB Controller Table 7. USB Controller Signal Description NFCLE O Command Latch Enable Signal Asserted high during command write cycle. - NFRE O Read Enable Signal Read signal asserted low during NF/SMC read operation. - NFWE O Write Enable Signal Write signal asserted low during NF/SMC write operation. - NFCE0 O Nand Flash 0 Chip Enable NFCE0 is active low and is asserted by the nand flash controller each time it makes access to the device 0. NFCE1 SMLCK O I Nand Flash 1 Chip Enable NFCE1 is active low and is asserted by the nand flash controller each time it makes access to the selected device. SmartMediaCard/xD-Picture Card Write Lock Signal SMLCK is the card write protected input. A low level on this pin indicates the card is write protected. Note: When used as SMLCK input, pad has internal pull-up. P4.4 NFCE2 SMINS O I Nand Flash 2 Chip Enable NFCE2 is active low and is asserted by the nand flash controller each time it makes access to the selected device. SmartMediaCard/xD-Picture Card Insertion Signal SMINS is the card presence signal. A low level on this input indicates the card is present in its slot. Note: When used as SMINS input, pad has internal pull-up. P4.5 NFCE3 SMCE O Nand Flash 3 Chip Enable NFCE3 is active low and is asserted by the nand flash controller each time it makes access to the selected device. SmartMediaCard/xD-Picture Card Chip Enable SMCE is active low and is asserted by the nand flash controller each time it makes access to the card. P4.6 NFWP O Write Protect Signal NFWP is the Nand Flash / SmartMediaCard/xD-Picture Card write protect signal. This signal is active low and is set to low during reset in order to protect the memory against parasitic writes. Signal Name Type Description Alternate Function Signal Name Type Description Alternate Function DPF I/O USB Full Speed Positive Data Upstream Port - DMF I/O USB Full Speed Minus Data Upstream Port - DPH I/O USB High Speed Plus Data Upstream Port - DMH I/O USB High Speed Minus Data Upstream Port - UVCON O USB VBUS Control line UVCON is used to control the external VBUS power supply ON or OFF. Note: This output is requested for OTG mode. P3.6

Table 9. Audio Codec Description This pin monitors the function of the OTG device. Note: This input is requested for OTG mode. Connect this pin to external resistor and capacitor.

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Table 12. SIO Signal Description Low Voltage system: connect this pin to LVDD pin. High voltage system: connect this pin to external +3V power supply. Low Voltage system: connect this pin to LVSS pin. High voltage system: connect this pin to external +3V ground. 8-bit bidirectional data bus. Read signal asserted low during external host read operation. Write signal asserted low during external host write operation. Select signal asserted low during external host read or write operation. Address signal asserted during external host read or write operation. When in master mode, MISO receives data from the slave peripheral. When in slave mode, MISO outputs data to the master controller. When in master mode, MOSI outputs data to the slave peripheral. When in slave mode, MOSI receives data from the master controller. When in master mode, SCK outputs clock to the slave peripheral. When in slave mode, SCK receives clock from the master controller. When in controlled slave mode, SS enables the slave mode. serial I/O modes 1, 2 and 3.

Table 14. LCD Interface Signal Description serial I/O modes 1, 2 and 3. Asserted low by hardware when SIO is ready to receive data. Asserted low by external hardware when SIO is allowed to send data. 8-bit bidirectional data bus. 8080: Read signal asserted low during display read access. 6800: Enable signal asserted high during display access. 8080: Write signal asserted low during display write access. Select signal asserted low during display access. Address signal asserted during display access. Connect low ESR inductance to DCLI and BVDD.

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7632A–MP3–03/06 OCD Interface Table 16. OCD Signal Description BVSS GND Battery Ground Connect this pin to the negative pin of the battery. - LVDD PWR Low Voltage DC-DC Power Supply output This pin outputs +1.8V typ. from internal DC-DC (battery powered).- RLVDD PWR Low Voltage Regulator Power Supply Output This pin outputs +1.8V typ. from internal regulator (USB powered or +3V external power supply). Connect this pin to LVDD incase of internal DC-DC usage. HVDD PWR High Voltage Power Supply This pin outputs +3V typ. from internal regulator (USB powered). Connect this pin to +3V external power supply. VSS GND Power Ground Connect this pin to the system ground. - CVSS GND Core Ground Connect this pin to VSS pin. - IOVDD PWR Input/Output Supply voltage Connect this pin to LVDD or HVDD pin. - IOVSS GND Input/Output Circuit Ground Connect this pin to VSS pin. - Signal Name Type Description Alternate Function Signal Name Type Description Alternate Function OCDR I On Chip Debug Receive Input OCDR receives data. - OCDT I/O On Chip Debug Transmit Output OCDT transmits data. ISP

7632A–MP3–03/06 Internal Pin Structure Table 17. Detailed Internal Pin Structure Circuit(1) Type Pins Input/Output RST Input/Output P0.7:0 P1.7:0 P2.7:0 P3.5:0 P4.6:0 P5.3:0 OCDT Input/Output P3.7:6 Input KIN3:0 SDINS SDLCK SMINS SMLCK TST ISP UID INT0 INT1 RXD OCDR Input SWR SA0 SRD SCS SS Input/Output NFD7:0 SD7:0 LD7:0 SDCMD SDDAT3:0 MISO MOSI R RST IOVSS N IOVDD N Ps IOVDD IOVDD2 osc Latch Output periods Pm Pw IOVDD IOVSS N Ps HVDD HVDD2 osc Latch Output periods Pm Pw HVDD IOVSS Pm Pw IOVSS IOVDDIOVDD N P IOVSS IOVDD

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7632A–MP3–03/06 Output SDCLK SCK NFCE3:0 NFCLE NFALE NFWE NFRE NFWP SMCE DSEL DDAT DCLK OCLK LWR /LE LA0/LRS LRD /LRW LCS UVCON TXD Input/Output DPF DMF Input/Output DPH DMH Input DCPWR (2) - DCLI(2) Circuit(1) Type Pins N P IOVSS IOVDD DPF DMF DPH DMH BVDD R DCP N P CVSS LVDD

7632A–MP3–03/06 Notes: 1. For information on resistor value, input/output levels, and drive capability, refer to Section “DC Characteristics”, page 241. 2. AT85C51SND3B3 only 3. AT85C51SND3B2 & AT85C51SND3B3 only Output MICBIAS Input MICIN LINR LINL Output OUTR (2) OUTL (2) Circuit(1) Type Pins AVSS AVSS

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as well as power failure detector and reset circuitry. ate from either USB power supply (5V nominal) or from an external 3 volts supply. Figure 5. Power Supply Diagram Note: 1. External connection mandatory when 1.8V DC-DC is used. pin. Its nominal voltage output is 3V. through RLVDD power pin. Its nominal voltage output is 1.8V. characteristics are specified in the section “DC characteristics”.

1.8 V DC-DC

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version range as detailed in Table 18. Table 18. Battery Voltage Value tional delay of 16 cycles is required before lauching any conversion. VBERR is cleared and conversion value is set in VB4:0 according to Table 18. VBERR is set and value reported by VB4:0 is indeterminate. to an hardware bit: PMLCK in PCON. event. It is cleared by software after exiting power reduction mode. and PD bits in PCON can not be set and idle or power down modes are not entered. Figure 9. Power Reduction Controller Block Diagram

7632A–MP3–03/06 Idle Mode Idle mode is a power reduction mode that reduces the power consumption. In this mode, program execution halts. Idle mode freezes the clock to the CPU at known states while the peripherals continue to be clocked (refer to Section “System Clock Generator”, page 29). The CPU status before entering Idle mode is preserved, i.e., the program counter and program status word register retain their data for the duration of Idle mode. The contents of the SFRs and RAM are also retained. Entering Idle Mode To enter Idle mode, the user must set the IDL bit in PCON register while PMLCK is cleared. The AT85C51SND3B enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed. Note: If IDL bit and PD bit are set simultaneously, the AT85C51SND3B enter Power-down mode. Then it does not go in Idle mode when exiting Power-down mode. Exiting Idle Mode There are 2 ways to exit Idle mode: 1. Generate an enabled interrupt. – Hardware clears IDL bit in PCON register which restores the clock to the CPU. Execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Idle mode. The general- purpose flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt occurred during normal operation or during Idle mode. When Idle mode is exited by an interrupt, the interrupt service routine may examine GF1 and GF0. 2. Generate a reset. – A logic high on the RST pin clears IDL bit in PCON register directly and asynchronously. This restores the clock to the CPU. Program execution momentarily resumes with the instruction immediately following the instruction that activated the Idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the AT85C51SND3B and vectors the CPU to address 0000h. Note: During the time that execution resumes, the internal RAM cannot be accessed; however, it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction immediately following the instruction that activated Idle mode should not write to a Port pin or to the external RAM. Power-down Mode The Power-down mode places the AT85C51SND3B in a very low power state. Power- down mode stops the oscillator and freezes all clocks at known states (refer to the Section “Oscillator”, page 27). The CPU status prior to entering Power-down mode is preserved, i.e., the program counter, program status word register retain their data for the duration of Power-down mode. In addition, the SFRs and RAM contents are preserved. Entering Power-down Mode To enter Power-down mode, set PD bit in PCON register while PMLCK is cleared. The AT85C51SND3B enters the Power-down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed. Exiting Power-down Mode There are 2 ways to exit the Power-down mode: 1. Generate an enabled external interrupt. – The AT85C51SND3B provides capability to exit from Power-down using INT0, INT1, and KIN3:0 inputs. In addition, using KIN input provides high or low level exit capability (see Section “Keyboard Interface”, page 239). Hardware clears PD bit in PCON register which starts the oscillator and restores

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pressed. In both cases, execution resumes with the interrupt service routine. execution will only resume when the interrupt is de-asserted.

Exit from power-down by external interrupt does not affect the SFRs nor the internal

Figure 10. Power-down Exit Waveform Using INT1:0 Figure 11. Power-down Exit Waveform Using KIN3:0 Note: 1. KIN3:0 can be high or low-level triggered. Power-down mode should not write to a Port pin or to the external RAM.

Exit from power-down by reset redefines all the SFRs, but does not affect the internal

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Figure 13. Reset Circuitry and Power-On Reset periods is mode independent (X2 or X1). tor must be added as shown in Figure 14. Figure 14. Reset Circuitry for WDT Reset-out Usage

Table 20. PCON Register

7 VBCEN

Set to enable the clock of the battery monitoring. Clear to disable the clock of the battery monitoring.

6 VBPEN

Set to power the battery monitoring. Clear to unpower the battery monitoring.

5 DCPBST

Set to disable DC-DC high power boost mode. Clear to enable DC-DC high power boost mode.

4 GF0

3 DCEN

2 PMLCK

Clear to unlock power-down or Idle mode entry. Cleared by hardware when an interrupt or reset occurs. Set to activate the Power-down mode when PMLCK is cleared. If IDL and PD are both set, PD takes precedence.

0 IDL

Cleared by hardware when an interrupt or reset occurs. Set to activate the Idle mode when PMLCK is cleared. If IDL and PD are both set, PD takes precedence. Table 21. PSTA Register

7 UVDET

Set by hardware when 5V is detected on UVDD pin. Cleared by hardware when 5V is not detected on UVDD pin.

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Note: 1. Reset value depends on the power supply presence and on the internal reset source.

6 HVDET

Set by hardware when 3V is detected on HVDD pin. Cleared by hardware when 3V is not detected on HVDD pin. The value of these bits is always 0. Do not set these bits.

2 WDTRST

Must be cleared by software at power-up.

1 EXTRST

Set by hardware when the external RST pin is asserted (warm reset). Must be cleared by software at power-up.

0 PFDRST

Must be cleared by software at power-up. Table 22. VBAT Register

7 VBEN

Set to enable the battery monitoring.

6 VBERR Battery Monitor Error Flag

Set by hardware when conversion is out of min/max values. The value read from this bit is always 0. Do not set this bit. Refer to Table 18 for voltage value correspondence.

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Figure 16. Crystal Connection The clock generation is enabled by setting CKGENE bit in CKEN (see Table 32). detailed in the following sections. Figure 17. Clock Generator Block Diagram and Symbol

480 MHz PLL The AT85C51SND3Bx PLL is based on a Phase Frequency Comparator and Lock

in order to support many oscillator frequencies and to minimize the PLL output jitter.

480 MHz PLLOSC

60 MHz

48 MHz

40 MHz

30 MHz

24 MHz

20 MHz

16 MHz

120 MHz

Figure 18. PLL Block Diagram and Symbol Table 24. PLL Reverse Clock Selection programming values and reverse frequency depending on some oscillator frequency. Table 25. PLL Programming Values versus Input Frequency bits in CKSEL (see Table 34) according to Table 26. Section “Power Management”, page 18.

480 MHz

12 MHz

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Figure 19. System Clock Generator Block Diagram and Symbols Table 26. System Clock Selection 2 while in X2 mode, it is the oscillator frequency. Figure 20. Mode Switching Waveforms Figure 21 and is based on a frequency selector. Frequency is enabled by setting DNFCKEN bit in CKEN.

00 FOSC (default)

Figure 21. DFC/NFC Clock Generator Block Diagram and Symbol Table 27. DFC/NFC Clock Selection quency selector followed by a frequency divider. Frequency division is done using MMCDIV4:0 bits in MMCCLK according to Table 29. clock generation by setting MMCKEN bit in CKEN. phase), FOSC selection can be divided by 2. Figure 22. MMC Clock Generator Block Diagram and Symbol

000 FOSC (default)

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Table 28. MMC Clock Selection Table 29. MMC Clock Divider rate when PLL is enabled. SIO clock is enabled by SIOCKEN bit in CKEN register. Figure 23. SIO Clock Generator Block Diagram and Symbol Table 30. SIO Clock Selection

111 FOSC ÷ 2

00000 Disabled (no clock out)

0 FOSC

Table 31. CKCON Register The value read from this bit is always 0. Do not set this bit.

6 WDX2

Clear to select the peripheral clock as watchdog clock input (X2 dependent).

5 OSCAMP

Clear to enable the oscillator amplifier in case of crystal usage (default). Set this bits according to Table 23 to optimize power consumption.

2 T1X2

Clear to select the peripheral clock as timer 1 clock input (X2 dependent).

1 T0X2

Clear to select the peripheral clock as timer 0 clock input (X2 dependent). Set to select 6 clock periods per machine cycle (X2 mode, FCPU = FPER = FOSC ).

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Table 32. CKEN Register

7 CKGENE

Set to enable the clock generator. Clear to disable the clock generators.

6 PLLEN

Set to enable the 480 MHz PLL. Clear to disable the 480 MHz PLL. The value read from this bit is always 0. Do not set this bit.

4 PLOCK

Set by hardware when the PLL is locked. Cleared by hardware when the PLL is not locked.

3 MMCKEN

Set to enable the MMC controller Clock. Clear to disable the MMC controller Clock. The value read from this bit is always 0. Do not set this bit.

1 SIOCKEN

Set to enable the SIO Clock. Clear to disable the SIO Clock.

0 DNFCKEN

Set to enable the DFC/NFC Clock. Clear to disable the DFC/NFC Clock.

Table 33. CKSEL Register Refer to Table 27 for information on selected clock value. Refer to Table 24 for information on selected clock value.

2 SIOCKS SIO Clock Select Bit

Refer to Table 30 for information on divided clock value. Refer to Table 26 for information on divided clock value. Table 34. PLLCLK Register Table 35. MMCCLK Register Refer to Table 28 for information on selected clock value. Refer to Table 29 for information on divided clock value.

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accessible through the PPCON (Peripheral Pagination Control) register (see Table 37).

Setting one bit of PPCON using the setb instruction automatically clears the 7 oth-

By default, after reset selected page is page 0. Figure 24. SFR Pagination Block diagram Table 36. Page Selection Truth Table Table 37. PPCON Register The value read from these bits is always 0. Do not set these bits. Refer to Table 36 for page decoding information.

Table 38. Page Address Notation to Table 58. In these tables, the bit-addressable registers are identified by Note 1. Note: Available in AT85C51SND3B3 only. Table 39. C51 Core SFRs Table 40. Power and System Management Table 41. Clock Management Unit SFRs

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Table 42. Interrupt SFRs Table 43. I/O Port SFRs Table 44. Timer SFRs Table 45. RAM Interface

Table 46. Memory Management SFRs Table 47. Scheduler SFRs Table 48. Data Flow Controller SFRs Table 49. USB Controller SFRs

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Table 50. NFC SFRs

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Table 51. MMC Controller SFRs Table 52. Audio Controller SFRs

Note: Available in AT85C51SND3B2 & AT85C51SND3B3 only. Table 53. Audio Stream Codec SFRs Table 54. PSI Controller SFRs Table 55. SPI Controller SFRs Table 56. Serial I/O Port SFRs

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Table 57. LCD Interface SFRs Table 58. Keyboard Interface SFRs

Notes: 1. SFR registers with least significant nibble address equal to 0 or 8 are bit-addressable. Table 59. SFR Page 0: Addresses and Reset Values

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Note: 1. SFR registers with least significant nibble address equal to 0 or 8 are bit-addressable. Table 60. SFR Page 1: Addresses and Reset Values

Notes: 1. SFR registers with least significant nibble address equal to 0 or 8 are bit-addressable.

Available in AT85C51SND3B2 & AT85C51SND3B3 only.

Table 61. SFR Page 2: Addresses and Reset Values

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Notes: 1. SFR registers with least significant nibble address equal to 0 or 8 are bit-addressable.

SVERS reset value depends on the silicon version 1111 1011 for AT85C51SND3B product.

Table 62. SFR Page 3: Addresses and Reset Values

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Table 63. Register Bank Selection addresses in this area are 00h to 7Fh. Figure 26. Lower 128 Bytes Internal RAM Organization Section “Special Function Registers”, page 36. M E M C B A X ( s e e Table 65) for the code segment base address. M E M D B A X ( s e e Table 66) for the data segment base address. MEMXBAX (see Table 67) for the xdata segment base address. MEMCSX (see Table 68) for the code segment size. MEMXSX (see Table 69) for the code segment size. The data segment is not programmable in size as it is a fixed 256-byte segment.

4 Banks of

8 Registers

start-up. In this figure italicized address are the logical address within segments. Figure 27. Memory Segment Configuration Table 64. PSW Register

7 CY Carry Flag

Carry out from bit 1 of ALU operands.

6 AC Auxiliary Carry Flag

Carry out from bit 1 of addition operands.

5 F0 User Definable Flag 0

Refer to Table 63 for bits description.

2 OV Overflow Flag

Overflow set by arithmetic operations.

1 F1 User Definable Flag 1

Set when ACC contains an odd number of 1’s. Cleared when ACC contains an even number of 1’s.

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Table 65. MEMCBAX Register 17-bit CODE Base Address: X XXXX XXX0 0000 0000b. 512-byte alignment, no offset. Table 66. MEMDBAX Register 17-bit DATA Base Address: X XXXX XXX1 0000 0000b. 512-byte alignment with 256-byte offset. Table 67. MEMXBAX Register 17-bit CODE Base Address: X XXXX XXX0 0000 0000b. 512-byte alignment, no offset. Table 68. MEMCSX Register

Size is equals to (CSX+1) x 256 bytes. CODE sizes available: from 256 bytes to 64 Kbytes, by 256-byte steps. Table 69. MEMXSX Register Size is equals to (XSX+1) x 256 bytes. XDATA sizes available: from 256 bytes to 64 Kbytes, by 256-byte steps.

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are enabled or disabled by the system designer and may be manipulated dynamically. AT85C51SND3Bx, latch this event into a flag buffer. handler. A high priority causes the handler to set an interrupt flag. reloads the PC with the start address of a software service routine. and IEN1 registers (see Table 72 and Table 73). sources: IPH0, IPL0, IPH1 and IPL1 registers (see Table 74 to Table 77). ters (IPH0 and IPH1) and one bit in the Interrupt Priority Low registers (IPL0 and IPL1). Table 70. Priority Levels rupts is determined by an internal hardware polling sequence detailed in Table 71.

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Table 71. Priority Within Same Level

Figure 28. Interrupt Control System

58 AT85C51SND3Bx

must be de-asserted before the end of the interrupt service routine. level signals as detailed in Section “Exiting Power-down Mode”, page 21. Figure 29. INT1:0 Input Circuitry detailed information on these inputs, refer to Section “Keyboard Interface”, page 239. interrupts must hold the request pin low for at least 6 peripheral clock periods. Figure 30. Minimum Pulse Timings

Table 72. IEN0 Register Set to enable all interrupts. Clear to disable all interrupts. clearing its interrupt enable bit.

6 EAUP

Set to enable audio processor interrupt. Clear to disable audio processor interrupt.

5 EDFC

Set to enable data flow interrupt. Clear to disable data flow interrupt. Set to enable serial port interrupt. Clear to disable serial port interrupt.

3 ET1

Set to enable timer 1 overflow interrupt. Clear to disable timer 1 overflow interrupt.

2 EX1

Set to enable external interrupt 1. Clear to disable external interrupt 1.

1 ET0

Set to enable timer 0 overflow interrupt. Clear to disable timer 0 overflow interrupt.

0 EX0

Set to enable external interrupt 0. Clear to disable external interrupt 0.

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Table 73. IEN1 Register The value read from these bits is always 0. Do not set these bits.

5 EMMC

Set to enable MMC/SD interrupt. Clear to disable MMC/SD interrupt. Set to enable IDE interrupt. Clear to disable IDE interrupt.

3 ESPI

Set to enable SPI interrupt. Clear to disable SPI interrupt.

2 EPSI

Set to enable PSI interrupt. Clear to disable PSI interrupt. Set to enable Keyboard interrupt. Clear to disable Keyboard interrupt. Set this bit to enable USB interrupt. Clear this bit to disable USB interrupt.

Table 74. IPH0 Register The value read from this bit is indeterminate. Do not set this bit.