8408RPFB

8408 MAXWELL | Alldatasheet

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All data sheets are subject to change without notice (858) 503-3300- Fax: (858) 503-3301- www.maxwell.com Quad 8-Bit Multiplying CMOS 8408 ©2002 Maxwell Technologies All rights reserved. D/A Converter with Memory

08.20.02 REV 1

FEATURES:

• R AD-PAK® patented shielding against natural
• space radiation
• Total dose hardness: - equal to 100 krad (Si), depending upon orbit and space mission
• Package: - 28 pin R AD-PAK® Flat Pack
• Single Supply Ooperation (+5V)
• Four 8 Bit DACs in one 28 Pin Package
• D/As Matched to within 1%
• TTL/CMOS Compatable
• Four-Quadrant Multiplication DESCRIPTION: Maxwell Technologies’ 8408 is a monolithic quad 8-bit multi- plying digital-to-analog CMOS c onverter. Each DAC has its own reference input, feedback resistor, and onboard data latches that feature read/write capability. The readback func- tion serves as memory for t hose systems requiring self-diag- nostics. A common 8-bit TTL/CMOS compatible input port is used to load data into any of the four DAC data-latches. Control lines DS1 , DS2 and A/B determine which DAC will accept data. Data loading is similar to that of a RAMs write cycle. Data can be read back onto the same bus with control line R/W . The 8408 is a bus compatible with most 8-bit microprocessors, including the 6800, 8080, 8085, and Z80. The 8408 operates on a single +5 volt supply and dissipates less than 20 mW. The 8408 is manufactured using hi ghly stable, thin-film resis- tors on an advanced oxide-isolat ed, silicon-gate, CMOS pro- cess. The improved latch-up resi stant design eliminates the need for external protective Schottky diodes. Maxwell Technologies' patented R AD-PAK® packaging technol- ogy incorporates radiation shie lding in the microcircuit pack- age. It eliminates the need for box shielding while providing the required radiation shielding fo r a lifetime in orbit or space mission. In a GEO orbit, R AD-PAK provides greater than 100 krad (Si) radiation dose toleranc e. This product is available with screening up to Class S. Logic Diagram

TABLE 1. 8408 PINOUT DESCRIPTION

9 DB0 (LSB) Data Bit 0, least significant bit

16 DB 7 (MSB) Data Bit 7, most significant bit

17 A/B

18 R/W Read/Write

21 V REFD REF Voltage (D)

22 R FBD REF Feedback (D)

23 I OUT 1D Current Output (1D)

24 I OUT 2C/IOUT 2D Current Output (2C/2D)

25 I OUT 1C Current Output (1C)

26 R FBC REF Feedback (C)

27 V REFC REF Voltage (C)

28 DGND Digital Ground

TABLE 2. 8408 ABSOLUTE MAXIMUM RATINGS

TABLE 3. DELTA LIMITS TABLE 4. 8408 SPECIFICATIONS

4 CIN 1, 2, 3 -- -- 8 pF

TABLE 2. 8408 ABSOLUTE MAXIMUM RATINGS

TABLE 4. 8408 SPECIFICATIONS

5All data sheets are subject to change without notice ©2002 Maxwell Technologies All rights reserved. Quad 8-Bit Multiplying CMOS D/A Converter with Memory 8408

1. This is an end-point linearity specification. 2. Guaranteed to be monotonic over t he full operating temperature range. 3. ppm/°C of FSR (FSR = Full Scale Range = V REF -1 LSB). 4. Guaranteed by design. 5. All Digital Inputs = 0V; VREF = +10V. 6. Logic Inputs are MOS gates. Typical input current at +25°C is less than 10 nA. 7. From Digital Input to 90% of final analog output current. 8. Digital Inputs = 0V to V DD or VDD to 0V. 9. Extrapolated: ts (1/2 LSB) = tPD + 6.2 τ where τ = the measured first constant of the final RC decay. 10.See Timing Diagram 11. All Digital Inputs “0” or V DD. 12.All Digital Inputs VIH or VIL

FIGURE 1. TIMING DIAGRAM FIGURE 2. SUPPLY CURRENT VS. LOGIC LEVEL

7All data sheets are subject to change without notice ©2002 Maxwell Technologies All rights reserved. Quad 8-Bit Multiplying CMOS D/A Converter with Memory 8408 The 8408 combines four identical 8-bit CMOS DACs onto a single monolithic chip. Ea ch DAC has its own reference input, feedback resistor, and on-board data latches. It also features a read/write function that serves as an accessible memory location for digital-input data words. The DAC’s three-state readback drivers place the data word back onto the data bus. D/A CONVERTER SECTION Each DAC contains a highly stable, silicon-chromium, thin-film, R-2R resistor ladder network and eight pairs of current steering switches. These switches are in series with each ladder resistor and are single-pole, double-throw NMOS transistors; the gates of these transistor s are controlled by CMOS inverters. Fi gure 3 shows a simplified circuit of the R-2R resistor ladder section, and Figure 4 shows an approximate equivalent switch circuit. The current through each resistor leg is switched between IOUT 1 and IOUT 2. This maintains a constant current in each leg, regardless of the digital input logic states. Each transistor switch has a finite “O N” resistance that can introduce errors to the DAC’s specified performance. These resistances must be accounted for by making the voltage drop across each transistor equal to each other. This is done by binarily scaling the transistor’s “ON” resistance from the most significant bit (MSB) to the least significant bit (LSB). With 10 volts applied at the reference input, the current through the MSB switch is 0.5 mA, the next bit is 0.25 mA, etc.; this maintains a constant 10 mV drop across each switch and the converter’s accuracy is maintained. It also results in a constant resistance appearing at the DAC’s reference input terminal; this allows the DAC to be driven by a voltage or current source, ac or dc, of positive or negative polarity. Shown in Figure 5 is an equivalent output circuit for DAC A. The circuit is shown with all digital inputs high. The leak- age current source is the combination of surface and junction leakages to the substrate. The 1/256 current source rep- resents the constant 1-bit current drain through the ladder terminating resistor. The situation is reversed with all digital inputs low, as shown in Figure 6. The output capacitance is code dependent, and therefore, is modulated between the low and high values.

FIGURE 3. SIMPLIFIED D/A CIRCUIT OF 8408 FIGURE 4. N-CHANNEL CURRENT STEERING SWITCH FIGURE 5. EQUIVALENT DAC CIRCUIT (AII DIGITAL INPUTS HIGH)

FIGURE 6. EQUIVALENT DAC CIRCUIT (AII DIGITAL INPUTS LOW) load. The three state digital readback leakage-current is typically 5 nA. FIGURE 7. DIGITAL INPUT/OUTPUT STRUCTURE

10All data sheets are subject to change without notice ©2002 Maxwell Technologies All rights reserved. Quad 8-Bit Multiplying CMOS D/A Converter with Memory 8408

• All DACs in HOLD MODE.
• DAC A, B, C, or D individually selected (WRITE MODE).
• DAC A, B, C, or D individually selected (READ MODE).
• DACs A and C simultaneously selected (WRITE MODE).
• DACs B and D simultaneously selected (WRITE MODE). DAC Selection: Control inputs, DS1 , DS2, and A/B select which DAC can accept data from the input port (see Mode Selection Table). Mode Selection: Control inputs DS and R/W control the operating mode of the selected DAC. Write Mode: When the control inputs DS and R/W are both low, the selected DAC is in the write mode. The input data latches of the selected DAC are transparent, and its analog output responds to activity on the data inputs DB0–DB7. Hold Mode: The selected DAC latch retains the data that was present on the bus line just prior to DS or R/W going to a high state. All analog outputs remain at the values corresponding to the data in their respective latches. Read Mode: When DS is low and R/W is high, the selected DAC is in the read mode, and the data held in the appro- priate latch is put back onto the data bus.

TABLE 4. MODE SELECTION TABLE inputs high. Low temperature coefficient (approximately 50 ppm/°C) resistors or trimmers should be selected if used. tions, R1 through R4 are not required, and the maximum gain error will then be that of the DAC. nonlinearity term at the amplifier’s output which can have a maximum value of 0.67 times the amplifier’s offset voltage. ing when using high speed op amps. an attenuator with an ac input voltage.

TABLE 5. UNIPOLAR BINARY CODE TABLE (REFER TO FIGURE 8) FIGURE 8. QUAD DAC UNIPOLAR OPERATION (2-QUADRANT MULTIPLICATION)

FIGURE 9. QUAD DAC BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) TABLE 6. BIPOLAR (OFFSET BINARY) CODE TABLE (REFER TO FIGURE 9)

should not go low until the data bus is fully settled (DATA VALID). and outputs to zero volts, buffers the DAC to produce a low impedance output voltage from 0 V to +1.5 V full-scale. Table 7 shows the code table. maintain the linearity performance. TABLE 7. SINGLE SUPPLY BINARY CODE TABLE (REFER TO FIGURE 10)

FIGURE 10. UNIPOLAR SUPPLY, VOLTAGE OUTPUT DAC OPERATION FIGURE 11. A DIGITALLY PROGRAMMABLE UNIVERSAL ACTIVE FILTER

sophisticated function is achieved in only two IC packages. and C is 1000 pF. Note that from device to device, the resistance RIN varies. Thus some tuning may be necessary. FIGURE 12. PROGRAMMABLE ACTIVE FILTER BAND-PASS FREQUENCY RESPONSE mance over temperature. The wide bandwidth of the OP-470 produces excellent high frequency and high Q response. In addition, the OP470’s low input offset voltage assures an unusually low dc offset at the filter output.

FIGURE 13. A DIGITALLY PROGRAMMABLE, LOW-DISTORTION SINEWAVE OSCILLATOR tude at any frequency. Again, only two ICs accomplish a very useful function.

18All data sheets are subject to change without notice ©2002 Maxwell Technologies All rights reserved. Quad 8-Bit Multiplying CMOS D/A Converter with Memory 8408 Note: All dimensions in inches

28 PIN RAD-PAK® FLAT PACKAGE

A 0.190 0.207 0.224 b 0.015 0.017 0.022 c 0.004 0.005 0.009 D -- 0.720 0.740 E 0.380 0.410 0.420 E1 -- -- 0.440 E2 0.180 0.250 -- E3 0.030 0.080 -- e 0.050 BSC L 0.360 0.370 0.380 Q 0.062 0.073 0.081 S1 0.000 0.027 -- N2 8

19All data sheets are subject to change without notice ©2002 Maxwell Technologies All rights reserved. Quad 8-Bit Multiplying CMOS D/A Converter with Memory 8408 Important Notice: These data sheets are created using the chip manufacturer s published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies’ products are not authorized for use as critical components in li fe support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech- nologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.

20All data sheets are subject to change without notice ©2002 Maxwell Technologies All rights reserved. Quad 8-Bit Multiplying CMOS D/A Converter with Memory 8408 Feature Option Details8408 RP F X Screening Flow Package Radiation Feature Base Product Nomenclature S = Maxwell Class S B = Maxwell Class B I = Industrial (testing @ -55°C, +25°C, +125°C) E = Engineering (testing @ +25°C F = Flat Pack RP = RAD-PAK® package Quad 8-Bit Multiplying CMOS D/A Converter with Memory