83C51SND2C-JL

AT83SND2C_05 ATMEL | Alldatasheet

Document overview

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Technical content

Features

• MPEG I/II-Layer 3 Hardwired Decoder – Stand-alone MP3 Decoder – 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency – Separated Digital Volume Control on Left and Right Channels (Software Control using 31 Steps) – Bass, Medium, and Treble Control (31 Steps) – Bass Boost Sound Effect – Ancillary Data Extraction – CRC Error and MPEG Frame Synchronization Indicators
• 20-bit Stereo Audio DAC – 93 dB SNR playback stereo channel – 32 Ohm/ 20 mW stereo headset drivers – Stereo Line Level Input, Diffe rential Mono Auxiliary Input
• Programmable Audio Output for Interfacing with External Audio System – PCM Format Compatible –I 2S Format Compatible
• Mono Audio Power Amplifier – 440mW on 8 Ohms Load
• 8-bit MCU C51 Core Based (FMAX = 20 MHz)
• 2304 Bytes of Internal RAM
• 64K Bytes of Code Memory – AT89C51SND2C: Flash (100K Erase/Write Cycles) – AT83SND2C: ROM
• 4K Bytes of Boot Flash Memory (AT89C51SND2C) – ISP: Download from USB (s tandard) or UART (option)
• USB Rev 1.1 Controller – Full Speed Data Transmission
• Built-in PLL – MP3 Audio Clocks –U S B C l o c k
• MultiMedia Card® Interface Compatibility
• Atmel DataFlash® SPI Interface Compatibility
• IDE/ATAPI Interface
• Up to 32 Bits of General-purpose I/Os – 1 Interrupt Keyboard – SmartMedia ® Software Interface
• 2 Standard 16-bit Timers/Counters
• Hardware Watchdog Timer
• Standard Full Duplex UART with Baud Rate Generator
• Two Wire Master and Slave Modes Controller
• SPI Master and Slave Modes Controller
• Power Management – Power-on Reset – Software Programmable MCU Clock – Idle Mode, Power-down Mode
• Operating Conditions: –3 V , ±10%, 25 mA Typical Operating at 25°C – Temperature Range: -40 °C to +85°C – Power amplifier supply 3.2V to 5.5V
• Packages –C T B G A 1 0 0 Single-Chip Flash Microcontroller with MP3 Decoder with Full Audio Interface AT83SND2C AT89C51SND2C Preliminary

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4341D–MP3–04/05 Description The AT8xC51SND2C has been developed for handling MP3 ringing tones in mobile phones and can replace sound generators while adding SD/MMC card reader, MP3 music decoding, and connection of the cell phone to a PC through USB. Cell phones can also be used as a thumb drive extending cell phone capabilities. The AT8xC51SND2C are fully integrated stand -alone hardwired MPEG I/II-Layer 3 decoder with a C51 microcontroller core hand ling data flow, MP3-player control, Stereo Audio DAC and Mono Audio Power Amplifier for speaker control. The AT89C51SND2C includes 64K Bytes of Flash memory and allows In-System Pro- gramming through an embedded 4K Bytes of Boot Flash memory. The AT83SND2C includes 64K Bytes of ROM memory. The AT8xC51SND2C include 2304 Bytes of RAM memory. The AT8xC51SND2C provides the necessary f eatures for human interface like timers, keyboard port, serial or parallel interface (USB, TWI, SPI, IDE), I 2S output, and all exter- nal memory interface (NAND or NOR Flash, SmartMedia, MultiMedia, DataFlash cards). Typical Applications • MP3-Player

• PDA, Camera, Mobile Phone MP3
• Car Audio/Multimedia MP3
• Home Audio/Multimedia MP3

Figure 1. AT8xC51SND2C Block Diagram

3 Alternate function of Port 3

4 Alternate function of Port 4

64 KBytes

4 KBytes

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4341D–MP3–04/05 Pin Description Pinouts Figure 2. AT8xC51SND2C 100-pin BGA Package Notes: 1. ISP pin is only available in AT89C51SND2C product. Do not connect this pin on AT83SND2C product. 2. NC is Do Not Connect AUXN 897 6 5 4 3 2 C B A D E F G H ALE NC AUDVDD HSVDD HSVSS AUDVSS AUDVCM NC HSL HSR PVSS INGND P0.0/ NC PVDD LINEL NC P0.3/ NC AUDVREF FILT LINER VSS VSS MONON P0.4/ P0.5/ VSS P3.0/ TST P3.6/ VDD P4.2/ P0.6/ P0.7/ VDD P3.1/ P3.4/ P3.5/ P3.7/ P4.1/ P4.0/ P4.3/ NC ESDVSS P3.2/ DSEL DCLK LPHN P2.0/ P2.1/ P2.5/ MCLK VDD NC SCLK DOUT CBP NC P2.2/ P2.3/ P2.7/ VSS MDAT AUDRST VSS AUDVSS J P0.2/ P0.1/ NC AUXP MONOP AD7 SS WR NC VDD P2.4/ P2.6/ EA MCMD RST NC VDD UVSSUVDDVDDP3.3/AUDVSSHPNAUDVBATHPPPAINNPAINP MOSI SCKMISO K KIN0AD0 AD4 AD3 AD2 AD1 SCLSDA AD5 A9A10 A11A12 A13 A14 A15 TXD RXD RD INT1 INT0 ISP/ AD6 NC

Signals All the AT8xC51SND2C signals are detailed by functionality in Table 1 to Table 14. Table 1. Ports Signal Description Table 2. Clock Signal Description Table 3. Timer 0 and Timer 1 Signal Description P3 is an 8-bit bidirectional I/O port with internal pull-ups. P4 is an 8-bit bidirectional I/O port with internal pull-ups. pin. X1 is the clock source for internal timing. this pin. If an external oscillator is used, leave X2 unconnected. set by a low level on INT0#.

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Table 4. Audio Interface Signal Description Table 5. USB Controller Signal Description Table 6. MutiMediaCard Interface Signal Description set by a low level on INT1#. (DOUT) and the channel selection signal (DSEL). unused MCMD input must be polarized to VDD or VSS. unused MDAT input must be polarized to VDD or VSS.

Table 7. UART Signal Description Table 8. SPI Controller Signal Description Table 9. TWI Controller Signal Description Table 10. Keypad Interface Signal Description serial I/O modes 1, 2 and 3. serial I/O modes 1, 2 and 3. When in master mode, MISO receives data from the slave peripheral. When in slave mode, MISO outputs data to the master controller. When in master mode, MOSI outputs data to the slave peripheral. When in slave mode, MOSI receives data from the master controller. in slave mode, SCK receives clock from the master controller. receives clock from the master controller.

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Table 11. External Access Signal Description Note: 1. For ROM/Flash/ROMless Dice product versions only. Table 12. System Signal Description Table 13. Power Signal Description Upper address lines for the external bus. Multiplexed higher address and data lines for the IDE interface. to demultiplex the address from address/data bus. falling reset to force execution of the internal bootloader. reset by connecting a capacitor between this pin and VDD. returns the chip to normal operation.

Table 14. Audio Power Signal Description Table 15. Stereo Audio Dac and Mono Power Amplifier Signal Description ESDVSS GND Audio Analog Circuit Ground for Electrostatic Discharge. HSVSS GND Headset Driver Ground.

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4341D–MP3–04/05 HSR O Audio Right Channel Headset Driver Output - LINEL I Audio Left Channel Line In - LINER I Audio Right Channel Line In - INGND I Audio Line Signal Ground Pin for decoupling.- AUDVCM I Audio Common Mode reference for decoupling - Signal Name Type Description Alternate Function

4341D–MP3–04/05 Internal Pin Structure Table 16. Detailed Internal Pin Structure Notes: 1. For information on resistors value, inpu t/output levels, and drive capability, refer to the Section “DC Characteristics”, page 201. 2. When the Two Wire controller is enabled, P 3 transistors are disabled allowing pseudo open-drain structure. Circuit(1) Type Pins Input TST Input/Output RST Input/Output P3 Input/Output MCMD MDAT ISP PSEN Output ALE SCLK DCLK DOUT DSEL MCLK Input/Output D+ RTST VDD RRST VSS P VDD Watchdog Output VSS N VDD VDD2 osc Latch Output periods VDD VSS N P VDD VSS N P VDD

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generated by this controller. detailed in the section “DC Characteristics”. Timer 1, MMC, SPI, and Port sampling clocks. Figure 3. Oscillator Block Diagram and Symbol Figure 4. Crystal Connection oscillator frequency divided by 2 while in X2 mode, it is the oscillator frequency. to X2 mode later by software.

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Figure 7. PLL Filter Connection Figure 8. PLL Programming Flow

Table 18. PLLCON Register Clear to select the peripheral clock as TWI clock input (X2 dependent). Clear to select the peripheral clock as watchdog clock input (X2 dependent). The values read from this bit is indeterminate. Do not set this bit. Clear to select the peripheral clock as UART clock input (X2 dependent).. The values read from this bit is indeterminate. Do not set this bit. Clear to select the peripheral clock as timer 1 clock input (X2 dependent). Clear to select the peripheral clock as timer 0 clock input (X2 dependent). Set to select 6 clock periods per machine cycle (X2 mode, FCPU = FPER = FOSC). 2 LSB of the 10-bit R divider. The values read from these bits are always 0. Do not set these bits.

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Table 19. PLLNDIV Register Table 20. PLLRDIV Register

3 PLLRES

Set this bit to reset the PLL. Clear this bit to free the PLL and allow enabling. The value read from this bit is always 0. Do not set this bit.

1 PLLEN

Set by hardware when PLL is locked. Clear by hardware when PLL is unlocked. The value read from this bit is always 0. Do not set this bit. 8 MSB of the 10-bit R divider.

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facturing process. It contains the user’s application code. detailed in the following paragraphs. Figure 11. AT89C51SND2C Memory Architecture Bytes. It contains the user’s application code. This space can be read or written by both software and hardware modes. System Programming and the routines for In Application Programming. and can only be written by hardware.

• The Software Boot Vector (SBV, see Table 24). This Byte is used by the software boot loader to build the boot address.
• The Software Security Byte (SSB, see Table 25). This Byte is used to lock the execution of some boot loader commands. FFFFh 64K Bytes Flash Memory 0000h Hardware Security User 4K Bytes Flash Memory FFFFh F000h Boot Extra Row

while the AT83SND2C is always set in read disabled mode. Level 0 is the level of an erased part and does not enable any security feature. Level 1 locks the hardware programming of both user and boot memories. Level 3 locks also the external execution.

1. AT89C51SND2C products are delivered with third level programmed to ensure that

(see Figure 22). The three ways to set this bit are detailed in the following sections. ware. This enables boot loader or API routines execution. to execute the boot loader software. user’s memory has been corrupted. 0000h, in order to execute the boot loader software. Table 21. Lock Bit Features

0 U U U Enable Enable Enable Enable Enable

1 U U P Enable Enable Enable Disable Enable

2 U P X Enable Enable Disable Disable Enable

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Figure 12. Hardware Boot Process Algorithm See Section “Reset Recommendation to Prevent Flash Corruption”, page 47.

4341D–MP3–04/05 Registers Table 22. AUXR1 Register AUXR1 (S:A2h) – Auxiliary Register 1 Reset Value = XXXX 00X0b Note: 1. ENBOOT bit is only available in AT89C51SND2C product. 76543210 - - ENBOOT - GF3 0 - DPS Bit Number Bit Mnemonic Description 7 - 6 - Reserved The value read from these bits are indeterminate. Do not set these bits.

5 ENBOOT 1

Set this bit to map the boot Flash in the code space between at addresses F000h to FFFFh. Clear this bit to disable boot Flash. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3G F 3 General Flag This bit is a general-purpose user flag. Always Zero This bit is stuck to logic 0 to allow IN C AUXR1 instruction without affecting GF3 flag. 1- Reserved for Data Pointer Extension. 0D P S Data Pointer Select Bit Set to select second data pointer: DPTR1. Clear to select first data pointer: DPTR0.

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Reset Value = XXUU UXXX, UUUU UUUU after an hardware full chip erase. Note: 1. X2B initializes the X2 bit in CKCON during the reset phase.

1. In order to ensure boot loader activation at first power-up, AT89C51SND2C products

are delivered with BLJB programmed.

1. Bits 0 to 3 (LSN) can only be programmed by hardware mode.

Reset Value = XXXX XXXX, UUUU UUUU after an hardware full chip erase. Reset Value = XXXX XXXX, UUUU UUUU after an hardware full chip erase. Program this bit to start in X2 mode. Unprogram (erase) this bit to start in standard mode. Program this bit to execute the boot loader at address F000h on next reset. The value read from this bit is always unprogrammed. Do not program this bit. Refer to for bits description. Table 24. SBV Byte – Software Boot Vector Table 25. SSB Byte – Software Security Byte

1. The internal space mapped in three separate segments:

on this segment, refer to the Section “Special Function Registers”, page 30. Figure 13 shows the internal and external data memory spaces organization. Figure 13. Internal and External Data Memory Organization ing, and can be used for context switching in interrupt service routines. Table 26. Register Bank Selection addresses in this area are 00h to 7Fh.

128 Bytes

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Figure 14. Lower 128 Bytes Internal RAM Organization and when EXTRAM = 1, the XRAM is selected (see Section “External Space”). Table 27. ERAM Size Selection must then be initialized properly.

4 Banks of

8 Registers

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Figure 16), and write data (see Figure 17) in the external data memory. mation on X2 mode, refer to the Section “X2 Feature”, page 12. signals from 3 to 15 CPU clock periods. the Section “AC Characteristics”. Figure 16. External Data Read Waveforms Notes: 1. RD signal may be stretched using M0 bit in AUXR register.

1. When executing MOVX @Ri instruct ion, P2 outputs SFR content.
2. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode),

P2 outputs SFR content instead of DPH. Figure 17. External Data Write Waveforms Notes: 1. WR signal may be stretched using M0 bit in AUXR register.

1. When executing MOVX @Ri instruct ion, P2 outputs SFR content.
2. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode),

P2 outputs SFR content instead of DPH.

and reducing code size in case of intensive usage of external memory accesses. Figure 18. Dual Data Pointer Implementation enhanced algorithm libraries.

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4341D–MP3–04/05 Registers Table 29. PSW Register PSW (S:8Eh) – Program Status Word Register Reset Value = 0000 0000b 76543210 CY AC F0 RS1 RS0 OV F1 P Bit Number Bit Mnemonic Description 7C Y Carry Flag Carry out from bit 1 of ALU operands. 6A C Auxiliary Carry Flag Carry out from bit 1 of addition operands. 5F 0 User Definable Flag 0 4 - 3 RS1:0 Register Bank Select Bits Refer to Table 26 for bits description. 2O V Overflow Flag Overflow set by arithmetic operations. 1F 1 User Definable Flag 1 Parity Bit Set when ACC contains an odd number of 1’s. Cleared when ACC contains an even number of 1’s.

Table 30. AUXR Register The value read from this bit is indeterminate. Do not set this bit.

6 EXT16

Set to enable 16-bit access mode during MOVX instructions. Set to stretch RD or WR signals duration to 15 CPU clock periods. Clear not to stretch RD or WR signals and set duration to 3 CPU clock periods. Set to disable DPH output on P2 when executing MOVX @DPTR instruction. Clear to enable DPH output on P2 when executing MOVX @DPTR instruction. Refer to Table 27 for ERAM size description.

1 EXTRAM

Set to output the ALE signal only during MOVX instructions.

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registers are identified by Note 1. Note: 1. ENBOOT bit is only available in AT89C51SND2C product. Table 31. C51 Core SFRs Table 32. System Management SFRs Table 33. PLL and System Clock SFRs Table 34. Interrupt SFRs

Note: 1. FCON register is only available in AT89C51SND2C product. Table 35. Port SFRs Table 36. Auxiliary SFRs Table 37. Flash Memory SFR Table 38. Timer SFRs

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Table 39. MP3 Decoder SFRs Table 40. Audio Interface SFRs

Table 41. USB Controller SFRs Table 42. Audio Interface SFRs Table 43. MMC Controller SFRs

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Table 44. IDE Interface SFR Table 45. Serial I/O Port SFRs Table 46. SPI Controller SFRs Table 47. Two Wire Controller SFRs Table 48. Keyboard Interface SFRs

Notes: 1. SFR registers with least significant nibble address equal to 0 or 8 are bit-addressable.

1. NVERS reset value depends on the silicon version: 1000 0100 for AT89C51SND2C product and 0000 0001 for AT83SND2C
2. FCON register is only available in AT89C51SND2C product.
3. FCON reset value is 00h in case of reset with hardware condition.
4. CKCON reset value depends on the X2B bit (programmed or unprogrammed) in the Hardware Byte.

Table 49. SFR Addresses and Reset Values

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are enabled or disabled by the system designer and may be manipulated dynamically.

• An internal or external device initiates an interrupt-request signal. The AT8xC51SND2C, latches this event into a flag buffer.
• The priority of the flag is compared to the priority of other interrupts by the interrupt handler. A high priority causes the handler to set an interrupt flag.
• This signals the instruction execution unit to execute a context switch. This context switch breaks the current flow of instruction sequences. The execution unit completes the current instruction prior to a save of the program counter (PC) and reloads the PC with the start address of a software service routine.
• The software service routine executes assigned tasks and as a final activity performs a RETI (return from interrupt) instruction. This instruction signals completion of the interrupt, resets the interrupt-in-progress priority and reloads the program counter. Program operation then continues from the original point of interruption.

Table 50. Interrupt System Signals IPL0, IPH1 and IPL1 registers (see Table 55 to Table 58).

Table 51. Priority Levels rupts is determined by an internal hard ware polling sequence detailed in Table 52. polling sequence. The interrupt control system is shown in Figure 19. Table 52. Priority within Same Level

2 C:0013h INT1

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Figure 19. Interrupt Control System

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4341D–MP3–04/05 Registers Table 53. IEN0 Register IEN0 (S:A8h) – Interrupt Enable Register 0 Reset Value = 0000 0000b 76543210 EA EAUD EMP3 ES ET1 EX1 ET0 EX0 Bit Number Bit Mnemonic Description 7E A Enable All Interrupt Bit Set to enable all interrupts. Clear to disable all interrupts. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit.

6 EAUD

Audio Interface Interrupt Enable Bit Set to enable audio interface interrupt. Clear to disable audio interface interrupt. 5E M P 3 MP3 Decoder Interrupt Enable Bit Set to enable MP3 decoder interrupt. Clear to disable MP3 decoder interrupt. 4E S Serial Port Interrupt Enable Bit Set to enable serial port interrupt. Clear to disable serial port interrupt. 3E T 1 Timer 1 Overflow Interrupt Enable Bit Set to enable timer 1 overflow interrupt. Clear to disable timer 1 overflow interrupt. 2E X 1 External Interrupt 1 Enable bit Set to enable external interrupt 1. Clear to disable external interrupt 1. 1E T 0 Timer 0 Overflow Interrupt Enable Bit Set to enable timer 0 overflow interrupt. Clear to disable timer 0 overflow interrupt. 0E X 0 External Interrupt 0 Enable Bit Set to enable external interrupt 0. Clear to disable external interrupt 0.

Table 54. IEN1 Register The value read from this bit is always 0. Do not set this bit. Set this bit to enable USB interrupts. Clear this bit to disable USB interrupts. The value read from this bit is always 0. Do not set this bit.

4 EKB

Set to enable Keyboard interrupt. Clear to disable Keyboard interrupt. The value read from this bit is always 0. Do not set this bit. Set to enable SPI interrupt. Clear to disable SPI interrupt. Set to enable Two Wire interrupt. Clear to disable Two Wire interrupt.

0 EMMC

Set to enable MMC interrupt. Clear to disable MMC interrupt.

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Table 55. IPH0 Register The value read from this bit is indeterminate. Do not set this bit.

6 IPHAUD Audio Interface Interrupt Priority Level MSB

Refer to Table 51 for priority level description. Refer to Table 51 for priority level description. Refer to Table 51 for priority level description. Refer to Table 51 for priority level description.

2 IPHX1 External Interrupt 1 Priority Level MSB

Refer to Table 51 for priority level description. Refer to Table 51 for priority level description.

0 IPHX0 External Interrupt 0 Priority Level MSB

Refer to Table 51 for priority level description.

Table 56. IPH1 Register The value read from this bit is always 0. Do not set this bit. Refer to Table 51 for priority level description. The value read from this bit is always 0. Do not set this bit. Refer to Table 51 for priority level description. The value read from this bit is always 0. Do not set this bit.

2 IPHSPI SPI Interrupt Priority Level MSB

Refer to Table 51 for priority level description. Refer to Table 51 for priority level description. Refer to Table 51 for priority level description.

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Table 57. IPL0 Register The value read from this bit is indeterminate. Do not set this bit.

6 IPLAUD Audio Interface Interrupt Priority Level LSB

Refer to Table 51 for priority level description. Refer to Table 51 for priority level description. Refer to Table 51 for priority level description. Refer to Table 51 for priority level description.

2 IPLX1 External Interrupt 1 Priority Level LSB

Refer to Table 51 for priority level description. Refer to Table 51 for priority level description.

0 IPLX0 External Interrupt 0 Priority Level LSB

Refer to Table 51 for priority level description.

Table 58. IPL1 Register The value read from this bit is always 0. Do not set this bit. Refer to Table 51 for priority level description. The value read from this bit is always 0. Do not set this bit.

4 IPLKB Keyboard Interrupt Priority Level LSB

Refer to Table 51 for priority level description. The value read from this bit is always 0. Do not set this bit.

2 IPLSPI SPI Interrupt Priority Level LSB

Refer to Table 51 for priority level description. Refer to Table 51 for priority level description.

0 IPLMMC MMC Interrupt Priority Level LSB

Refer to Table 51 for priority level description.

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cally divided by 2 using the X2 mode detailed in section “X2 Feature”, page 12. Port pins during reset is detailed in Table 59. Figure 22. Reset Circuitry and Power-On Reset Table 59. Pin Conditions in Special Operating Modes Note: 1. Refer to section “Audi o Output Interface”, page 73.

• V DD must reach the specified VDD range
• The level on X1 input pin must be outside the specification (V IH, VIL) If one of these 2 conditions are not met, th e microcontroller does not start correctly and can execute an instruction fe tch from anywhere in the program space. An active level applied on the RST pin must be maintained till both of the above conditions are met. A reset is active when the level V IH1 is reached and when the pulse width covers the period of time where V DD and the oscillator are not stabilized. 2 parameters have to be taken into account to determine the reset pulse width:
• V DD rise time,
• Oscillator startup time. To determine the capacitor value to implement, the highest value of these 2 parameters has to be chosen. Table 60 gives some ca pacitor values examples for a minimum R RST of 50 KΩ and different oscillator startup and VDD rise times. Mode Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 MMC Audio Reset Floating High High High High High Floating 1 Idle Data Data Data Data Data Data Data Data Power-down Data Data Data Data Data Data Data Data RRST RST VSS To CPU Core and Peripherals RST VDD Power-on ResetRST input circuitry P VDD From Internal Reset Source

Table 60. Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor(1) fully discharged, leading to a bad reset sequence. periods is mode independent (X2 or X1). be added as shown in Figure 23. Figure 23. Reset Circuitry for WDT Reset-out Usage this bit allows mapping of the bootloader in the code area, a reset failure can be critical. (write or erase) may corrupt the Flash on-chip memory. supply failure, power supply switched off).

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4341D–MP3–04/05 Entering Idle Mode To enter Idle mode, the user must set the IDL bit in PCON register (see Table 61). The AT8xC51SND2C enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed. Note: If IDL bit and PD bit are set simultaneously, the AT8xC51SND2C enter Power-down mode. Then it does not go in Idle mode when exiting Power-down mode. Exiting Idle Mode There are 2 ways to exit Idle mode: 1. Generate an enabled interrupt. – Hardware clears IDL bit in PCON register which restores the clock to the CPU. Execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Idle mode. The general-purpose flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt occurred during normal operation or during Idle mode. When Idle mode is exited by an interrupt, the interrupt service routine may examine GF1 and GF0. 2. Generate a reset. – A logic high on the RST pin clears ID L bit in PCON register directly and asynchronously. This restores the clock to the CPU. Program execution momentarily resumes with the instruction immediately following the instruction that activated the Idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the AT8xC51SND2C and vectors the CPU to address C:0000h. Note: During the time that execution resumes, the internal RAM cannot be accessed; however, it is possible for the Port pins to be acce ssed. To avoid unexpected outputs at the Port pins, the instruction immediately following the instruction that activated Idle mode should not write to a Port pin or to the external RAM. Power-down Mode The Power-down mode places the AT8xC51SND2C in a very low power state. Power- down mode stops the oscillator and freezes all clocks at known states (refer to the Sec- tion "Oscillator", page 12). The CPU status prior to entering Power-down mode is preserved, i.e., the program counter, program status word register retain their data for the duration of Power-down mode. In addition, the SFRs and RAM contents are pre- served. The status of the Port pins during Power-down mode is detailed in Table 59. Note: V DD may be reduced to as low as VRET during Power-down mode to further reduce power dissipation. Notice, however, that VDD is not reduced until Power-down mode is invoked. Entering Power-down Mode To enter Power-down mode, set PD bit in PCON register. The AT8xC51SND2C enters the Power-down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed. Exiting Power-down Mode If VDD was reduced during the Power-down mode, do not exit Power-down mode until VDD is restored to the normal operating level. There are 2 ways to exit the Power-down mode: 1. Generate an enabled external interrupt. – The AT8xC51SND2C provides capabilit y to exit from Power-down using INT0, INT1, and KIN0 inputs. In addition, using KIN input provides high or low level exit capability (see section “Keyboard Interface”, page 198). Hardware clears PD bit in PCON register which starts the oscillator and restores the clocks to the CPU and peripherals. Using INTn input, execution

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4341D–MP3–04/05 Registers Table 61. PCON Register PCON (S:87h) – Power Configuration Register Reset Value = 00XX 0000b 76543210 SMOD1 SMOD0 - - GF1 GF0 PD IDL Bit Number Bit Mnemonic Description 7S M O D 1 Serial Port Mode Bit 1 Set to select double baud rate in mode 1,2 or 3. 6S M O D 0 Serial Port Mode Bit 0 Set to select FE bit in SCON register. Clear to select SM0 bit in SCON register. 5 - 4 - Reserved The value read from these bits is indeterminate. Do not set these bits. 3G F 1 General-Purpose Flag 1 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode. 2G F 0 General-Purpose Flag 0 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode. 1P D Power-Down Mode Bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Power-down mode. If IDL and PD are both set, PD takes precedence. 0I D L Idle Mode Bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Idle mode. If IDL and PD are both set, PD takes precedence.

4341D–MP3–04/05 Timers/Counters The AT8xC51SND2C implement 2 general-purp ose, 16-bit Timers/Counters. They are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or as an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, the Timer/Counter counts negative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request. The various operating modes of each Time r/Counter are described in the following sections. Timer/Counter Operations For instance, a basic operation is Timer regi sters THx and TLx (x = 0, 1) connected in cascade to form a 16-bit Timer. Setting the run control bit (TRx) in TCON register (see Table 62) turns the Timer on by allowing the selected input to increment TLx. When TLx overflows it increments THx; when THx overflows it sets the Timer overflow flag (TFx) in TCON register. Setting the TRx does not clea r the THx and TLx Timer registers. Timer registers can be accessed to obtain the current count or to enter preset values. They can be read at any time but TRx bit must be cleared to preset their values, otherwise, the behavior of the Timer/Counter is unpredictable. The C/Tx# control bit selects Timer operati on or Counter operation by selecting the divided-down peripheral clock or external pin Tx as the source for the counted signal. TRx bit must be cleared when changing the mode of operation, ot herwise the behavior of the Timer/Counter is unpredictable. For Timer operation (C/Tx# = 0), the Timer register counts the divided-down peripheral clock. The Timer register is incremented once every peripheral cycle (6 peripheral clock periods). The Timer clock rate is F PER/6, i.e., FOSC/12 in standard mode or F OSC/6 in X2 mode. For Counter operation (C/Tx# = 1), the Timer register counts the negative transitions on the Tx external input pin. The external in put is sampled every peripheral cycles. When the sample is high in one cycle and low in the next one, the Counter is incremented. Since it takes 2 cycles (12 peripheral clock pe riods) to recognize a negative transition, the maximum count rate is F PER/12, i.e., F OSC/24 in standard mode or F OSC/12 in X2 mode. There are no restrictions on the duty cycle of the ex ternal input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full peripheral cycle. Timer Clock Controller As shown in Figure 26, the Timer 0 (FT0) and Timer 1 (FT1) clocks are derived from either the peripheral clock (F PER) or the oscillator clock (F OSC) depending on the T0X2 and T1X2 bits in CKCON register. These cl ocks are issued from the Clock Controller block as detailed in Section “Clock Controlle r”, page 12. When T0X2 or T1X2 bit is set, the Timer 0 or Timer 1 clock frequency is fixed and equal to the oscillator clock fre- quency divided by 2. When cl eared, the Timer clock frequen cy is equal to the oscillator clock frequency divided by 2 in standard mode or to the oscillator clock frequency in X2 mode.

52 AT8xC51SND2C

Figure 26. Timer 0 and Timer 1 Clock Controller and Symbols Timer 0 Timer 0 functions as either a Timer or event Counter in four modes of operation. Figure 27 through Figure 33 show the logical configuration of each mode. bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0). It is important to stop Timer/Counter before changing mode. Figure 27. Timer/Counter x (x = 0 or 1) in Mode 0 Figure 28. Mode 0 Overflow Period Formula

54 AT8xC51SND2C

1. Figure 32 gives the autoreload period calculation formulas for both TF0 and TF1

Figure 33. Timer/Counter 0 in Mode 3: 2 8-bit Counters Figure 34. Mode 3 Overflow Period Formula

• Timer 1 functions as either a Timer or event Counter in three modes of operation. Figure 27 through Figure 31 show the logical configuration for modes 0, 1, and 2. Timer 1’s mode 3 is a hold-count mode.
• Timer 1 is controlled by the four high-ord er bits of TMOD register (see Figure 63) and bits 2, 3, 6 and 7 of TCON register (see Figure 62). TMOD register selects the method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and mode of operation (M11 and M01). TCON register provides Timer 1 control functions: overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type control bit (IT1).
• Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best suited for this purpose.
• For normal Timer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented by the selected input. Setting GATE1 and TR1 allows external pin INT1 to control Timer operation.
• Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating an interrupt request.
• When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit (TR1). For this situation, use Timer 1 only for applications that do not require an interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in and out of mode 3 to turn it off and on.
• It is important to stop the Timer/Counter before changing modes. TR0 TCON.4 TF0 TCON.5 INT0 GATE0 TMOD.3 Overflow Timer 0 Interrupt Request C/T0# TMOD.2 TL0 (8 bits) TR1 TCON.6 TH0 (8 bits) TF1 TCON.7 Overflow Timer 1 Interrupt Request TIM0 CLOCK ÷ 6 TIM0 CLOCK ÷ 6 TF0PER = FTIM0 6 ⋅ (256 – TL0) TF1PER = FTIM0 6 ⋅ (256 – TH0)

cascade (see Figure 29). The selected input increments TL1 register. Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in mode 3. assumes interrupts are globally enabled by setting EA bit in IEN0 register. Figure 35. Timer Interrupt System

56 AT8xC51SND2C

4341D–MP3–04/05 Registers Table 62. TCON Register TCON (S:88h) – Timer/Counter Control Register Reset Value = 0000 0000b 76543210 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Number Bit Mnemonic Description 7T F 1 Timer 1 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 1 register overflows. 6T R 1 Timer 1 Run Control Bit Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1. 5T F 0 Timer 0 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 0 register overflows. 4T R 0 Timer 0 Run Control Bit Clear to turn off Timer/Counter 0. Set to turn on Timer/Counter 0. 3I E 1 Interrupt 1 Edge Flag Cleared by hardware when interrupt is processed if edge-triggered (see IT1). Set by hardware when external interrupt is detected on INT1 pin. 2I T 1 Interrupt 1 Type Control Bit Clear to select low level active (level triggered) for external interrupt 1 (INT1). Set to select falling edge active (edge triggered) for external interrupt 1. 1I E 0 Interrupt 0 Edge Flag Cleared by hardware when interrupt is processed if edge-triggered (see IT0). Set by hardware when external interrupt is detected on INT0 pin. 0I T 0 Interrupt 0 Type Control Bit Clear to select low level active (level triggered) for external interrupt 0 (INT0). Set to select falling edge active (edge triggered) for external interrupt 0.

Notes: 1. Reloaded from TH1 at overflow.

1. Reloaded from TH0 at overflow.

Table 64. TH0 Register Table 63. TMOD Register Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1 pin is high and TR1 bit is set. Clear for Timer operation: Timer 1 counts the divided-down system clock. Set for Counter operation: Timer 1 counts negative transitions on external pin T1. 0 0 Mode 0: 8-bit Timer/Counter (TH1) with 5-bit prescaler (TL1). 0 1 Mode 1: 16-bit Timer/Counter. 1 1 Mode 3: Timer 1 halted. Retains count. Clear to enable Timer 0 whenever TR0 bit is set. Set to enable Timer/Counter 0 only while INT0 pin is high and TR0 bit is set. Clear for Timer operation: Timer 0 counts the divided-down system clock. Set for Counter operation: Timer 0 counts negative transitions on external pin T0.

1 M10 Timer 0 Mode Select Bit

0 0 Mode 0: 8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0). 0 1 Mode 1: 16-bit Timer/Counter. 1 1 Mode 3: TL0 is an 8-bit Timer/Counter. TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 bits.

0 M00

58 AT8xC51SND2C

Table 65. TL0 Register Table 66. TH1 Register Table 67. TL1 Register

60 AT8xC51SND2C

Figure 38. WDT Time-Out Formula

1. These frequencies are achieved in X2 mode when WTX2 = 0: F WDT = FOSC.

Operation of the WDT during power reduction modes deserves special attention. the WDT just before entering Power-down mode. The WDT is cleared and disabled if the Power-down mode is terminated by a reset. Table 68. WDT Time-Out Computation

6 MHz(1) 8 MHz(1) 10 MHz(1) 12 MHz(2) 16 MHz(2) 20 MHz(2)

Figure 39. WDTPRG Register The value read from these bits is indeterminate. Do not set these bits. Refer to Table 68 for time-out periods.

62 AT8xC51SND2C

allows highest compression rate of about 12 :1 while still maintaining CD audio quality. are supported for low bit rates applications. into a PCM audio data, and also supports MPEG II audio layer 3 additional frequencies. Table 83); and MPCLK, the MP3 Clock Divider register (see Table 84). Figure 40 shows the MP3 decoder block diagram. Figure 40. MP3 Decoder Block Diagram

64 AT8xC51SND2C

MP3VOR and MP3VOL registers allow a 32-step volume control according to Table 71. Table 71. Volume Control and MP3TRE registers allow a 32-step gain control in each band according to Table 72. Table 72. Bass, Medium, Treble Control lowing characteristics: gain increase of +9 dB in the frequency under 375 Hz. header of the frame that has been sent to the decoder. data that have been sent to the decoder. played or rejected. In both cases, noise may appear at audio output.

00000 Mute

Frame Information The MP3 frame header contains information on the audio data contained in the frame. These informations is made available in the MP3STA register for you information. Table 73. MPVER bit gives the MPEG version (2 or 1). Table 73. MP3 Frame Frequency Sampling Bytes to empty the ancillary buffer. Figure 43. Ancillary Data Block Diagram

011 R e s e r v e d

111 R e s e r v e d

8 MP3ANC 8 MPANC

66 AT8xC51SND2C

ERRCRC, ERRSYN, ERRLAY, MPREQ, and MPANC flags in MP3STA register. MSKREQ, and MSKANC mask bits respectively in MP3CON register. rupts are globally enabled by setting EA bit in IEN0 register. All interrupt flags but MPREQ and MPANC are cleared when reading MP3STA register. Figure 44. MP3 Decoder Interrupt System and tested, interrupt flag by interrupt flag to be sure not to forget any interrupts.

Figure 45. MP3 Interrupt Service Routine Flow Note: 1. Test these bits only if needed (unmasked interrupt).

68 AT8xC51SND2C

4341D–MP3–04/05 Registers Table 74. MP3CON Register MP3CON (S:AAh) – MP3 De coder Control Register Reset Value = 0011 1111b 76543210 MPEN MPBBST CRCEN MSKANC MSKREQ MSKLAY MSKSYN MSKCRC Bit Number Bit Mnemonic Description

7 MPEN

Set to enable the MP3 decoder. Clear to disable the MP3 decoder.

6 MPBBST

Set to enable the bass boost sound effect. Clear to disable the bass boost sound effect.

5 CRCEN

Set to enable processing of frame that contains CRC error. Frame is played whatever the error. Clear to disable processing of frame that contains CRC error. Frame is skipped.

4 MSKANC

Set to prevent the MPANC flag from generating a MP3 interrupt. Clear to allow the MPANC flag to generate a MP3 interrupt. 3M S K R E Q MPREQ Flag Mask Bit Set to prevent the MPREQ flag from generating a MP3 interrupt. Clear to allow the MPREQ flag to generate a MP3 interrupt.

2 MSKLAY

Set to prevent the ERRLAY flag from generating a MP3 interrupt. Clear to allow the ERRLAY flag to generate a MP3 interrupt.

1 MSKSYN

Set to prevent the ERRSYN flag from generating a MP3 interrupt. Clear to allow the ERRSYN flag to generate a MP3 interrupt.

0 MSKCRC

Set to prevent the ERRCRC flag from generating a MP3 interrupt. Clear to allow the ERRCRC flag to generate a MP3 interrupt.

Table 75. MP3STA Register Table 76. MP3DAT Register Set by hardware as soon as one ancillary data is available (buffer not empty). Cleared by hardware when no more ancillary data is available (buffer empty).

6 MPREQ

Set by hardware when MP3 decoder request data. Cleared when reading MP3STA.

5 ERRLAY

Set by hardware when an invalid layer is encountered. Cleared when reading MP3STA.

4 ERRSYN

Set by hardware when no synchronization pattern is encountered in a frame. Cleared when reading MP3STA.

3 ERRCRC

Set by hardware when a frame handling CRC is corrupted. Cleared when reading MP3STA. Refer to Table 73 for bits description.

0 MPVER

Set by the MP3 decoder when the loaded frame is a MPEG I frame. Cleared by the MP3 decoder when the loaded frame is a MPEG II frame. 8-bit MP3 stream data input buffer.

70 AT8xC51SND2C

Table 77. MP3STA1 Register Table 78. MP3ANC Register Table 79. MP3VOL Register The value read from these bits is always 0. Do not set these bits. Set by hardware when MP3 decoder request data. Cleared when MP3 decoder no more request data . Set by hardware when MP3 decoder request data. Cleared when writing to MP3DAT. The value read from these bits is always 0. Do not set these bits. MP3 ancillary data Byte buffer. The value read from these bits is always 0. Do not set these bits. Refer to Table 71 for the left channel volume control description.

Table 80. MP3VOR Register Table 81. MP3BAS Register Table 82. MP3MED Register The value read from these bits is always 0. Do not set these bits. Refer to Table 71 for the right channel volume control description. The value read from these bits is always 0. Do not set these bits. Refer to Table 72 for the bass control description. The value read from these bits is always 0. Do not set these bits. Refer to Table 72 for the medium control description.

72 AT8xC51SND2C

Table 83. MP3TRE Register Table 84. MP3CLK Register The value read from these bits is always 0. Do not set these bits. Refer to Table 72 for the treble control description. The value read from these bits is always 0. Do not set these bits. 5-bit divider for MP3 decoder clock generation.

74 AT8xC51SND2C

the incoming MP3 frames and the audio DAC used. Figure 47. Audio Clock Generator and Symbol Figure 48. DSEL Output Polarity LSB justification by filling the low significant bits with logic 0.

Figure 49. Audio Output Format ing from the C51 core for voice or sound playing. for generating the bit and word clocks. bits in AUDCON1 register according to Table 85. I2S Format with DSIZ = 0 and JUST4:0 = 00001. I2S Format with DSIZ = 1 and JUST4:0 = 00001. MSB/LSB Justified Format with DSIZ = 0 and JUST4:0 = 00000. 16-bit LSB Justified Format with DSIZ = 1 and JUST4:0 = 10000. 18-bit LSB Justified Format with DSIZ = 1 and JUST4:0 = 01110.

76 AT8xC51SND2C

Table 85. Sample Duplication Factor MP3 Buffer In song playing mode, the audio stream comes from the MP3 decoder through a buffer. empty. This bit can be used to suspend the audio generation (pause mode). Figure 50. Audio Interface Interrupt System shows the configuration flow of the audio interface when in MP3 song mode. 0 0 No sample duplication, DAC rate = 8 kHz (C51 rate). 0 1 One sample duplication, DAC rate = 16 kHz (2 x C51 rate). 1 0 2 samples duplication, DAC rate = 32 kHz (4 x C51 rate). 1 1 Three samples duplication, DAC rate = 48 kHz (6 x C51 rate).

78 AT8xC51SND2C

Table 87. AUDCON1 Register Refer to Section "Data Converter", page 74 for bits description. Set to output the left channel on high level of DSEL output (PCM mode). Clear to output the left channel on the low level of DSEL output (I2S mode). Set to select 32-bit data output format. Clear to select 16-bit data output format. Set by software when the PLL clock frequency is 384·Fs. Clear by software when the PLL clock frequency is 256·Fs. Set to select C51 as audio source for voice or sound playing. Clear to select the MP3 decoder output as audio source for song playing.

6 DRQEN

Set to enable data request to the MP3 decoder and to start playing song. Clear to disable data request to the MP3 decoder.

5 MSREQ

Set to prevent the SREQ flag from generating an audio interrupt. Clear to allow the SREQ flag to generate an audio interrupt.

4 MUDRN

Set to prevent the UDRN flag from generating an audio interrupt. Clear to allow the UDRN flag to generate an audio interrupt. The value read from this bit is always 0. Do not set this bit. Refer to Table 85 for bits description. Set to enable the audio interface. Clear to disable the audio interface.

Table 88. AUDSTA Register Table 89. AUDDAT Register Table 90. AUDCLK Register half empty). This bit generates an interrupt if not masked and if enabled in IEN0. Cleared by hardware when samples are loaded in AUDDAT.

6 UDRN

Cleared by hardware when samples are loaded in AUDDAT.

5 AUBUSY

Cleared by hardware when buffer is no more full. The value read from these bits is always 0. Do not set these bits. 8-bit sampling data for voice or sound playing. The value read from these bits is always 0. Do not set these bits. 5-bit divider for audio clock generation.

80 AT8xC51SND2C

Power Amplifier targeted for Li-Ion or Ni-Mh battery powered devices. Figure 53. Audio Interface Block Diagram delta modulator already provides extremely low noise tones energy. as a differential monaural auxiliary input (line level).

• 72dB Dynamic Range, -75dB THD Stereo line-in or microphone interface with 20dB amplification
• 93dB Dynamic Range, -80dB THD Stereo D/A conversion
• 74dB Dynamic Range / -65dB THD for 20mW output power over 32 Ohm loads
• Stereo, Mono and Reverse Stereo Mixer
• Left/Right speaker short-circuit detection flag
• Differential mono auxiliary input amplifier and PA driver
• Audio sampling rates (Fs): 16, 22.05, 24, 32, 44.1 and 48 kHz.

Figure 54. Stereo DAC functional diagram

• D S E L
• S C L K
• D C L K
• D O U T The data interface allows three different data transfer modes: Digital Filter Digital Filter Volume Control Volume Control Volume Control Volume Control SPKR DRV DAC DAC PGA PGA SPKR DRV HSR HSL LINEL LINER Serial to Parallel Interface DSEL DCLK AUXN AUXP AUX PADRV MONON MONOP DOUT SCLK DAC_OLC Gain 6 to -6dB (3dB) LLIG,RLIG Gain 20,12 to -33 dB (3dB) AUXG Gain PA Gain Line Out Gain LLOG, RLOG 0 to -46.5dB (1.5dB) Master Playback Gain 12 to -34dB (1.5dB)

82 AT8xC51SND2C

Figure 55. 20 bit I2S justified mode Figure 56. 20 bit MSB justified mode Figure 57. 20 bit LSB justified mode DCLK signals are provided by microcontroller audio data interface.

• AUDCDIN: is used to transf er data in series from the master to the slave DAC. It is driven by the master.
• AUDCDOUT: is used to transfer data in se ries from the slave DAC to the master. It is driven by the selected slave DAC.
• Serial Clock (AUDCCLK): it is used to synchronize the data transmission both in and out the devices through the AUDCDIN and AUDCDOUT lines. Note: Refer to Table 101. for DAC SPI Interface Description SCLK DSEL DOUT SCLK DSEL DOUT SCLK DSEL DOUT DINTSEL 1:0 Format

00 I2S Justified

01 MSB Justified

84 AT8xC51SND2C

Note that the DLCK must run during any DAC SPI interface access (read or write). Figure 60. DAC SPI Interface Timings Table 91. Dac SPI Interface Timings

Table 93. Line-in gain

86 AT8xC51SND2C

Table 94. Master Playback Gain Table 93. Line-in gain (Continued)

Table 95. Line-out Gain Table 94. Master Playback Gain (Continued)

88 AT8xC51SND2C

Table 96. DAC Output Level Control Figure 61. Mixing / Multiplexing functions Note: Whenever the two mixer inputs are selected, a –6 dB gain is applied to the output signal. Whenever only one input is selected, no gain is applied. Table 95. Line-out Gain (Continued)

Table 97. Master Clock selection (refer to Table 112.) according to Table 98. Table 98. Input Sample Size Selection to Table 112.) according to Table 99. Table 99. Format Selection emphasis filtering, DEEMPEN must be set to high.

90 AT8xC51SND2C

Table 100. DAC Auxlilary Input Gain

4341D–MP3–04/05 Register Table 101. AUXCON Register AUXCON (S:90h) – Auxiliary Control Register Reset Value = 1111 1111b 7 6 5 4 321 0 SDA SCL - AUDCDOUT AUDCDIN AUDCCLK AUDCCS KIN0 Bit Number Bit Mnemonic Description 7S D A TWI Serial Data SDA is the bidirectional Two Wire data line. 6S C L TWI Serial Clock When TWI controller is in master mode, SCL outputs the serial clock to the slave peripherals. When TWI controller is in slave mode, SCL receives clock from the master controller. 5 - Not used. 4 AUDCDOUT Audio Dac SPI Data Output.

3 AUDCDIN Audio Dac SPI Data Input

2 AUDCCLK Audio Dac SPI clock

1 AUDCCS

0K I N 0 Keyboard Input Interrupt.

92 AT8xC51SND2C

4341D–MP3–04/05 Table 102. Dac Control Register Register - DAC_CTRL (00h) Table 103. DAC Left Line In Gain Register - DAC_LLIG (01h)

Description

7O N P A D R V Differential mono PA driver Clear to power down. Set to power up. 6O N A U X I N Differential mono auxiliary input amplifier Clear to power down. Set to power up. 5O N D A C R Right channel DAC Clear to power down. Set to power up. 4O N D A C L Left channel DAC Clear to power down. Set to power up.

3 ONLNOR Right channel line out driver

Clear to power down. Set to power up. 2O N L N O L Left channel line out driver Clear to power down. Set to power up.

1 ONLNIR Right channel line in amplifier

Clear to power down. Set to power up. 0O N L N I L Left channel line in amplifier Clear to power down. Set to power up. 76543210 - - - LLIG4 LLIG3 LLIG2 LLIG1 LLIG0 Bit Number Bit Mnemonic 7:5 - Not used 4:0 LLIG 4:0 Left channel line in analog gain selector

4341D–MP3–04/05 Table 104. DAC Right Line In Gain Register - DAC_RLIG (02h) Table 105. DAC Left Master Playback Gain Register - DAC_LMPG (03h) Table 106. DAC Right Master Playback Gain Register - DAC_RMPG (04h) Table 107. DAC Left Line Out Gain Register - DAC_LLOG (05h) 7:5 - Not used 4:0 RLIG 4:0 Right channel line in analog gain selector 76543210 - - LMPG5 LMPG4 LMPG3 LMPG2 LMPG1 LMPG0 Bit Number Bit Mnemonic 7:6 - Not used 5:0 LMPG 5:0 Left channel master playback digital gain selector 76543210 - - RMPG5 RMPG4 RMPG3 RMPG2 RMPG1 RMPG0 Bit Number Bit Mnemonic 7:6 - Not used 5:0 RMPG 5:0 Right channel master playback digital gain selector 76543210 -- LLOG5 LLOG4 LLOG3 LLOG2 LLOG1 LLOG0 Bit Number Bit Mnemonic 7:6 - Not used 5:0 LLOG 5:0 Left channel line out digital gain selector

94 AT8xC51SND2C

4341D–MP3–04/05 Table 108. DAC Rigth Line Out Gain Register - DAC_RLOG (06h) Table 109. DAC Output Level Control Register - DAC_OLC (07h) 7:6 - Not used 5:0 RLOG 5:0 Right channel line out digital gain selector 76543210 RSHORT ROLC2 RLOC1 RLOC0 LSHORT LOLC2 LOLC1 LOLC0 Bit Number Bit Mnemonic Description 7R S H O R T Right channel short circuit indicator (persistent; after being set, bit is not cleared automatically even after the s hort circuit is eliminated; must be cleared by reset cycle or direct register write operation) 6:4 ROLC 2:0 Right channel output level control selector 3L S H O R T Left channel short circuit indicator ( persistent; after being set, bit is not cleared automatically even after the s hort circuit is eliminated; must be cleared by reset cycle or direct register write operation) 2:0 LOLC 2:0 Left channel output level control selector

Table 110. Dac Mixer Control Register - DAC_MC (08h) Table 111. DAC Mixer Control Register - DAC_CSFC (09h) Set to enable. Clear to disable. 4I N V L Left channel mixer output invert. Set to enable. Clear to disable.

3 RMSMIN2 Right Channel Mono/Stereo Mixer Right Mixed input enable

Set to enable. Clear to disable.

2 RMSMIN1 Right Channel Mono/Stereo Mixer Left Mixed input enable

Set to enable. Clear to disable. Set to enable. Clear to disable. Set to enable. Clear to disable.

4 OVRSEL

96 AT8xC51SND2C

Table 112. Dac Miscellaneous Register - DAC_ MISC (0Ah) Table 113. DAC Precharge Control Register - DAC_ PRECH (0Ch)

3 DITHEN Dither enable (Clear this bit to disable, set to enable)

2 DEEMPEN De-emphasis enable (clear this bit to disable, set to enable)

7 PRCHARGEPAD

Differential mono PA driver pre-charge.

6 PRCHARGEAUX

Differential mono auxiliary input pre-charge.

5 PRCHARGELNO

Right channel line out pre-charge.

4 PRCHARGELNO

Left channel line out pre-charge.

3 PRCHARGELNI

Right channel line in pre-charge.

2 PRCHARGELNIL Left channel line in pre-charge

1 PRCHARGE Master pre-charge

Clear to power down. Set to to power up.

4341D–MP3–04/05 Table 114. DAC Auxilary input gain Register - DAC_ AUXG (0Dh)l Note: Refer to Audio DAC Startup sequence. 7:3 - Not Used.

2 RESMASK Active high reset mask of the audio codec

1 RESFILZ Active low reset of the audio codec filter

0R S T Z Active low reset of the audio codec

98 AT8xC51SND2C

voice CODEC output driver in mobile phones. mal earphone/speaker mode of a telephone handset. should avoid any short-circuit on the load.

• Low Power Mode for Earphone
• Programmable Gain (-22 to +20 dB)
• Fully Differential Structure, Input and Output

Table 115. PA Gain

Table 116. PA Operating Mode Table 117. PA Low Power Mode AUDVDD, HSVDD and VDD must be inferior or equal to AUDVBAT. AUDVBAT must be present at the same time or before AUDVDD, HSVDD and VDD. Note: Refer to the application diagram.

• Desassert the Reset: write 07h at address 10h.
• All precharge and Master on: write FFh at address 0Ch.
• Line Out On: write 30h at address 00h.
• Delay 500 ms.
• Precharge off: write 0Ch at address 01h.
• Delay 1 ms.
• Line Out on, DAC On: write 3Ch at address 00h. Example of power-off: Path DAC to Headset Output
• DAC off: write 30h at address 00h.
• Master off: write 00h at address 0Ch.
• Delay 1 ms.
• All off: write 00h at address 00h APAON APAPRECH Operating Mode 0 0 Stand-By 0 1 Input Capacitors Precharge 1 0 Active Mode 1 1 Forbidden State APALP Power Mode

0 Low power mode

1 High power mode

100 AT8xC51SND2C

Example Start I2S •S t a r t D C L K .

• RSTMASK=1.
• RESFILZ=0 and RSTZ=0.
• RESFILZ=1 and RSTZ=1.
• RSTMASK=0.
• Delay 5 ms.
• ONDACL=1 and ONDACR=1.
• Program all DAC settings: audio format, gains... Example Stop I2S: • DAC off: ONDACL=0 and ONDACR=0.
• Stop I2S and DLCK. Audio PA Sequence PA Power-On Sequence To avoid an audible ‘click’ at start-up, the input capacitors have to be pre-charged before the Power Amplifier. PA Power-Off Sequence To avoid an audible ‘click’ at power-off, the gain should be set to the minimum gain (- 22dB) before setting the Power Amplifier. Precharge Control The power up of the circuit can be perfo rmed independently for several blocks. The sequence flow starts by setting to High the block specific fastcharge control bit and sub- sequently the associated power control bit. Once the power control bit is set to High, the fast charging starts. This action begins a user controlled fastcharge cycle. When the fastcharge period is over, the user must reset the associated fastcharge bit and the block is ready for use. If a power contro l bit is cleared a new power up sequence is needed. The several blocks with independent power control are identified in Table 118. The table describes the power on control and fastcharge bits for each block.

Table 118. Precharge and Power Control Note: Note that all block can be precharged simultaneously.

4341D–MP3–04/05 Register Table 119. PA Control Register - PA_CTRL (11h)l Reset Value = 00000000b 76 5 4 3 2 1 0 -A P A O N APAPREC H APALP APAGAIN3 APAGAIN2 APAGAIN1 APAGAIN0 Bit Number Bit Mnemonic Description 7 - Not used

6 APAON Audio power amplifier on bit

5 APAPRECH Audio power amplifier precharge bit

4 APALP Audio power amplifier low power bit

3:0 APAGAIN3:0 Audio power amplifier gain

102 AT8xC51SND2C

4341D–MP3–04/05 Universal Serial Bus The AT8xC51SND2C implements a USB devi ce controller supporting full speed data transfer. In addition to the default control endpoint 0, it provides 2 other endpoints, which can be configured in control, bulk, interrupt or isochronous modes:

• Endpoint 0: 32-Byte FIFO, default control endpoint
• Endpoint 1, 2: 64-Byte Ping-pong FIFO, This allows the firmware to be developed c onforming to most US B device classes, for example:
• USB Mass Storage Class Bulk-only Transport, Revision 1.0 - September 31, 1999
• USB Human Interface Device Class, Version 1.1 - April 7, 1999
• USB Device Firmware Upgrade Class, Revision 1.0 - May 13, 1999 USB Mass Storage Class Bulk-Only Transport Within the Bulk-only framework, the Control endpoint is only used to transport class- specific and standard USB requests for device set-up and configuration. One Bulk-out endpoint is used to transport commands and data from the host to the device. One Bulk in endpoint is used to transport status and data from the device to the host. The following AT8xC51SND2C configuration adheres to those requirements:
• Endpoint 0: 32 Bytes, Control In-Out
• Endpoint 1: 64 Bytes, Bulk-in
• Endpoint 2: 64 Bytes, Bulk-out USB Device Firmware Upgrade (DFU) The USB Device Firmware Update (DFU) protocol can be used to upgrade the on-chip Flash memory of the AT89C51SND2C. This allows installing product enhancements and patches to devices that ar e already in the field. 2 different configurations and descriptor sets are used to support DFU functions. The Run-Time configuration co-exist with the usual functions of the device, which is USB Mass Storage for AT89C51SND2C. It is used to initiate DFU from the no rmal operating mode. The DFU configuration is used to perform the firmware update after device re-configuration and USB reset. It excludes any other function. Only the default control pipe (endpoint 0) is used to support DFU services in both configurations. The only possible value for t he MaxPacketSize in the DFU configuration is 32 Bytes, which is the size of the FIFO implemented for endpoint 0.

interface a USB link to a data flow stored in a double port memory. device tolerance. Clock recovery is done by a Digital Phase Locked Loop (DPLL) block. ing, CRC generation and checking, and the serial-parallel data conversion. the Dual Port RAM, but also the interface with the C51 core itself. the section “DC Characteristics”. Figure 62. USB Device Controller Block Diagram Figure 63. USB Connection quency must always be 48 MHz. Figure 64. USB Clock Generator and Symbol

48 MHz 12 MHz

104 AT8xC51SND2C

4341D–MP3–04/05 USBCD1:0 USBCLK

48 MHz USB Clock

• NRZI data encoding and decoding.
• Bit stuffing and unstuffing.
• CRC generation and checking.
• ACKs and NACKs automatic generation.
• TOKEN type identifying.
• Address checking.
• Clock recovery (using DPLL).

Figure 65. SIE Block Diagram

48 MHz SysClk

8 Data Out

106 AT8xC51SND2C

device firmware, which reads and writes the endpoint FIFOs. ware (UFI) and software (C51) load. Figure 66. UFI Block Diagram Figure 67. USB Typical Transaction Load

12 MHz DPLL

correctly generated (See “Clock Controller” on page 19).

• Set address After a Reset or a USB reset, the software has to set the FEN (Function Enable) bit in the USBADDR register. This action will allo w the USB controller to answer to the requests sent at the address 0. When a SET_ADDRESS request has been received, the USB controller must only answer to the address defined by the request. The new address should be stored in the USBADDR register. The FEN bit and the FADDEN bit in the USBCON register should be set to allow the USB controller to answer only to requests sent at the new address.
• Set configuration The CONFG bit in the USBCON register should be set after a SET_CONFIGURATION request with a non-zero value. Otherwise, this bit should be cleared. Endpoint Configuration • Selection of an Endpoint The endpoint register access is performed using the UEPNUM register. The registers – UEPSTAX – UEPCONX – UEPDATX – UBYCTX Theses registers correspond to the endpoint whose number is stored in the UEP- NUM register. To select an Endpoint, the firmware has to write the endpoint number in the UEPNUM register.

Figure 68. Endpoint Selection

108 AT8xC51SND2C

• Endpoint enable Before using an endpoint, this must be enabled by setting the EPEN bit in the UEP- CONX register. An endpoint which is not enabled won’t ans wer to any USB request. The Default Control Endpoint (Endpoint 0) should always be enabled in order to answer to USB standard requests.
• Endpoint type configuration All Standard Endpoints can be configured in Control, Bulk, Interrupt or Isochronous mode. The Ping-pong Endpoints can be configured in Bulk, Interrupt or Isochronous mode. The configuration of an endpoint is performed by setting the field EPTYPE with the following values: – Control: EPTYPE = 00b – Isochronous:EPTYPE = 01b – Bulk: EPTYPE = 10b – Interrupt: EPTYPE = 11b The Endpoint 0 is the Default Control Endpoint and should always be configured in Control type.
• Endpoint direction configuration For Bulk, Interrupt and Isochronous endpoints, the direction is defined with the EPDIR bit of the UEPCONX register with the following values: – IN: EPDIR = 1b – OUT: EPDIR = 0b For Control endpoints, the EPDIR bit has no effect.
• Summary of Endpoint Configuration: Do not forget to select the correct endpoint number in the UEPNUM register before accessing endpoint specific registers.

Table 120. Summary of Endpoint Configuration

• Endpoint FIFO reset Before using an endpoint, its FIFO should be reset. This action resets the FIFO pointer to its original value, resets the Byte counter of the endpoint (UBYCTX regis- ter), and resets the data toggle bit (DTGL bit in UEPCONX). The reset of an endpoint FIFO is performed by setting to 1 and resetting to 0 the corresponding bit in the UEPRST register. For example, in order to reset the Endpoint number 2 FIFO, write 0000 0100b then 0000 0000b in the UEPRST register. Note that the endpoint reset doesn’t reset the bank number for ping-pong endpoints. Read/Write Data FIFO Read Data FIFO The read access for each OUT endpoint is performed using the UEPDATX register. After a new valid packet has been received on an Endpoint, the data are stored into the FIFO and the Byte counter of the endpoint is updated (UBYCTX registers). The firmware has to store the endpoint Byte counter before any access to the endpoint FIFO. The Byte counter is not updated when reading the FIFO. To read data from an endpoint, select the correct endpoint number in UEPNUM and read the UEPDATX register. This action automatically decreases the corresponding address vector, and the next data is then available in the UEPDATX register. Write Data FIFO The write access for each IN endpoint is performed using the UEPDATX register. To write a Byte into an IN endpoint FIFO, select the correct endpoint number in UEP- NUM and write into the UEPDATX register. The corresponding address vector is automatically increased, and another write can be carried out. Warning 1: The Byte counter is not updated. Warning 2: Do not write more Bytes than supported by the corresponding endpoint. FIFO Mapping

Figure 69. Endpoint FIFO Configuration

110 AT8xC51SND2C

Bulk and Interrupt transactions are managed in the same way. Figure 70. Bulk/Interrupt OUT transactions in Standard Mode to 0 and no data has to be read. answer a NAK handshake for each OUT requests. correct and the endpoint Byte counter contains the number of Bytes sent by the Host.

Figure 71. Bulk/Interrupt OUT Transactions in Ping-pong Mode equal to 0 and no data has to be read. OUT requests on the bank 0 endpoint FIFO. OUT requests on the bank 1 endpoint FIFO. a new valid packet to be stored in the corresponding bank.

112 AT8xC51SND2C

Figure 72. Bulk/Interrupt IN Transactions in Standard Mode should set the TXRDY bit without writing any data into the endpoint FIFO. handshake for each IN requests. The firmware should never write more Bytes than supported by the endpoint FIFO. All USB retry mechanisms are automatically managed by the USB controller.

Figure 73. Bulk/Interrupt IN transactions in Ping-pong mode switched, and the firmware can immediately write into the endpoint FIFO bank 1. bank 0 with new data. The FIFO banks are then automatically switched. The firmware should never write more Bytes than supported by the endpoint FIFO.

114 AT8xC51SND2C

4341D–MP3–04/05 Control Transactions Setup Stage The DIR bit in the UEPSTAX register should be at 0. Receiving Setup packets is the same as re ceiving Bulk Out packets, except that the RXSETUP bit in the UEPSTAX register is set by the USB controller instead of the RXOUTB0 bit to indicate that an Out packet with a Setup PID has been received on the Control endpoint. When the RXSE TUP bit has been set, all th e other bits of the UEP- STAX register are cleared and an interrupt is triggered if enabled. The firmware has to read the Setup request stored in the Control endpoint FIFO before clearing the RXSETUP bit to free the endpoint FIFO for the next transaction. Data Stage: Control Endpoint Direction The data stage management is similar to Bulk management. A Control endpoint is managed by the USB controller as a full-duplex endpoint: IN and OUT. All other endpoint types are managed as half-duplex endpoint: IN or OUT. The firmware has to specify the control endpoint direction for the data stage using the DIR bit in the UEPSTAX register.

• If the data stage consists of INs, the fi rmware has to set the DIR bit in the UEPSTAX register before writing into the FIFO and sending the data by setting to 1 the TXRDY bit in the UEPSTAX register. The IN transaction is complete when the TXCMPL has been set by the hardware. The firmware should clear the TXCMPL bit before any other transaction.
• If the data stage consists of OUTs, the fi rmware has to leave the DIR bit at 0. The RXOUTB0 bit is set by hardware when a new valid packet has been received on the endpoint. The firmware must read the data stored into the FIFO and then clear the RXOUTB0 bit to reset the FIFO and to allow the next transaction. To send a STALL handshake, see “STALL Handshake” on page 117. Status Stage The DIR bit in the UEPSTAX register should be reset at 0 for IN and OUT status stage. The status stage management is similar to Bulk management.
• For a Control Write transaction or a No-Data Control transaction, the status stage consists of a IN Zero Length Packet (see “Bulk/Interrupt IN Transactions in Standard Mode” on page 112). To send a STALL handshake, see “STALL Handshake” on page 117.
• For a Control Read transaction, the status stage consists of a OUT Zero Length Packet (see “Bulk/Interrupt OUT Transactions in Standard Mode” on page 110).

4341D–MP3–04/05 Isochronous Transactions Isochronous OUT Transactions in Standard Mode An endpoint should be first enabled and configured before being able to receive Isochro- nous packets. When an OUT packet is received on an en dpoint, the RXOUTB0 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware has to select the corre Bulk-outsponding endpoint, store the numbe r of data Bytes by reading the UBYCTX register. If the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has to be read. The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet stored in FIFO has a corrupted CRC. This bit is updated after each new packet receipt. When all the endpoint FIFO Bytes have been read, the firmware should clear the RXOUTB0 bit to allow the USB controller to store the next OUT packet data into the endpoint FIFO. Until the RXOU TB0 bit has been cleared by the firmware, the data sent by the Host at each OUT transaction will be lost. If the RXOUTB0 bit is cleared while the Host is sending data, the USB controller will store only the remaining Bytes into the FIFO. If the Host sends more Bytes than support ed by the endpoint FIFO, the overflow data won’t be stored, but the USB controller will consider that the packet is valid if the CRC is correct. Isochronous OUT Transactions in Ping-pong Mode An endpoint should be first enabled and configured before being able to receive Isochro- nous packets. When a OUT packet is received on the endpoi nt bank 0, the RXOUTB0 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware has to select the cor- responding endpoint, store the number of data Bytes by reading the UBYCTX register. If the received packet is a ZLP (Zero Length Pa cket), the UBYCTX register value is equal to 0 and no data has to be read. The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet stored in FIFO has a corrupted CRC. This bit is updated after each new packet receipt. When all the endpoint FIFO Bytes have been read, the firmware should clear the RXOUB0 bit to allow the USB controller to store the next OUT packet data into the end- point FIFO bank 0. This action switches the endpoint bank 0 and 1. Until the RXOUTB0 bit has been cleared by the firmware, the data sent by the Host on the bank 0 endpoint FIFO will be lost. If the RXOUTB0 bit is cleared while the Host is sending data on the endpoint bank 0, the USB controller will store only the remaining Bytes into the FIFO. When a new OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware empties the bank 1 endpoint FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has been cleared by the firmware, the da ta sent by the Host on the bank 1 endpoint FIFO will be lost. The RXOUTB0 and RXOUTB1 bits are alternat ively set by the USB controller at each new packet receipt. The firmware has to clear one of these 2 bits after having read all the data FIFO to allow a new packet to be stored in the corresponding bank.

116 AT8xC51SND2C

4341D–MP3–04/05 If the Host sends more Bytes than support ed by the endpoint FIFO, the overflow data won’t be stored, but the USB controller will consider that the packet is valid if the CRC is correct. Isochronous IN Transactions in Standard Mode An endpoint should be first enabled and configured before being able to send Isochro- nous packets. The firmware should fill the FIFO with the dat a to be sent and set the TXRDY bit in the UEPSTAX register to allow the USB controlle r to send the data stored in FIFO at the next IN request concerning this endpoint. If the TXRDY bit is not set wh en the IN request occurs, no thing will be sent by the USB controller. When the IN packet has been sent, the TXCMPL bit in the UEPSTAX register is set by the USB controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO with new data. The firmware should never write more Bytes than supported by the endpoint FIFO Isochronous IN Transactions in Ping-pong Mode An endpoint should be first enabled and configured before being able to send Isochro- nous packets. The firmware should fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in the UEPSTAX register to allo w the USB controller to send the data stored in FIFO at the next IN request concerning the endpo int. The FIFO banks are automatically switched, and the firmware can immediately write into the endpoint FIFO bank 1. If the TXRDY bit is not set wh en the IN request occurs, no thing will be sent by the USB controller. When the IN packet concerning the bank 0 has been sent, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO bank 0 with new data. The FIFO banks are then automatically switched. When the IN packet concerning the bank 1 has been sent, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO bank 1 with new data. The bank switch is performed by the USB cont roller each time the TXRDY bit is set by the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank, the USB controller won’t send anything at each IN requests concerning this bank. The firmware should never write more Bytes than supported by the endpoint FIFO.

4341D–MP3–04/05 Miscellaneous USB Reset The EORINT bit in the USBINT register is set by hardware when a End Of Reset has been detected on the USB bus. This triggers a USB interrupt if enabled. The USB con- troller is still enabled, but all the USB registers are rese t by hardware. The firmware should clear the EORINT bit to allow the next USB reset detection. STALL Handshake This function is only available for Control, Bulk, and Interrupt endpoints. The firmware has to set the STALLRQ bit in the UEPSTAX register to send a STALL handshake at the next request of the Host on the endpoint selected with the UEPNUM register. The RXSETUP, TXRDY, TXCMPL, RXOUTB0 and RXOUTB1 bits must be first resseted to 0. The bit STLCRC is set at 1 by the USB controller when a STALL has been sent. This triggers an interrupt if enabled. The firmware should clear the STALLRQ and STLCRC bits after each STALL sent. The STALLRQ bit is cleared automatically by hardware when a valid SETUP PID is received on a CONTROL type endpoint. Important note: when a Clear Halt Feature occurs for an endpoint, the firmware should reset this endpoint using the UEPRST resgister in order to reset the data toggle management. Start of Frame Detection The SOFINT bit in the USBINT register is set when the USB controller detects a Start Of Frame PID. This triggers an interrupt if enabled. The firmware should clear the SOFINT bit to allow the next Start of Frame detection. Frame Number When receiving a Start Of Frame, the fr ame number is automatically stored in the UFNUML and UFNUMH registers. The CRCOK and CRCERR bits indicate if the CRC of the last Start Of Frame is valid (CRCOK set at 1) or corrupted (CRCERR set at 1). The UFNUML and UFNUMH registers are automatically updated when receiving a new Start of Frame. Data Toggle Bit The Data Toggle bit is set by hardware when a DATA0 packet is received and accepted by the USB controller and cleared by hardware when a DATA1 packet is received and accepted by the USB controller. This bit is reset when the firmware resets the endpoint FIFO using the UEPRST register. For Control endpoints, each SETUP transacti on starts with a DATA0 and data toggling is then used as for Bulk endpoints until the end of the Data stage (for a control write transfer). The Status stage completes the data transfer with a DATA1 (for a control read transfer). For Isochronous endpoints, the device firmware should ignore the data-toggle.

118 AT8xC51SND2C

state is detected for more than 3 ms. This triggers a USB interrupt if enabled. exits of idle mode when a wake-up event is detected.

1. Disable of the 48 MHz clock input of th e USB controller by setting to 1 the SUS-

PCLK bit in the USBCON register.

1. Disable the PLL by clearing the PLLEN bit in the PLLCON register.

ation and then reset to 0 the SUSPCLK bit in the USBCON register if needed. operation in order to wake up the USB controller from its Suspend mode. The USB controller is then re-activated. Figure 74. Example of a Suspend/Resume Management

Figure 75. Example of REMOTE WAKEUP Management

120 AT8xC51SND2C

Table 1. Priority Levels

• TXCMPL: Transmitted In Data (Table 127 on page 126). This bit is set by hardware when the Host accept a In packet.
• RXOUTB0: Received Out Data Bank 0 (Table 127 on page 126). This bit is set by hardware when an Out packet is accepted by the endpoint and stored in bank 0.
• RXOUTB1: Received Out Data Bank 1 (only for Ping-pong endpoints) (Table 127 on page 126). This bit is set by hardware when an Out packet is accepted by the endpoint and stored in bank 1.
• RXSETUP: Received Setup (Table 127 on page 126). This bit is set by hardware when an SETUP packet is accepted by the endpoint.
• STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints) (Table 127 on page 126). This bit is set by hardware when a STALL handshake has been sent as requested by STALLRQ, and is reset by hardware when a SETUP packet is received.
• SOFINT: Start of Frame Interrupt (Table 123 on page 123). This bit is set by hardware when a USB start of frame packet has been received.
• WUPCPU: Wake-Up CPU Interrupt (Table 123 on page 123). This bit is set by hardware when a USB resume is detected on the USB bus, after a SUSPEND state.
• SPINT: Suspend Interrupt (Table 123 on page 123). This bit is set by hardware when a USB suspend is detected on the USB bus. EUSB IE1.6 EA IE0.7 USB Controller IPH/L Interrupt Enable Lowest Priority InterruptsPriority Enable IPHUSB IPLUSB USB Priority Level 01 1 10 2

Figure 77. USB Interrupt Control Block Diagram

122 AT8xC51SND2C

4341D–MP3–04/05 Registers Table 121. USBCON Register USBCON (S:BCh) – USB Global Control Register Reset Value = 0000 0000b 76543210 USBE SUSPCLK SDRMWUP - UPRSM RMWUPE CONFG FADDEN Bit Number Bit Mnemonic Description

7 USBE

Set this bit to enable the USB controller. Clear this bit to disable and reset t he USB controller, to disable the USB transceiver an to disable the USB controllor clock inputs. 6S U S P C L K Suspend USB Clock Bit Set to disable the 48 MHz clock input (Resume Detection is still active). Clear to enable the 48 MHz clock input.

5 SDRMWUP

Set to force an external interrupt on the USB controller for Remote Wake UP purpose. An upstream resume is send only if the bit RMWUPE is set, all USB clocks are enabled AND the USB bus was in SUSPEND state for at least 5 ms. See UPRSM below. Cleared by software. 4- Reserved The value read from this bit is always 0. Do not set this bit.

3 UPRSM

Upstream Resume Bit (read only) Set by hardware when SDRMWUP has been set and if RMWUPE is enabled. Cleared by hardware after the upstream resume has been sent. 2R M W U P E Remote Wake-Up Enable Bit Set to enabled request an upstream resume signaling to the host. Clear after the upstream resume has been indicated by RSMINPR. Note: Do not set this bit if the host has not set the DEVICE_REMOTE_WAKEUP feature for the device. 1C O N F G Configuration Bit This bit should be set by the device firmware after a SET_CONFIGURATION request with a non-zero value has been correctly processed. It should be cleared by the device firmware when a SET_CONFIGURATION request with a zero value is received . It is cleared by hardware on hardware reset or when an USB reset is detected on the bus (SE0 state for at least 32 Full Speed bit times: typically 2.7 µs). 0F A D D E N Function Address Enable Bit This bit should be set by the device firmware after a successful status phase of a SET_ADDRESS transaction. It should not be cleared afterwards by the device firmware. It is cleared by hardware on hardware reset or when an USB reset is received (see above). When this bit is cleared, the default function address is used (0).

Table 122. USBADDR Register Table 123. USBINT Register the default address (FEN is reset to 0). This field contains the default address (0) after power-up or USB bus reset. The value read from these bits is always 0. Do not set these bits.

5 WUPCPU

triggers a USB interrupt when EWUPCPU is set in the USBIEN. Cleared by software after re-enabling all USB clocks. Set by hardware when a End of Reset has been detected by the USB controller. This triggers a USB interrupt when EEORINT is set in USBIEN. received. This triggers a USB interrupt when ESOFINT is set in USBIEN. The value read from these bits is always 0. Do not set these bits.

0 SPINT

124 AT8xC51SND2C

Table 124. USBIEN Register Table 125. UEPNUM Register The value read from these bits is always 0. Do not set these bits.

5 EWUPCPU

Set to enable the Wake Up CPU interrupt. Clear to disable the Wake Up CPU interrupt. Set to enable the End Of Reset interrupt. This bit is set after reset. Clear to disable End Of Reset interrupt. Set to enable the SOF interrupt. Clear to disable the SOF interrupt. The value read from these bits is always 0. Do not set these bits.

0 ESPINT

Set to enable Suspend interrupt. Clear to disable Suspend interrupt. The value read from these bits is always 0. Do not set these bits. reading or writing to registers UEPSTAX, UEPDATX, UBYCTX or UEPCONX.

Table 126. UEPCONX Register

7 EPEN

Clear to disable the endpoint according to the device configuration. Set this bit to enable NAK IN or NAK OUT interrupt. Clear this bit to disable NAK IN or NAK OUT Interrupt.

5 NAKOUT

This bit should be cleared by software.

4 NAKIN

of a IN request from the Host. This triggers a USB interrupt when NAKIEN is set. This bit should be cleared by software. Set by hardware when a DATA1 packet is received. Cleared by hardware when a DATA0 packet is received.

2 EPDIR

Set to configure IN direction for Bulk, Interrupt and Isochronous endpoints. Clear to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. This bit has no effect for Control endpoints.

00 Control endpoint

01 Isochronous endpoint

10 Bulk endpoint

11 Interrupt endpoint

126 AT8xC51SND2C

Table 127. UEPSTAX Register This bit is relevant only if the endpoint is configured in Control type. Set for the data stage. Clear otherwise.

6 RXOUTB1

4341D–MP3–04/05 Reset Value = 0000 0000b

5 STALLRQ Stall Handshake Request Bit

Set to send a STALL answer to the host for the next handshake. Clear otherwise.

4 TXRDY

TX Packet Ready Control Bit Set after a packet has been written into the endpoint FIFO for IN data transfers. Data should be written into the endpoint FIFO only after this bit has been cleared. Set this bit without writing data to the endpoint FIFO to send a Zero Length Packet, which is generally recommended and may be required to terminate a transfer when the length of the last data packet is equal to MaxPacketSize (e.g. for control read transfers). Cleared by hardware, as soon as th e packet has been sent for Isochronous endpoints, or after the host has acknowledged the packet for Control, Bulk and Interrupt endpoints. 3S T L C R C Stall Sent Interrupt Flag/CRC Error Interrupt Flag For Control, Bulk and Interrupt Endpoints: Set by hardware after a STALL handshake has been sent as requested by STALLRQ. Then, the endpoint interrupt is triggered if enabled in UEPIEN. Cleared by hardware when a SETUP packet is received (see RXSETUP). For Isochronous Endpoints: Set by hardware if the last data received is corrupted (CRC error on data). Then, the endpoint interrupt is triggered if enabled in UEPIEN. Cleared by hardware when a non corrupted data is received.

2 RXSETUP

Received SETUP Interrupt Flag Set by hardware when a valid SETUP packet has been received from the host. Then, all the other bits of the register are cleared by hardware and the endpoint interrupt is triggered if enabled in UEPIEN. Clear by software after reading the SETUP data from the endpoint FIFO.

1 RXOUTB0

Received OUT Data Bank 0 (see also RXOUTB1 bit for Ping-pong Endpoints) This bit is set by hardware after a new packet has been stored in the endpoint FIFO data bank 0. Then, the endpoint interrupt is triggered if enabled and all the following OUT packets to the endpoint bank 0 are rejected (NAK’ed) until this bit has been cleared, excepted for Isochronous Endpoints. However, for control endpoints, an early SETUP transaction may overwrite the content of the endpoint FIFO, even if its Data packet is received while this bit is set. This bit should be cleared by the devi ce firmware after reading the OUT data from the endpoint FIFO. 0T X C M P Transmitted IN Data Complete Interrupt Flag Set by hardware after an IN pack et has been transmitted for Isochronous endpoints and after it has been accepted (ACK’ed) by the host for Control, Bulk and Interrupt endpoints. Then, the endpoint interrupt is triggered if enabled in UEPIEN. Clear by software before setting again TXRDY. Bit Number Bit Mnemonic Description

128 AT8xC51SND2C

Table 128. UEPRST Register Table 129. UEPIEN Register The value read from these bits is always 0. Do not set these bits.

2 EP2RST

hardware reset or when an USB bus reset has been received.

1 EP1RST

hardware reset or when an USB bus reset has been received.

0 EP0RST

hardware reset or when an USB bus reset has been received. The value read from these bits is always 0. Do not set these bits.

2 EP2INTE

Set to enable the interrupts for endpoint 2. Clear this bit to disable the interrupts for endpoint 2.

1 EP1INTE

Set to enable the interrupts for the endpoint 1. Clear to disable the interrupts for the endpoint 1.

0 EP0INTE

Set to enable the interrupts for the endpoint 0. Clear to disable the interrupts for the endpoint 0.

Table 130. UEPINT Register Table 131. UEPDATX Register The value read from these bits is always 0. Do not set these bits.

2 EP2INT

and can be: TXCMP , RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP2IE bit in the UEPIEN register is set.

1 EP1INT

and can be: TXCMP , RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP1IE bit in the UEPIEN register is set.

0 EP0INT

and can be: TXCMP , RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP0IE bit in the UEPIEN register is set.

130 AT8xC51SND2C

Table 132. UBYCTX Register Table 133. UFNUML Register The value read from this bits is always 0. Do not set this bit. data Bytes received after the Data PID. Lower 8 bits of the 11-bit Frame Number.

Table 134. UFNUMH Register Table 135. USBCLK Register The value read from these bits is always 0. Do not set these bits.

5 CRCOK

Updated after every Start Of Frame packet reception. Note: The Start Of Frame interrupt is generated just after the PID receipt.

4 CRCERR

Updated after every Start Of Frame packet reception. Note: The Start Of Frame interrupt is generated just after the PID receipt. The value read from this bits is always 0. Do not set this bit. packet. FNUM does not change if a corrupted SOF is received. The value read from these bits is always 0. Do not set these bits. 2-bit divider for USB controller clock generation.

132 AT8xC51SND2C

bit data transfer (read or write) between the AT8xC51SND2C and the IDE device. data (as in 8-bit mode) while DAT16H register (see Table 137) contains D15:8 data. Figure 78 shows the IDE read bus cycle while Figure 79 shows the IDE write bus cycle. Section “AC Characteristics”. mode, refer to the Section “X2 Feature”, page 12. from 3 to 15 CPU clock periods. Figure 78. IDE Read Waveforms Notes: 1. RD signal may be stretched using M0 bit in AUXR register.

1. When executing MOVX @Ri instruction, P2 outputs SFR content.
2. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode),

P2 outputs SFR content instead of DPH.

134 AT8xC51SND2C

Table 136. External Data Memory Interface Signals Upper address lines for the external bus. Multiplexed higher address and data lines for the IDE interface. prior any MOVX write instruction.

4341D–MP3–04/05 MultiMedia Card Controller The AT8xC51SND2C implements a MultiMedi a Card (MMC) controller. The MMC is used to store MP3 encoded audio files in removable Flash memory cards that can be easily plugged or removed from the application. Card Concept The basic MultiMedia Card concept is based on transferring data via a minimum number of signals. Card Signals The communication signals are:

• CLK: with each cycle of this signal a one bit transfer on the command and data lines is done. The frequency may vary from zero to the maximum clock frequency.
• CMD: is a bi-directional command channel used for card initialization and data transfer commands. The CMD signal has 2 operation modes: open-drain for initialization mode and push-pull for fast command transfer. Commands are sent from the MultiMedia Card bus master to the card and responses from the cards to the host.
• DAT: is a bi-directional data channel. The DAT signal operates in push-pull mode. Only one card or the host is driving this signal at a time. Card Registers Within the card interface fi ve registers are defined: O CR, CID, CSD, RCA and DSR. These can be accessed only by the corresponding commands. The 32-bit Operation Conditions Register (OCR) stores the V DD voltage profile of the card. The register is optional and can be read only. The 128-bit wide CID register carries the ca rd identification information (Card ID) used during the card identification procedure. The 128-bit wide Card-Specific Data register (CSD) provides information on how to access the card contents. The CSD defines the data format, error correction type, maxi- mum data access time, data transfer speed, and whether the DSR register can be used. The 16-bit Relative Card Address register (RCA) carries the card address assigned by the host during the card identification. This address is used for the addressed host-card communication after the card identification procedure. The 16-bit Driver Stage Register (DSR) can be optionally used to improve the bus per- formance for extended operating conditions (depending on parameters like bus length, transfer rate or number of cards). Bus Concept The MultiMedia Card bus is designed to c onnect either solid-state mass-storage mem- ory or I/O-devices in a card format to multimedia applications. The bus implementation allows the coverage of application fields from low-cost systems to systems with a fast data transfer rate. It is a single master bu s with a variable number of slaves. The Multi- Media Card bus master is the bus controller and each slave is either a single mass storage card (with possibly different technolog ies such as ROM, OTP, Flash etc.) or an I/O-card with its own controlling unit (on card) to perform the data transfer. The MultiMedia Card bus also includes power connections to supply the cards. The bus communication uses a special protocol (MultiMedia Card bus protocol) which is applicable for all devices. Therefore, the payload data transfer between the host and the cards can be bi-directional.

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reduces the connection costs of the MultiMedia Card system.

• Power supply: V SS1 and VSS2, VDD – used to supply the cards.
• Data transfer: MCMD, MDAT – used for bi-directional communication.
• Clock: MCLK – used to synchroniz e data transfer across the bus. Bus Protocol After a power-on reset, the host must initialize the cards by a special message-based MultiMedia Card bus protocol. Each message is represented by one of the following tokens:
• Command: a command is a token which starts an operation. A command is transferred serially from the host to the card on the MCMD line.
• Response: a response is a token which is sent from an addressed card (or all connected cards) to the host as an answer to a previously received command. It is transferred serially on the MCMD line.
• Data: data can be transferred from the card to the host or vice-versa. Data is transferred serially on the MDAT line. Card addressing is implemented using a se ssion address assigned during the initializa- tion phase, by the bus controller to all cu rrently connected cards. Individual cards are identified by their CID number. This method requires that every card will have an unique CID number. To ensure uniqueness of CIDs the CID register contains 24 bits (MID and OID fields) which are defined by the MMCA. Every card manufacturers is required to apply for an unique MID (and optionally OID) number. MultiMedia Card bus data transfers are composed of these tokens. One data transfer is a bus operation. There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token, the others transfer their information directly within the command or response structure. In this case no data token is present in an operation. The bits on the MDAT and the MCMD lines are transferred synchronous to the host clock. 2 types of data transfer commands are defined:
• Sequential commands: These commands init iate a continuous data stream, they are terminated only when a stop command follows on the MCMD line. This mode reduces the command overhead to an absolute minimum.
• Block-oriented commands: These commands send a data block succeeded by CRC bits. Both read and write operations allow either single or multiple block transmission. A multiple block transmission is terminated when a stop command follows on the MCMD line similarly to the stream read. Figure 82 through Figure 86 show the different types of operations, on these figures, grayed tokens are from host to card(s) while white tokens are from card(s) to host.

Figure 82. Sequential Read Operation

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Table 138. Command Token Format Figure 88. Response Token Format Table 139. R1 Response Format (Normal Response) Table 140. R2 Response Format (CID and CSD registers)

Table 141. R3 Response Format (OCR Register) Table 142. R4 Response Format (Fast I/O) Table 143. R5 Response Format case. The CRC protection algorithm for block data is a 16-bit CCITT polynomial. Figure 89. Data Token Format mode or to control the data flow (to avoid under-run or ov er-run conditions) on the bus. The host is allowed to lower the clock frequency or shut it down.

• The bus frequency can be changed at any ti me (under the restrictions of maximum data transfer frequency, defined by the cards, and the identification frequency defined by the specification document).
• It is an obvious requiremen t that the clock must be running for the card to output data or response tokens. After the last MultiMedia Card bus transaction, the host is Bit Position 47 46 [45:40] [39:8] [7:1] 0 Width (bits) 11 6 3 2 71 Description Start bit Transmission bit Reserved OCR register Reserved End bit Bit Position 47 46 [45:40] [39:8] [7:1] 0 Width (bits) 11 6 3 2 7 1 Description Start bit Transmission bit Command Index Argument CRC7 End bit Bit Position 47 46 [45:40] [39:8] [7:1] 0 Width (bits) 11 6 3 2 71 Description Start bit Transmission bit Command Index Argument CRC7 End bit

0 Content 1Sequential Data

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• A command with no response. 8 clocks after the host command End bit.
• A command with response. 8 cloc ks after the card command End bit.
• A read data transaction. 8 clocks afte r the End bit of the last data block.
• A write data transaction. 8 clocks after the CRC status token.
• The host is allowed to shut down the clo ck of a “busy” card. T he card will complete the programming operation regardless of the host clock. However, the host must provide a clock edge for the card to turn off its busy signal. Without a clock edge the card (unless previously disconnected by a deselect command-CMD7) will force the MDAT line down, forever. Description The MMC controller interfaces to the C51 co re through the following eight special func- tion registers: MMCON0, MMCON1, MMCON2, the three MMC control registers (see Table 145 to Table 153); MMSTA, the MMC st atus register (see Table 148); MMINT, the MMC inter- rupt register (see Table 149); MMMSK, the MMC interrupt mask register (see Table 150); MMCMD, the MMC command register (see Table 151); MMDAT, the MMC data register (see Table 152); and MMCLK, the MMC clock register (see Table 153). As shown in Figure 90, the MMC controller is divided in four blocks: the clock generator that handles the MCLK (for mally the MMC CLK) output to the card, the command line controller that handles the MCMD (formally the MMC CMD) line traffic to or from the card, the data line controller that handles th e MDAT (formally the MMC DAT) line traffic to or from the card, and the interrupt controller that handles the MMC controller interrupt sources. These blocks are detailed in the following sections.

Figure 90. MMC Controller Block Diagram given by MMCD7:0 bits in MMCLK register, a value of 0x00 stops the MMC clock. Figure 91 shows the MMC clock generator and its output clock calculation formula.

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Figure 93. Command Line Controller Block Diagram

• RESPEN bit in MMCON1 register to indica te whether a response is expected or not.
• RFMT bit in MMCON0 register to indi cate the response size expected.
• CRCDIS bit in MMCON0 register to indi cate whether the CRC7 included in the response will be computed or not. In order to avoid CRC error, CRCDIS may be set for response that do not include CRC7. Figure 94 summarizes the command transmission flow. As soon as command transmission is enabled, the CFLCK flag in MMSTA is set indicat- ing that write to the FIFO is locked. This mechanism is implemented to avoid command overrun. The end of the command transmission is signalled to you by the EOCI flag in MMINT register becoming set. This flag may generate an MMC interrupt request as detailed in Section "Interrupt", page 150. The end of the command transmission also resets the CFLCK flag. CTPTR MMCON0.4 CRPTR MMCON0.5 MCMDCMDEN MMCON1.0 TX COMMAND Line Finished State Machine Data Converter // -> Serial5-Byte FIFO MMCMD TX Pointer RFMT MMCON0.1 CRCDIS MMCON0.0 RESPEN MMCON1.1 Data Converter Serial -> // RX Pointer 17 - Byte FIFO MMCMD CFLCK MMSTA.0 CRC7 Generator RX COMMAND Line Finished State Machine CRC7 and Format Checker CRC7S MMSTA.2 RESPFS MMSTA.1 EOCI MMINT.5 EORI MMINT.6 Command Transmitter Command Receiver Write Read

register which resets the write pointer to the transmit FIFO. Figure 94. Command Transmission Flow register which resets the read pointer to the receive FIFO. clearing the CCR bit in MMCON2 register. This time-out may be disarmed when receiving the response.

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channel and by the data receiver channel. Figure 95. Data Line Controller Block Diagram flags indicating the status full and empty of each FIFO. abort the writing or reading of data. detailed in Section “Interrupt”. Table 144. Figure 96 summarizes the data modes configuration flows. Table 144. Block Length Programming

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Figure 97. Data Stream Transmission Flows

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end of frame (EOFI flag set) in case of block length less than 8 data (1, 2 or 4). becomes full (F1FI or F2FI set), user is requested to flush this FIFO by reading 8 data. Figure 99. Data Stream Reception Flows

Figure 100. Data Block Reception Flows

• MMCLK is stopped when both FIFOs become empty: F1EI and F2EI set.
• MMCLK is restarted when one of the FI FOs becomes full: F1EI or F2EI cleared. During reception, setting the FLOWC bit has the following effects:
• MMCLK is stopped when both FIFOs become full: F1FI and F2FI set.
• MMCLK is restarted when one of the FIFOs becomes empty: F1FI or F2FI cleared. As soon as the clock is stopped, the MMC bus is frozen and remains in its state until the clock is restored by writing or reading data in MMDAT. Data Block Reception Start Transmission DATEN = 1 DATEN = 0FIFO Full? F1EI or F2EI = 1? FIFO Reading read 8 data from MMDAT No More Data To Receive? a. Polling mode Data Block Initialization Start Transmission DATEN = 1 DATEN = 0 Data Block Reception ISR FIFO Reading read 8 data from MMDAT No More Data To Receive? b. Interrupt mode FIFO Full? F1EI or F2EI = 1? Mask FIFOs Full F1FM = 1 F2FM = 1 Unmask FIFOs Full F1FM = 0 F2FM = 0

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flags are detailed in the previous sections. F1FM, and F2EM mask bits respectively in MMMSK register. MMC controller interrupt enable bit is set (EMMC in IEN1 register). Reading the MMINT register automatically clears the interrupt flags (acknowledgment). flag to be sure not to forget any interrupts. Figure 101. MMC Controller Interrupt System

4341D–MP3–04/05 Registers Table 145. MMCON0 Register MMCON0 (S:E4h) – MMC Control Register 0 Reset Value = 0000 0000b 76543210 DRPTR DTPTR CRPTR CTPTR MBLOCK DFMT RFMT CRCDIS Bit Number Bit Mnemonic Description 7D R P T R Data Receive Pointer Reset Bit Set to reset the read pointer of the data FIFO. Clear to release the read pointer of the data FIFO.

6 DTPTR

Data Transmit Pointer Reset Bit Set to reset the write pointer of the data FIFO. Clear to release the write pointer of the data FIFO. 5C R P T R Command Receive Pointer Reset Bit Set to reset the read pointer of the receive command FIFO. Clear to release the read pointer of the receive command FIFO.

4 CTPTR

Command Transmit Pointer Reset Bit Set to reset the write pointer of the transmit command FIFO. Clear to release the read pointer of the transmit command FIFO. 3M B L O C K Multi-block Enable Bit Set to select multi-block data format. Clear to select single block data format. 2D F M T Data Format Bit Set to select the block-oriented data format. Clear to select the stream data format. 1R F M T Response Format Bit Set to select the 48-bit response format. Clear to select the 136-bit response format.

0 CRCDIS

Set to disable the CRC7 computation when receiving a response. Clear to enable the CRC7 computation when receiving a response.

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Table 146. MMCON1 Register Table 147. MMCON2 Register Set to select data transfer from host to card (write mode). Clear to select data transfer from card to host (read mode).

1 RESPEN

Set and clear to enable transmission of the command FIFO to the card.

7 MMCEN

Set to enable the MCLK clocks and activate the MMC controller. Clear to disable the MMC clocks and freeze the MMC controller. Set and clear to reset the data line controller in case of transfer abort. Set and clear to reset the command line controller in case of transfer abort. The value read from these bits is always 0. Do not set these bits. Set to enable the flow control during data transfers. Clear to disable the flow control during data transfers.

Table 148. MMSTA Register The value read from these bits is always 0. Do not set these bits.

5 CBUSY

Set by hardware when the card sends a busy state on the data line. Cleared by hardware when the card no more sends a busy state on the data line.

4 CRC16S

Set by hardware when the token response reports a good CRC. Cleared by hardware when the token response reports a bad CRC. Set by hardware when the CRC16 received in the data block is correct. Cleared by hardware when the CRC16 received in the data block is not correct. Set by hardware when the format of the token response is correct. Cleared by hardware when the format of the token response is not correct. Set by hardware when the format of the frame is correct. Cleared by hardware when the format of the frame is not correct.

2 CRC7S

Set by hardware when the CRC7 computed in the response is correct. Cleared by hardware when the CRC7 computed in the response is not correct. This bit is not relevant when CRCDIS is set.

1 RESPFS

Set by hardware when the format of a response is correct. Cleared by hardware when the format of a response is not correct.

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Table 149. MMINT Register signal is asserted or deasserted on the data line). Set by hardware at the end of response reception. Set by hardware at the end of command transmission. Set by hardware at the end of frame (stream or block) transfer. Set by hardware when second FIFO becomes full. Cleared by hardware when second FIFO becomes empty. Set by hardware when first FIFO becomes full. Cleared by hardware when first FIFO becomes empty. Set by hardware when second FIFO becomes empty. Cleared by hardware when second FIFO becomes full. Set by hardware when first FIFO becomes empty. Cleared by hardware when first FIFO becomes full.

Table 150. MMMSK Register Table 151. MMCMD Register Set to prevent MCBI flag from generating an MMC interrupt. Clear to allow MCBI flag to generate an MMC interrupt. Set to prevent EORI flag from generating an MMC interrupt. Clear to allow EORI flag to generate an MMC interrupt. Set to prevent EOCI flag from generating an MMC interrupt. Clear to allow EOCI flag to generate an MMC interrupt. Set to prevent EOFI flag from generating an MMC interrupt. Clear to allow EOFI flag to generate an MMC interrupt. Set to prevent F2FI flag from generating an MMC interrupt. Clear to allow F2FI flag to generate an MMC interrupt. Set to prevent F1FI flag from generating an MMC interrupt. Clear to allow F1FI flag to generate an MMC interrupt. Set to prevent F2EI flag from generating an MMC interrupt. Clear to allow F2EI flag to generate an MMC interrupt. Set to prevent F1EI flag from generating an MMC interrupt. Clear to allow F1EI flag to generate an MMC interrupt. Output (read) register of the response FIFO. Input (write) register of the command FIFO.

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Table 152. MMDAT Register Table 153. MMCLK Register Input (write) or output (read) register of the data FIFO. 8-bit divider for MMC clock generation.

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Table 156); and SPDAT, the SPI data register (see Table 157). Master Mode The SPI operates in master mode when the MSTR bit in SPCON is set. register updated at the end of each transfer. The Byte begins shifting out on the MOSI pin under the control of the bit rate generator. Figure 104. SPI Master Mode Block Diagram Note: MSTR bit in SPCON is set to select master mode.

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Table 154. Serial Bit Rates Notes: 1. These frequencies are achieved in X1 mode, F PER = FOSC ÷ 2.

1. These frequencies are achieved in X2 mode, F PER = FOSC.

while the selected slave captures data from the SO line. Note: 1. When the peripher al is disabled (SPEN = 0), default SCK line is high level. Figure 106. Data Transmission Format (CPHA = 0)

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and is cleared by reading SPSTA and then reading from or writing to SPDAT. rupts are globally enabled by setting EA bit in IEN0 register. Figure 109. SPI Interrupt System

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rupt. Using this flow prevents any overrun error occurrence. The bit rate is selected according to Table 154. The transfer format depends on the slave peripheral. may be deasserted between transfers depending also on the slave peripheral. Reading SPSTA at the beginning of the ISR is mandatory for cl earing the SPIF flag. Clear is effective when reading SPDAT. Figure 111. Master SPI Interrupt Flows

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The transfer format depends on the master controller. Reading SPSTA at the beginning of the ISR is mandatory for cl earing the SPIF flag. Clear is effective when reading SPDAT. Figure 113. Slave SPI Interrupt Policy Flows

4341D–MP3–04/05 Registers Table 155. SPCON Register SPCON (S:C3h) – SPI Control Register Reset Value = 0001 0100b Note: 1. When the SPI is disabled, SCK outputs high level. 76543210 SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0 Bit Number Bit Mnemonic Description

7 SPR2 SPI Rate Bit 2

Refer to Table 154 for bit rate description.

6 SPEN

Set to enable the SPI interface. Clear to disable the SPI interface.

5 SSDIS

Slave Select Input Disable Bit Set to disable SS in both master and slave modes. In slave mode this bit has no effect if CPHA = 0. Clear to enable SS in both master and slave modes. 4M S T R Master Mode Select Set to select the master mode. Clear to select the slave mode. 3C P O L SPI Clock Polarity Bit(1) Set to have the clock output set to high level in idle state. Clear to have the clock output set to low level in idle state. 2C P H A SPI Clock Phase Bit Set to have the data sampled when the clock returns to idle state (see CPOL). Clear to have the data sampled when the clock leaves the idle state (see CPOL). 1 - 0 SPR1:0 SPI Rate Bits 0 and 1 Refer to Table 154 for bit rate description.

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Table 156. SPSTA Register Table 157. SPDAT Register

7 SPIF

Set by hardware when an 8-bit shift is completed. Cleared by hardware when reading or writing SPDAT after reading SPSTA. Set by hardware to indicate that a collision has been detected. Cleared by hardware to indicate that no collision has been detected. The value read from this bit is indeterminate. Do not set this bit. pin is at an appropriate level. Cleared by hardware to indicate that the SS pin is at an inappropriate level. The value read from these bits is indeterminate. Do not set these bits. 7 - 0 SPD7:0 Synchronous Serial Data.

the single synchronous and the three asynchronous modes according to Table 158. Table 158. Serial I/O Port Mode Selection Generator as it allows higher and more accurate baud rates than Timer 1. Figure 114. Timer 1 Baud Rate Generator Block Diagram

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ister allows doubling of the generated baud rate. Figure 115. Internal Baud Rate Generator Block Diagram eight clock pulses while the receive data (RXD) pin transmits or receives a Byte of data. at a fixed Baud Rate (see Section "B aud Rate Selection (Mode 0)", page 171). Figure 116 shows the serial port block diagram in Mode 0. Figure 116. Serial I/O Port Block Diagram (Mode 0) Transmission (Mode 0) To start a transmission mode 0, write to SCON register clearing bits SM0, SM1. indicate the end of the transmission.

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shows the Serial Port block diagram in such asynchronous modes. Figure 121. Serial I/O Port Block Diagram (Modes 1, 2 and 3) the RB8 bit in SCON register. Figure 122. Data Frame Format (Mode 1) tively, you can use the ninth bit can be used as a command/data flag. Figure 123. Data Frame Format (Modes 2 and 3) transmitted to SBUF register starts the transmission. to-low transition on the RXD pin.

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Notes: 1. These frequencies are achieved in X1 mode, F PER = FOSC ÷ 2.

1. These frequencies are achieved in X2 mode, F PER = FOSC.

As shown in Figure 127 the selection is done using SMOD1 bit in PCON register. Figure 128 gives the baud rate calculation formula depending on the selection. Figure 127. Baud Rate Generator Selection (Mode 2) Table 159. Internal Baud Rate Generator Value

Figure 128. Baud Rate Formula (Mode 2) ware sets RB8 and RI bits in SCON register, generating an interrupt. they are waiting to respond to their own addresses. nication feature is enabled (SM2 bit in SCON register is set). is not interrupted by command frames addressed to other devices. be enabled in mode 0 (i.e, setting SM2 bit in SCON register in mode 0 has no effect). slaves at a time. The following example illustrates how a given address is formed.

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4341D–MP3–04/05 The following is an example of how to use given addresses to address different slaves: Slave A:SADDR = 1111 0001b SADEN = 1111 1010b Given = 1111 0X0Xb Slave B:SADDR = 1111 0011b SADEN = 1111 1001b Given = 1111 0XX1b Slave C:SADDR = 1111 0011b SADEN = 1111 1101b Given = 1111 00X1b The SADEN Byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bi t; for slaves B and C, bit 0 is a 1. To com- municate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000B). For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011B). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001B). Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t-care bits, e.g.: SADDR = 0101 0110b SADEN = 1111 1100b (SADDR | SADEN)=1111 111Xb The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A:SADDR = 1111 0001b SADEN = 1111 1010b Given = 1111 1X11b, Slave B:SADDR = 1111 0011b SADEN = 1111 1001b Given = 1111 1X11b, Slave C:SADDR = 1111 0010b SADEN = 1111 1101b Given = 1111 1111b, For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send the address FFh. To communicate with slaves A and B, bu t not slave C, the master must send the address FBh. Reset Address On reset, the SADDR and SADEN registers ar e initialized to 00h, i.e. the given and broadcast addresses are XXXX XXXXb (all don’t care bits). This ensures that the Serial Port is backwards compatible with the 80C51 microcontrollers that do not support auto- matic address recognition.

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4341D–MP3–04/05 Registers Table 160. SCON Register SCON (S:98h) – Serial Control Register Reset Value = 0000 0000b 76543210 FE/SM0 OVR/SM1 SM2 REN TB8 RB8 TI RI Bit Number Bit Mnemonic Description FE Framing Error Bit To select this function, set SMOD0 bit in PCON register. Set by hardware to indicate an invalid stop bit. Must be cleared by software. SM0 Serial Port Mode Bit 0 Refer to Table 158 for mode selection. 6S M 1 Serial Port Mode Bit 1 Refer to Table 158 for mode selection. 5S M 2 Serial Port Mode Bit 2 Set to enable the multiprocessor communication and automatic address recognition features. Clear to disable the multiprocessor communication and automatic address recognition features. 4R E N Receiver Enable Bit Set to enable reception. Clear to disable reception. 3T B 8 Transmit Bit 8 Modes 0 and 1: Not used. Modes 2 and 3: Software writes the ninth data bit to be transmitted to TB8. 2R B 8 Receiver Bit 8 Mode 0: Not used. Mode 1 (SM2 cleared): Set or cleared by hardware to reflect the stop bit received. Modes 2 and 3 (SM2 set): Set or cleared by hardware to reflect the ninth bit received. 1T I Transmit Interrupt Flag Set by the transmitter after the last data bit is transmitted. Must be cleared by software. 0R I Receive Interrupt Flag Set by the receiver after the stop bit of a frame has been received. Must be cleared by software.

Table 161. SBUF Register Table 162. SADDR Register Table 163. SADEN Register Read the last data received by the serial I/O Port. Write the data to be transmitted by the serial I/O Port.

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Table 164. BDRCON Register Table 165. BRL Register The value read from these bits are indeterminate. Do not set these bits. Set to enable the baud rate generator. Clear to disable the baud rate generator. Set to select the baud rate generator as transmission baud rate generator. Clear to select the Timer 1 as transmission baud rate generator. Set to select the baud rate generator as reception baud rate generator. Clear to select the Timer 1 as reception baud rate generator.

1 SPD

Set to select high speed baud rate generation. Clear to select low speed baud rate generation. Set to select the variable baud rate generator in Mode 0. Clear to select fixed baud rate in Mode 0.

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Figure 132. Complete Data Transfer on TWI Bus

• Master transmitter
• Master receiver
• Slave transmitter
• Slave receiver Data transfer in each mode of operation are shown in Figure 133 through Figure 136. These figures contain the following abbreviations: A Acknowledge bit (low level at SDA) A Not acknowledge bit (high level on SDA) Data 8-bit data Byte S START condition P STOP condition MR Master Receive MT Master Transmit SLA Slave Address GCA General Call Address (00h) R Read bit (high level at SDA) W Write bit (low level at SDA) In Figure 133 through Figure 136, circles are used to indicate when the serial interrupt flag is set. The numbers in the circles show the status code held in SSSTA. At these points, a service routine must be executed to continue or complete the serial transfer. These service routines are not critical si nce the serial transfer is suspended until the serial interrupt flag is cleared by software. When the serial interrupt routine is entered, the status code in SSSTA is used to branch to the appropriate service routine. For each status code, the required software action and details of the following serial transfer are given in Table 167 through Table 136. S Slave Address SCL SDA MSB R/W direction ACK signal Nth data Byte ACK signal P/S bit from receiver from receiver 12 89 12 89 Clock Line Held Low While Serial Interrupts Are Serviced

generator is based on timer 1 overflow output. but can be used with high speed TWI components limited to 400 kHz. troller. SSSTA, SSSTO and SSI must be cleared. serial transfer can continue. STOP condition is transmitted. Table 167. After a repeated START condition (state 10h) the controller may switch to the master receiver mode by loading SSDAT with SLA+R. Table 166. Serial Clock Rates

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(SSI) must then be cleared before the serial transfer can continue. repeated until a STOP condition is transmitted. Table 136. After a repeated START condition (state 10h) the controller may switch to the master transmitter mode by loading SSDAT with SLA+W. address (00h); otherwise, it ignores the general call address. SSCR2:0 have no effect in the slave mode. SSPE must be set to enable the controller. acknowledgment. SSSTA, SSSTO and SSI must be cleared. the controller is in the master mode (see states 68h and 78h). SSAA bit may be used to temporarily isolate the controller from the TWI bus.

receiver (see Figure 136). Data transfer is initialized as in the slave receiver mode. Table 171. The slave transmitter mode may also be entered if arbitration is lost while the controller is in the master mode (see state B0h). may be used to temporarily isolate the controller from the TWI bus. Table 172). These are discussed below. involved in a serial transfer. STOP condition is transmitted.

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Figure 133. Format and States in the Master Transmitter Mode

Figure 134. Format and States in the Master Receiver Mode

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Figure 135. Format and States in the Slave Receiver Mode

Figure 136. Format and States in the Slave Transmitter Mode

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Table 167. Status for Master Transmitter Mode Write SLA+W X0 0 X SLA+W will be transmitted. Data Byte will be transmitted. Repeated START will be transmitted. be transmitted and SSSTO flag will be reset. Data Byte will be transmitted. Repeated START will be transmitted. be transmitted and SSSTO flag will be reset. Data Byte will be transmitted. Repeated START will be transmitted. be transmitted and SSSTO flag will be reset. Data Byte will be transmitted. Repeated START will be transmitted. be transmitted and SSSTO flag will be reset.

Table 168. Status for Master Receiver Mode Write SLA+R X0 0 X SLA+R will be transmitted. Logic will switch to master transmitter mode. Data Byte will be received and ACK will be returned. Repeated START will be transmitted. be transmitted and SSSTO flag will be reset. Data Byte will be received and ACK will be returned. Repeated START will be transmitted. be transmitted and SSSTO flag will be reset.

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Table 169. Status for Slave Receiver Mode with Own Slave Address Data Byte will be received and ACK will be returned. Data Byte will be received and ACK will be returned. Data Byte will be received and ACK will be returned. recognition of own SLA or GCA. will be transmitted when the bus becomes free. transmitted when the bus becomes free. recognition of own SLA or GCA. will be transmitted when the bus becomes free. transmitted when the bus becomes free.

Table 170. Status for Slave Receiver Mode with General Call Address Data Byte will be received and ACK will be returned. Data Byte will be received and ACK will be returned. Data Byte will be received and ACK will be returned. recognition of own SLA or GCA. will be transmitted when the bus becomes free. transmitted when the bus becomes free. recognition of own SLA or GCA. will be transmitted when the bus becomes free. transmitted when the bus becomes free.

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Table 171. Status for Slave Transmitter Mode Last data Byte will be transmitted. Data Byte will be transmitted. Last data Byte will be transmitted. Data Byte will be transmitted. Last data Byte will be transmitted. Data Byte will be transmitted. recognition of own SLA or GCA. will be transmitted when the bus becomes free. transmitted when the bus becomes free. recognition of own SLA or GCA. will be transmitted when the bus becomes free. transmitted when the bus becomes free. Table 172. Status for Miscellaneous States Wait or proceed current transfer. released and SSSTO is reset.

Table 173. AUXCON Register Table 174. SSCON Register SDA is the bidirectional Two Wire data line.

196 AT8xC51SND2C

4341D–MP3–04/05 Reset Value = 0000 0000b Bit Number Bit Mnemonic Description

7 SSCR2 Synchronous Serial Control Rate Bit 2

Refer to Table 166 for rate description. 6S S P E Synchronous Serial Peripheral Enable Bit Set to enable the controller. Clear to disable the controller.

5 SSSTA

Synchronous Serial Start Flag Set to send a START condition on the bus. Clear not to send a START condition on the bus.

4 SSSTO

Synchronous Serial Stop Flag Set to send a STOP condition on the bus. Clear not to send a STOP condition on the bus.

3 SSI

Synchronous Serial Interrupt Flag Set by hardware when a serial interrupt is requested. Must be cleared by software to acknowledge interrupt. 2S S A A Synchronous Serial Assert Acknowledge Flag Set to enable slave modes. Slave modes are entered when SLA or GCA (if SSGC set) is recognized. Clear to disable slave modes. Master Receiver Mode in progress Clear to force a not acknowledge (high level on SDA). Set to force an acknowledge (low level on SDA). Master Transmitter Mode in progress This bit has no specific effect when in master transmitter mode. Slave Receiver Mode in progress Clear to force a not acknowledge (high level on SDA). Set to force an acknowledge (low level on SDA). Slave Transmitter Mode in progress Clear to isolate slave from the bus after last data Byte transmission. Set to enable slave mode.

1 SSCR1 Synchronous Serial Control Rate Bit 1

Refer to Table 166 for rate description.

0 SSCR0 Synchronous Serial Control Rate Bit 0

Refer to Table 166 for rate description.

Table 175. SSSTA Register Table 176. SSDAT Register Table 177. SSADR Register Refer to Table 167 to Table 136 for status description.

0 SSD0 Synchronous Serial Address bit 0 (R/W) or Synchronous Serial Data Bit 0

Set to enable the general call address recognition. Clear to disable the general call address recognition.

198 AT8xC51SND2C

level. This input allows exit from idle and power down modes. status register (see Table 180). ter. Level detection is then reported in interrupt flag KINF0 in KBSTA register. software using KINM0 bits in KBCON register and is cleared by reading KBSTA register. Figure 137. Keyboard Interface Block Diagram Figure 138. Keyboard Input Circuitry software must enter power down again.

Table 179. KBCON Register Table 180. KBSTA Register 0K I N 0 Keyboard Input Interrupt. Set to enable a high level detection on the respective KIN0 input. Clear to enable a low level detection on the respective KIN0 input.

0 KINM0

Set to prevent the respective KINF3:0 flag from generating a keyboard interrupt. Clear to allow the respective KINF3:0 flag to generate a keyboard interrupt.

7 KPDE

Set to enable exit of power down mode by the keyboard interrupt. Clear to disable exit of power down mode by the keyboard interrupt.

200 AT8xC51SND2C

4341D–MP3–04/05 Reset Value = 0000 0000b 6 - 1 - Reserved The value read from these bits is always 0. Do not set these bits. 0K I N F 0 Keyboard Input Interrupt Flag Set by hardware when the KIN0 input detects a programmed level. Cleared when reading KBSTA. Bit Number Bit Mnemonic Description

4341D–MP3–04/05

Electrical Characteristics

*NOTICE: Stressing the device beyond the “Absolute Maxi- mum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “operating conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. Table 181. Digital DC Characteristics

202 AT8xC51SND2C

there is no guarantee on these values.

1. Flash retention is guaranteed with the same formula for V DD min down to 0V.
2. See Table 182 for typical consumption in player mode.

Table 182. Typical Reference Design AT89C51SND2C Power Consumption

12 MHz

16 MHz

20 MHz

This consumption does not include AUDVBAT current. This consumption does not include AUDVBAT current.

204 AT8xC51SND2C

4341D–MP3–04/05 Oscillator & Crystal Schematic Figure 142. Crystal Connection Note: For operation with most standard crys tals, no external components are needed on X1 and X2. It may be necessary to add external capacitors on X1 and X2 to ground in spe- cial cases (max 10 pF). X1 and X2 may not be used to drive other circuits. Parameters Table 183. Oscillator & Crystal Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85°C Phase Lock Loop Schematic Figure 143. PLL Filter Connection Parameters Table 184. PLL Filter Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85°C VSS Q Symbol Parameter Min Typ Max Unit CX1 Internal Capacitance (X1 - VSS) 10 pF CX2 Internal Capacitance (X2 - VSS) 10 pF CL Equivalent Load Capacitance (X1 - X2) 5 pF DL Drive Level 50 µW F Crystal Frequency 20 MHz RS Crystal Series Resistance 40 Ω CS Crystal Shunt Capacitance 6 pF VSS FILT R VSS Symbol Parameter Min Typ Max Unit R Filter Resistor 100 Ω C1 Filter Capacitance 1 10 nF C2 Filter Capacitance 2 2.2 nF

PA AUDVBAT = 3.6V, TA = 25°C unless otherwise noted. Figure 145. PA Specification UP Output setup time Off to on mode. Voltage already settled.

206 AT8xC51SND2C

Figure 146. Maximum Dissipated Power Versus Power Supply Figure 147. Dissipated Power vs Output Power, AUDVBAT = 3.2V

8 Ohms load

6.5 Ohms load

Full Scale levels scale proportionally with the analog supply voltage. Figure 148. Audio DAC Specification

208 AT8xC51SND2C

4341D–MP3–04/05 PSRR - 1kHz - 20kHz dB dB Maximum output slope at power up (100 to 220F coupling capacitor) 3V / s ANALOG PERFORMANCE – Line-in/Microphone Input to Line-out/Headphone Output Input level for full scale output - 0dBFS Level @ AUDVDD, HSVDD = 2.8 V and 0 dB gain @ AUDVDD, HSVDD = 2.8 V and 20 dB gain 1.65 583 0.165 58.3 Vpp mVrms Vpp mVrms Input common mode voltage 0.5xAUDVD D V Input impedance 7 10 kOhm Signal to Noise Ratio -1 dBFS @ 1kHz input and 0 dB gain -21 dBFS @ 1kHz input and 20 dB gain 81 85 dB Dynamic Range (extrapolated to full scale level) -60 dBFS @ 1kHz input and 0 dB gain -60 dBFS @ 1kHz input and 20 dB gain 82 86 dB Total Harmonic Distortion –1dBFS @ 1kHz input and 0 dB gain –1dBFS @ 1kHz input and 20 dB gain -80 -75 -76 -68 dB Interchannel mismatch 0.1 1 dB Left-channel to right-channel crosstalk (@ 1kHz) -90 -80 dB ANALOG PERFORMANCE – Differential mono input amplifier Differential input level for full scale output - 0dBFS Level @ AUDVDD, HSVDD = 2.8 V and 0 dB gain 1.65 583 Vppdif mVrms Input common mode voltage 0.5xAUDVD D V Input impedance 7 10 kOhm Signal to Noise Ratio (-1 dBFS @ 1kHz input and 0 dB gain) 76 80 dB Total Harmonic Distortion (–1dBFS @ 1kHz input and 0 dB gain) -85 -81 dB ANALOG PERFORMANCE – PA Driver Differential output level for full scale input (for AUDVDD, HSVDD = 3 V) 3.3 Vppdif Output common mode voltage 0.5x HSVDD V Output load 10 30 kOhm pF OVERALL MIN TYP MAX UNITS

4341D–MP3–04/05 Signal to Noise Ratio (–1dBFS @ 1kHz input and 0dB Gain) 76 80 dB Total Harmonic Distortion (–1dBFS @ 1kHz input and 0dB Gain) -75 -71 dB MASTER CLOCK Master clock Maximum Long Term Jitter 1.5 ns pp DIGITAL FILTER PERFORMANCE Frequency response (10 Hz to 20 kHz) +/- 0.1 dB Deviation from linear phase (10 Hz to 20 kHz) +/- 0.1 deg Passband 0.1 dB corner 0.4535 Fs Stopband 0.5465 Fs Stopband Attenuation 65 dB DE-EMPHASIS FILTER PERFORMANCE (for 44.1kHz Fs) Frequency Gain Margin Pass band Transition band Stop Band 0Hz to 3180Hz 3180Hz to 10600Hz 10600Hz to 20kHz -1dB Logarithm decay -10.45dB 1dB 1dB 1dB Power Performance Current consumption from Audio Analog supply AVDD, HSVDD in power on 9.5 mA Current consumption from Audio Analog supply AVDD, HSVDD in power down 10 µA Power on Settling Time - From full Power Down to Full Power Up (AUDVREF and AUDVCM decoupling capacitors charge) - Linein amplifier (Line-in coupling capacitors charge) - Driver amplifier (out driver DC blocking capacitors charge) 500 500 ms ms ms OVERALL MIN TYP MAX UNITS

210 AT8xC51SND2C

Figure 149. Channel Filter Figure 150. De-emphasis Filter

4341D–MP3–04/05 Audio DAC and PA Connection Figure 151. DAC and PA Connection Audio Dac and PA Connection AUDVREF AUXP PAINN VSS LPHN LINEL LINER HSL HSR ESDVSS INGND CBP HPN PAINP HPP AUDVBAT MONON MONOP AUXN VDD AUDVDD AUDVCM mono input (-) 3V from LDO 3V from LDO 3.2V to 5.5V Battery Mono Differential Input

8 Ohm

32 Ohm

R L mono input (+) HSVDD C17 C18 C19 VSS HSVSS AUDVSS ESDVSS AUDVSS AUDVSS AUDVSS AUDVSS AUDVSS AUDVSS VSS AUDVSS VSS

212 AT8xC51SND2C

Table 186. DAC and PA Characteristics

Timings Test conditions: capacitive load on all pins= 50 pF. Table 189. External Program Bus Cycle - Read AC Timings

214 AT8xC51SND2C

Timings Test conditions: capacitive load on all pins= 50 pF. Table 191. External Data 8-bit Bus Cycle - Read AC Timings

4341D–MP3–04/05 TRLRH RD Pulse Width 6·T CLCL-25 3·T CLCL-25 ns TRHLH RD high to ALE High T CLCL-20 T CLCL+20 0.5·T CLCL-20 0.5·T CLCL+20 ns TAVDV Address Valid to Valid Data In 9·T CLCL-65 4.5·T CLCL-65 ns TAVRL Address Valid to RD Low 4·T CLCL-30 2·T CLCL-30 ns TRLDV RD Low to Valid Data 5·T CLCL-30 2.5·T CLCL-30 ns TRLAZ RD Low to Address Float 0 0 ns TRHDX Data Hold After RD High 0 0 ns TRHDZ Instruction Float After RD High 2·T CLCL-25 T CLCL-25 ns Symbol Parameter Variable Clock Standard Mode Variable Clock X2 Mode UnitMin Max Min Max

216 AT8xC51SND2C

Table 192. External Data 8-bit Bus Cycle - Write AC Timings

Figure 155. External Data 8-bit Bus Cycle - Write Waveforms

218 AT8xC51SND2C

Timings Test conditions: capacitive load on all pins= 50 pF. Table 194. External IDE 16-bit Bus Cycle - Data Read AC Timings Table 195. External IDE 16-bit Bus Cycle - Data Write AC Timings

Note: 1. D15:8 is written in DAT16H SFR. Figure 157. External IDE 16-bit Bus Cycle - Data Write Waveforms Note: 1. D15:8 is the content of DAT16H SFR.

220 AT8xC51SND2C

Timings Test conditions: capacitive load on all pins= 50 pF. Table 197. SPI Interface Master AC Timing Note: 1. Value of this parameter depends on software.

Note: 1. Not Defined but generally the MSB of the character which has just been received. Figure 159. SPI Slave Waveforms (SSCPHA= 1) Note: 1. Not Defined but generally the LSB of the character which has just been received.

222 AT8xC51SND2C

Figure 160. SPI Master Waveforms (SSCPHA= 0) Note: 1. SS handled by software using general purpose port pin. Figure 161. SPI Master Waveforms (SSCPHA= 1) Note: 1. SS handled by software using general purpose port pin.

4341D–MP3–04/05 Two-wire Interface Timings Table 198. TWI Interface AC Timing VDD = 2.7 to 3.3 V, TA = -40 to +85°C Notes: 1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. Determined by the external bus-line ca pacitance and the external bus-line pull-up resistor, this must be < 1 µs. 3. Spikes on the SDA and SCL lines with a duration of less than 3·T CLCL will be filtered out. Maximum capacitance on bus-lines SDA and SCL= 400 pF. 4. T CLCL= TOSC= one oscillator clock period. Waveforms Figure 162. Two Wire Waveforms Symbol Parameter INPUT Min Max OUTPUT Min Max THD; STA Start condition hold time 14·T CLCL(4) 4.0 µs(1) TLOW SCL low time 16·T CLCL(4) 4.7 µs(1) THIGH SCL high time 14·T CLCL(4) 4.0 µs(1) TRC SCL rise time 1 µs- (2) TFC SCL fall time 0.3 µs0 . 3 µs(3) TSU; DAT1 Data set-up time 250 ns 20·T CLCL(4)- TRD TSU; DAT2 SDA set-up time (before repeated START condition) 250 ns 1 µs(1) TSU; DAT3 SDA set-up time (before STOP condition) 250 ns 8·T CLCL(4) THD; DAT Data hold time 0 ns 8·T CLCL(4) - TFC TSU; STA Repeated START set-up time 14·T CLCL(4) 4.7 µs(1) TSU; STO STOP condition set-up time 14·T CLCL(4) 4.0 µs(1) TBUF Bus free time 14·T CLCL(4) 4.7 µs(1) TRD SDA rise time 1 µs - (2) TFD SDA fall time 0.3 µs0 . 3 µs(3) Tsu;DAT1 Tsu;STA Tsu;DAT2Thd;STA ThighTlow SDA (INPUT/OUTPUT) 0.3 VDD

0.7 VDD

TbufTsu;STO

0.3 VDD

(INPUT/OUTPUT) Thd;DAT Tsu;DAT3 START or Repeated START condition START condition STOP condition Repeated START condition

224 AT8xC51SND2C

4341D–MP3–04/05 MMC Interface Definition of symbols Table 199. MMC Interface Timing Symbol Definitions Timings Table 200. MMC Interface AC timings VDD = 2.7 to 3.3 V, TA = -40 to +85°C, CL ≤ 100pF (10 cards) Waveforms Figure 163. MMC Input-Output Waveforms Signals Conditions CC l o c k HH i g h D Data In L Low O Data Out V Valid X No Longer Valid Symbol Parameter Min Max Unit TCHCH Clock Period 50 ns TCHCX Clock High Time 10 ns TCLCX Clock Low Time 10 ns TCLCH Clock Rise Time 10 ns TCHCL Clock Fall Time 10 ns TDVCH Input Data Valid to Clock High 3 ns TCHDX Input Data Hold after Clock High 3 ns TCHOX Output Data Hold after Clock High 5 ns TOVCH Output Data Valid to Clock High 5 ns TIVCH MCLK MDAT Input TCHCH TCLCXTCHCX TCHCL TCLCH MCMD Input TCHIX TOVCH MDAT Output MCMD Output TCHOX

4341D–MP3–04/05 Audio Interface Definition of symbols Table 201. Audio Interface Timing Symbol Definitions Timings Table 202. Audio Interface AC timings VDD = 2.7 to 3.3 V, TA = -40 to +85°C, CL≤ 30pF Note: 1. 32-bit format with Fs= 48 KHz. Waveforms Figure 164. Audio Interface Waveforms Signals Conditions CC l o c k HH i g h O Data Out L Low S Data Select V Valid X No Longer Valid Symbol Parameter Min Max Unit TCHCH Clock Period 325.5 (1) ns TCHCX Clock High Time 30 ns TCLCX Clock Low Time 30 ns TCLCH Clock Rise Time 10 ns TCHCL Clock Fall Time 10 ns TCLSV Clock Low to Select Valid 10 ns TCLOV Clock Low to Data Valid 10 ns DCLK TCHCH TCLCXTCHCX TCLCHTCHCL DSEL DDAT Right Left TCLSV TCLOV

226 AT8xC51SND2C

Figure 166. FLASH Memory - Internal Busy Waveforms

Figure 168. AC Testing Input/Output Waveforms

1. Timing measurements are made on all outputs at V IH min for a logic 1 and VIL max for

Figure 169. Float Waveforms occurs with IOL/IOH= ±20 mA.

228 AT8xC51SND2C

4341D–MP3–04/05

Ordering Information

Frequency Package Packing Product Marking RoHS Compliant AT89C51SND2C-7FTIL 64K Flash 3V Industrial 40 MHz BGA100 Tray 89C51SND2C-IL No AT89SND2C-7FTUL 64K Flash 3V Industrial & ROHS 40 MHz BGA100 Tray 89C51SND2C-JL Yes AT83SND2Cxxx-7FTUL 64K ROM 3V Industrial & ROHS 40 MHz BGA100 Tray 83C51SND2C-JL Yes

4341D–MP3–04/05

Package Information

230 AT8xC51SND2C

4341D–MP3–04/05 Datasheet Change Log Changes from 4341A - 10/04 to 4341B - 01/05 1. Update Power Amplif ier DC characteristics, Section “Electrical Characteristics”, page 201. 2. Fix minor bugs. 3. Update power consumption measures, Table 182 on page 202. Changes from 4341B - 01/05 to 4341C - 03/05 1. Change to hardware security system description. Section “Hardware Security System”, page 19. Changes from 4341C - 03/05 to 4341D - 04/05 1. Update to DAC gain information, Figure 54 on page 81. 2. Correction to BGA package pinout, Figure 2 on page 4. 3. Updated Ordering Information, Green product version changed to ROHS. (Green version not yet available)

232 AT8xC51SND2C

4341D–MP3–04/05

4341D–MP3–04/05

234 AT8xC51SND2C

4341D–MP3–04/05

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