8288

SAB8288A SIEMENS | Alldatasheet

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‘ey My; for SAB 8086 Family Processors © Fully compatible with SAB 8288 © Provides Wide Flexibility 40% Less Power Supply Current in System Configurations than Standard SAB 8288 @ 3-State Command Output Drivers © Bipolar Drive Capability © Configurable for Use with an I/O Bus © Provides Advanced Commands © Facilitates Interface to One or Two Multi-Master Busses Pin Configuration Pin Names ALE Adress Latch Enable DEN Data Enable DT/R Data Transmit/Receive los} 20 Wve AEN ‘Address Enable GLK 42 191138, “ “ CEN Command Enable a 18 LS: t 3 2 108 Input/Output Bus Mode OUR} 4 LIMCE/POEN Sowe Advanced 1/0 Write aes sae [L-J0eN Tow 1/0 Write ANC|6 = gagga_—s 15 EJ CEN TORT V/O Read RoC (] 7 14{ JINTA AMWC ‘Advanced Memory Write GND [410 11 Jiowe INTA Interrupt Acknowledge MCE/PDEN | Master Cascade/Peripheral Data Veo Power Supply (+5V) GND Ground (0V) SAB 8288A Bus Controller is a 20-pin bipolar A strapping option on the bus controller configures component for use with medium-to-large it for use with a multi-master system bus and SAB 80186, SAB 80188, SAB 8086 and SAB 8088 separate I/O bus. processing systems. The bus controller provides _This device is fabricated in a fast bipolar ASBC command and control timing generation as well as (Advanced Standard Buried Collector) process of bipolar bus drive capability while optimizing system Siemens. performance.

761 January 1985

a Block Diagram g,{ So MAROC S22 5, |_| Status a Twit 2s)” a Decoder |_| 4 ° yy AMWO | & Command | | a Signal | —~TRE oP Generator 2 a —-owo | & S a nowe | ° —= INTA . 23% CLK ——= DT/R BES TEN |_| Control € g B Zs | AEN i onto! }-——= DEN 25 ge eee ee See O~ | CEN | Generator MCE/PDEN 3 ‘8 °

108 ALE 38s

+5V GND Pin Definitions and Functions Symbol umber | Input | Eunetion 10B 1 INPUT/OUTPUT BUS MODE - When the IOB is strapped HIGH the SAB 8288A functions in the |/O Bus mode. When it is strapped LOW, the SAB 8288A functions in the System Bus mode. (See sections on I/O Bus and Systems Bus modes). CLK CLOCK - This is a clock signal from the SAB 8284A or SAB 8284B clock generator and serves to establish when command and control signals are generated. So, Si, Sz 3, 18, STATUS INPUT PINS — These pins are the status input pins 19 from the SAB 80186, SAB 80188, SAB 8086 or SAB 8088 processors. The SAB 8288A decodes these inputs to generate command and control signals at the appropriate time. When these pins are not in use (passive) they are all HIGH. (See chart under Functional Description). 762

Input (1) Symbol Number Output (O) Function OTR 4 fe} DATA TRANSMIT/RECEIVE — This signal establishes the | | | direction of data flow through the transceivers. A HIGH on this line indicates Transmit (write to 1/0 or memory) gene a LOW indicates Receive (Read). ALE 15 fe) | ADDRESS LATCH ENABLE - This signal serves to strobe an address into the address latches. This signal is active HIGH and latching occurs on the falling (HIGH to LOW) | transition. ALE is intended for use with transparent Dtype latches. ee a ee AEN | 6 \\b ADDRESS ENABLE - AEN enables command outputs of . the SAB 8288A Bus Controller at least 105 ns after it | becomes active (LOW). AEN going inactive immediately | | | 3-states the command output drivers. AEN does not affect ‘ the 1/0 command lines if the SAB 82884 is in the I/O Bus mode (IOB tied HIGH) MRODC ‘7 10 | MEMORY READ COMMAND - This command line | instructs the memory to drive its data onto the data bus. [ts signal is active LOW AMWC 8 rue) . ADVANCED MEMORY WRITE COMMAND - The AMWC issues a Memory write command earlier in the machine cycle to give memory devices an early indication of a write ‘instruction. Its timing is the same as a read command signal. AMWC is active LOW MWTC 9 0 MEMORY WRITE COMMAND - This command line instructs the memory to record the data present on the data bus. This signal is active LOW. tOwc W fe) | /O WRITE COMMAND - This command line instructs an | | 1/0 device to read the data on the data bus. This signal is active LOW. AIOWC 12 fe) ADVANCED I/O WRITE COMMAND - The AIOWC issues | an1/O Write Command earlier in the machine cycle to give 1/O devices an early indication of a write instruction. Its timing 1s the same as a read command signal | AIOWC is active LOW (ORC 13 fe) 1/0 READ COMMAND - This command line instructs an 1/0 device to drive its data onto the data bus. This signal is active LOW. INTA 14 Oo INTERRUPT ACKNOWLEDGE - Thiscommand line tells an interrupting device that its interrupt has been acknowledged and that it should drive vectoring information anto the data bus. This signal is active LOW. CEN 15 | COMMAND ENABLE - When this signa! is LOW all SAB8288A command outputs and the DEN and POEN control outputs are forced to their inactive state. When this signal is HIGH, these same outputs are enabled DEN 16 ie) DATA ENABLE - This signal serves to enable data transceivers onto either the local or system data bus This signal is active HIGH. 763 3

Pin Definitions and Functions (continued) Symbol Number | Gout), | Function MCE/PDEN 7 This is a dual function pin MCE {IOB is tied LOW} - Master Cascade Enable occurs during an interrupt sequence and serves to read a Cascade. Address from a master PIC (Priority Interrupt Controller) onto the data bus. The MCE signal is active HIGH. | PDEN (108 is tied HIGH) — Peripheral Data Enable enables | the data bus transceiver for the I/O bus during 1/O | instructions. It performs the same function for the 1/O bus | that DEN performs for the system bus. PDEN is active LOW va 20 [=| Power Suppiv (60) GND | 10 - Ground (OV) Functional Description The command logic decodes the three SAB 80186, SAB 80188, SAB 8086 or SAB 8088 CPU status lines (55, $1, S)} to determine what commandis to be issued. This chart shows the meaning of each status “word” $2 si 56 | Processor State SAB 82884 Command () 0 0 | Interrupt Acknowledge INTA 0 0 1 | Read I/O Port TORC 0 1 0 | Write /0 Port TOW, AIOWC 0) 1 1 | Halt None 1 0 0 | Code Access MRDC

1 C) 1 | Read Memory MRDC

1 1 0 | Write Memory MWTC. AMWC 1 1 1 | Passive None The command is issued in one of two ways. when the CPU wants to gain access to the I/O bus dependent on the mode of the SAB 8288A Normal memory access requires a “Bus Ready” Bus Controller. signal (AEN LOW) before it will proceed. It is advantageous to use the 1OB mode if I/O or 1/0 Bus Mode — The SAB 8288A is in the I/O Bus peripherals dedicated to one processor exist ina mode if the |OB pin is strapped HIGH. In the /O Bus MU!ti-processor system mode all I/O command lines (IORC, IOWC, AIOWC, System Bus Mode - The SAB 8288A is in the System INTA) are always enabled (i.e., not dependent on Bus mode if the IOB pin is strapped LOW. In this AEN). When an I/O command is initiated by the mode no command is issued until 115 ns after the processor, the SAB 8288A immediately activates AEN Line is activated (LOW). This mode assumes the command lines using PDEN and DT/Rto control __ bus arbitration logic will inform the bus controller the I/O bus transceiver. The I/O command lines (on the AEN line) when the bus is free for use. Both should not be used to control the system bus in this | memory and I/O commands wait for bus arbitration: configuration because no arbitration is present This mode is used when only one bus exists: This mode allows one SAB 8288A Bus Controller to Here, both I/O and memory are shared by more handle two external busses. No waiting is involved than one processor. 4 764

Command Outputs If the system contains only one PIC, the MCE signal is not used. In this case the second Interrupt The advanced write commands are made available Acknowledge signal gates the interrupt vector to initiate write procedures early in the machine onto the processor bus cycle. This signal can be used to prevent the processor from entering an unnecessary wait state The command output are: MRDC — Memory Read Command Address Latch Enable and Halt MWTC - Memory Write Command Address Latch Enable (ALE) occurs during each [ORC - 1/0 Read Command machine cycle and serves to strobe the current ee v AQeanecd Memon Write Command address into the address latches. ALE also serves to aia strobe the status (So, S;, S,) into a latch for halt state AIOWC - Advanced 1/0 Write Command decodin INTA — Interrupt Acknowledge INTA {Interrupt Acknowledge) acts as an I/O read during an interrupt cycle. Its purpose is ta inform an interrupting device that its interrupt is being Command Enable acknowledged and that it should place vectoring information onto the data bus. The Command Enable (CEN) input acts as a command qualifier for the SAB 82884. If the CEN pin is high the SAB 8288A functions normally. If the CEN pinis pulled LOW, all command lines are held in their Control Outputs inactive state (not 3-state}. This feature can be used to implement memory partitioning and to eliminate The control outputs of the SAB 8288A are Data address conflicts between system bus devices and Enable (DEN), Data Transmit/Receive (DT/R) and resident bus devices. Master Cascade Enable/Peripheral Data Enable (MCE/PDEN). The DEN signal determines when the external bus should be enable onto the local bus and the DT/R determines the direction of data transfer. These two signals usually go to the chip select and direction pins of a transceiver The MCE/PDEN pin changes function with the two modes of the SAB 8288A. When the SAB 8288A is in the 1OB mode (IOB HIGH) the PDEN signal serves as a dedicated data enable signal for the |/O or Peripheral System bus Interrupt Acknowledge and MCE i The MCE signal is used during an interrupt acknowledge cycle if the SAB 8288A is in the System Bus mode (IOB LOW). During any interrupt sequence there are two interrupt acknowledge cycle no data or address transfers take place Logic should be provided to mask off MCE during this cycle. Just before the second cycle begins the MCE signal gates a master Priority Interrupt Controller's (PIC) cascade address onto the processor's local bus where ALE (Address Latch Enable} strobes it into the address latches. On the leading edge of the second interrupt cycle the addressed slave PIC gates an interrupt vector onto the system data bus where it is read by the processor 765

Absolute Maximum Ratings " Temperature Under Bias Oto +70C Storage Temperature ~65 to +150 C All Output and Supply Voltages -0.5to +7V All input Voltages 1.0to +5.5V Power Dissipation 1w : D.C. Characteristics Tx - 01070 C; Voc ~ #5V + 10% OT Limit Values Symbol Parameter Units | Test Conditions Max Ve Input Clamp Voltage i | -1 v Ic -5mA lee Power Supply Current 140 A All outputs open Q ae mi hk Forward Input Current - : 07 Ve = 0.45V tr | Reserve Input Current [so WA Va = Vee Vor | Output Low Voltage | Command Outputs 05 Jou = 32 MA Control Outputs | 0.5 Jou = 16 mA Vou Output High Voltage ‘Command Outputs 2.4 Ton = -5 mA Control Outputs 2.4 Jon = ~1MA ve Input Low Votage — fos | a Input High Voltage 20 |_| fo Output Off Current [— [00 [wa [Vow = oto 525V A.C. Characteristics Tx = 01070 C; Vec = +5V + 10% Timing Requirements a [Limit Values | Symbol Parameter [Min. [Max _| Units | Test Conditions terce CLK Cycle Period tevcn CLK Low Time tence CLK High Time tensv Status Active Hold Time [ro | teusn Status Inactive Hold Time Jo | tun Input, Rise Time From 0.8V to 2.0V fie Input, Fall Time From 2.0V to 0.8V 1} Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 766

symbot | Paramet [_timvaiues Tris | test condi y' arameter [Min [Max | nits | Test Conditions tev Control Active Delay Is | teu termcn | ALE MCE Active Delay (from CLK] 20 tsvuns tsvmcn_ | ALE MCE Active Delay (from Status) MRDC tom AIE Inactive Delay a ne teume Command Active Delay 1 MWTC Io. = 32 MA —— 35 ns lowe fon= -5 mA term Command Inactive Delay iNTA . = 300 pF 7 ae AMWC fewor Direction Control Active Delay (50 | nOWe tcHoTH Direction Control Inactive Delay Ioan tm taeven Command Enable Time Other (. na taencz Command Disable Time C. = 80 pF taevev Enable Delay Time 200 | taevnv AEN to DEN 20 | toevny CEN to DEN, PDEN toron Output, Rise Time 20 From 0.8V to 2.0V tonor Output, Fall Time 12 From 2.0V to 0.8V A.C. Testing Input, Output Waveform Input/Output i 1.5-=—— Test Points-—1.5 0.65 4.3V and 0.25V timing measurements are made at 1.5V for both a logic "1" and “0” 767

Test Load Circuits - 3-State Command Output Test Load 15V 15V | [#00 []s82 Outputo + Outpulo | + = 300 pF = 5000F 3-state to High 3-state to Low Test Load Circuits — 3-State Command Output Test Load 214v 2.28V | - ae (] 52.72 [In40 == 300pF = 80 pF - + Command Output Control Output Test Load Test Load 768

State — 4 h h Ts Ts foe “cucH CuK . os = | L ho Write natesiboay) [| Xia X Bates || {Cu “ot anc CTA Nr AMWC, AIOWC: MWTC,IOWC 2} few | (Read) q ot =i) apen (Read) POEN (ina) DEN (Write) CEE a} PDEN (Write) ‘cuore jp (Read) “~~~ 7 OUR Uinta) ol ‘cHoTH MCE ave FcuMcH, fovnx fsyMicH 1) Address/Data Bus is shown only for reference whichever occurs last. purposes 3) Alltiming measurements are made at 1.5V unless 2) Leading edge of ALE and MCE is determined by specified otherwise. the falling edge of CLK or status going active, 769

a DEN, PDEN Qualification Timing CEN EN ChevNv DEN fcevnv PDEN Address Enable (AEN) Timing (3-State Enable/Disable) ety AEN 15V 15V eeLcH fxeH0z > iQ Vou S Output You Command ‘CeLRH CEN fceury CEN must be low or valid prior to T2 to prevent the command from being generated. 770

Ordering information

SAB 8288A-P Bus Controller (plastic) Q67020-Y 155 771