80C32-20

P80C32 TEMIC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 20

Technical content

Features

8 Kbytes of ROM (80C52)

Three 16 bit timer/counters

64 K program memory space

64 K data memory space

0.8µ CMOS process Boolean processor 6 interrupt sources Programmable serial port Temperature range : commercial, industrial, automotive, military Optional Secret ROM : Encryption Secret TAG : Identification number CMOS 0 to 44 MHz Single Chip 8–bit Microntroller

2 MA TRA MHS

Figure 1. Block Diagram

Figure 2. Pin Configuration Diagrams are for reference only. Package sizes are not to scale.

Rev. G (14 Jan. 97)

4 MA TRA MHS

Circuit ground potential. VCC Supply voltage during normal, Idle, and Power Down operation. Port 0 Port 0 is an 8 bit open drain bi-directional I/O port. Port 0 pins that have 1’s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory. In this application it uses strong internal pullups when emitting 1’s. Port 0 also outputs the code bytes during program verification in the 80C52. External pullups are required during program verification. Port 0 can sink eight LS TTL inputs. Port 1 Port 1 is an 8 bit bi-directional I/O port with internal pullups. Port 1 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL, on the data sheet) because of the internal pullups. Port 1 also receives the low-order address byte during program verification. In the 80C52, Port 1 can sink/ source three LS TTL inputs. It can drive CMOS inputs without external pullups. 2 inputs of PORT 1 are also used for timer/counter 2 : P1.0 [T2] : External clock input for timer/counter 2. P1.1 [T2EX] : A trigger input for timer/counter 2, to be reloaded or captured causing the timer/counter 2 interrupt. Port 2 Port 2 is an 8 bit bi-directional I/O port with internal pullups. Port 2 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (ILL, on the data sheet) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16 bit addresses (MOVX @DPTR). In this application, it uses strong internal pullups when emitting 1’s. During accesses to external Data Memory that use 8 bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 Special Function Register. It also receives the high-order address bits and control signals during program verification in the 80C52. Port 2 can sink/source three LS TTL inputs. It can drive CMOS inputs without external pullups. Port 3 Port 3 is an 8 bit bi-directional I/O port with internal pullups. Port 3 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (ILL, on the data sheet) because of the pullups. It also serves the functions of various special features of the TEMIC 51 Family, as listed below. Port Pin Alternate Function P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 RXD (serial input port) TXD (serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) TD (Timer 0 external input) T1 (Timer 1 external input) WR (external Data Memory write strobe) RD (external Data Memory read strobe) Port 3 can sink/source three LS TTL inputs. It can drive CMOS inputs without external pullups. RST A high level on this for two machine cycles while the oscillator is running resets the device. An internal pull-down resistor permits Power-On reset using only a capacitor connected to V CC . As soon as the Reset is applied (Vin), PORT 1, 2 and 3 are tied to one. This operation is achieved asynchronously even if the oscillator does not start-up. ALE Address Latch Enable output for latching the low byte of the address during accesses to external memory. ALE is activated as though for this purpose at a constant rate of 1/6 the oscillator frequency except during an external data memory access at which time one ALE pulse is skipped. ALE can sink/source 8 LS TTL inputs. It can drive CMOS inputs without an external pullup.

6 MA TRA MHS

There are three ways to terminate the Idle mode. instruction that wrote 1 to PCON.0. has restarted and stabilized. strong pullup, T1, shown in Figure 4. Table 1. Status of the external pins during idle and power down modes. Figure 4.I/O Buffers in the 80C52 (Ports 1, 2, 3).

8 MA TRA MHS

The capture mode is illustrated in Figure 7. Figure 7. Timer 2 in Capture Mode. the 16 bit reload and set EXF2. The auto-reload mode is illustrated in Figure 8. Figure 8. Timer in Auto-Reload Mode. The baud rate generator mode is selected by : RCLK = 1 and/or TCLK = 1. will not be set when either RCLK = 1 OR TCLK = 1. negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. TR2 T2CON.2 Start/stop control for Timer 2. A logic 1 starts the timer. 1 = External event counter (falling edge triggered). bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

Rev. G (14 Jan. 97) 9MA TRA MHS 80C52 with Secret ROM TEMIC offers 80C52 with the encrypted secret ROM option to secure the ROM code contained in the 80C52 microcontrollers. The clear reading of the program contained in the ROM is made impossible due to an encryption through several random keys implemented during the manufacturing process. The keys used to do such encryption are selected randomwise and are definitely different from one microcontroller to another. This encryption is activated during the following phases : – Everytime a byte is addressed during a verify of the ROM content, a byte of the encryption array is selected. – MOVC instructions executed from external program memory are disabled when fetching code bytes from internal memory. – EA is sampled and latched on reset, thus all state modification are disabled. For further information please refer to the application note (ANM053) available upon request. 80C52 with Secret TAG TEMIC offers special 64-bit identifier called “SECRET TAG” on the microcontroller chip. The Secret Tag option is available on both ROMless and masked microcontrollers. The Secret Tag feature allows serialization of each microcontroller for identification of a specific equipment. A unique number per device is implemented in the chip during manufacturing process. The serial number is a 64-bit binary value which is contained and addressable in the Special Function Registers (SFR) area. This Secret Tag option can be read-out by a software routine and thus enables the user to do an individual identity check per device. This routine is implemented inside the microcontroller ROM memory in case of masked version which can be kept secret (and then the value of the Secret Tag also) by using a ROM Encryption. For further information, please refer to the application note (ANM031) available upon request.

Rev. G (14 Jan. 97)

10 MA TRA MHS

Electrical Characteristics

Absolute Maximum Ratings* Ambiant Temperature Under Bias : * This value is based on the maximum allowable die temperature and the thermal resistance of the package * Notice Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. DC Parameters TA = 0°C to 70°C ; VSS = 0 V ; VCC = 5 V ± 10 % ; F = 0 to 44 MHz TA = –40°C + 85°C ; VSS = 0 V ; VCC = 5 V ± 10 % ; F = 0 to 36 MHz SYMBOL PARAMETER MIN MAX UNIT TEST CONDITIONS VIL Input Low V oltage – 0.5 0.2 Vcc – 0.1 V VIH Input High V oltage (Except XTAL and RST) 0.2 Vcc + 1.4 Vcc + 0.5 V VIH1 Input High V oltage (for XTAL and RST) 0.7 Vcc Vcc + 0.5 V VOL Output Low V oltage (Port 1, 2 and 3) 0.3 0.45 1.0 V V V IOL = 100 µA IOL = 1.6 mA (note 2) IOL = 3.5 mA VOL1 Output Low V oltage (Port 0, ALE, PSEN) 0.3 0.45 1.0 V V V IOL = 200 µA IOL = 3.2 mA (note 2) IOL = 7.0 mA VOH Output High V oltage Port 1, 2, 3 Vcc – 0.3 V IOH = – 10 µA Vcc – 0.7 V IOH = – 30 µA Vcc – 1.5 V IOH = – 60 µA VCC = 5 V ± 10 % VOH1 Output High V oltage (Port 0, ALE, PSEN) Vcc – 0.3 V IOH = – 200 µA Vcc – 0.7 V IOH = – 3.2 mA Vcc – 1.5 V IOH = – 7.0 mA VCC = 5 V ± 10 % IIL Logical 0 Input Current (Ports 1, 2 and 3) – 50 µA Vin = 0.45 V ILI Input leakage Current ± 10 µA 0.45 < Vin < Vcc ITL Logical 1 to 0 Transition Current (Ports 1, 2 and 3) – 650 µA Vin = 2.0 V IPD Power Down Current 50 µA Vcc = 2.0 V to 5.5 V (note 1) RRST RST Pulldown Resistor 50 200 KOhm CIO Capacitance of I/O Buffer 10 pF fc = 1 MHz, Ta = 25/C0095C ICC Power Supply Current Freq = 1 MHz Icc op Icc idle Freq = 6 MHz Icc op Icc idle Freq ≥ 12 MHz Icc op = 1.25 Freq (MHz) + 5 mA Icc idle = 0.36 Freq (MHz) + 2.7 mA 1.8 mA mA mA mA Vcc = 5.5 V

Rev. G (14 Jan. 97) 11MA TRA MHS Absolute Maximum Ratings* Ambient Temperature Under Bias : * This value is based on the maximum allowable die temperature and the thermal resistance of the package * Notice Stresses above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Parameters TA = –40°C + 125°C ; VSS = 0 V ; VCC = 5 V ± 10 % ; F = 0 to 36 MHz SYMBOL PARAMETER MIN MAX UNIT TEST CONDITIONS VIL Input Low V oltage – 0.5 0.2 Vcc – 0.1 V VIH Input High V oltage (Except XTAL and RST) 0.2 Vcc + 1.4 Vcc + 0.5 V VIH1 Input High V oltage (for XTAL and RST) 0.7 Vcc Vcc + 0.5 V VOL Output Low V oltage (Port 1, 2 and 3) 0.3 0.45 1.0 V V V IOL = 100 µA IOL = 1.6 mA (note 2) IOL = 3.5 mA VOL1 Output Low V oltage (Port 0, ALE, PSEN) 0.3 0.45 1.0 V V V IOL = 200 µA IOL = 3.2 mA (note 2) IOL = 7.0 mA VOH Output High V oltage Port 1, 2 and 3 Vcc – 0.3 V IOH = – 10 µA Vcc – 0.7 V IOH = – 30 µA Vcc – 1.5 V IOH = – 60 µA VCC = 5 V ± 10 % VOH1 Output High V oltage (Port 0, ALE, PSEN) Vcc – 0.3 V IOH = – 200 µΑ Vcc – 0.7 V IOH = – 3.2 mA Vcc – 1.5 V IOH = – 7.0 mA VCC = 5 V ± 10 % IIL Logical 0 Input Current (Ports 1, 2 and 3) – 75 µA Vin = 0.45 V ILI Input leakage Current ±10 µA 0.45 < Vin < Vcc ITL Logical 1 to 0 Transition Current (Ports 1, 2 and 3) – 750 µA Vin = 2.0 V IPD Power Down Current 75 µA Vcc = 2.0 V to 5.5 V (note 1) RRST RST Pulldown Resistor 50 200 KOhm CIO Capacitance of I/O Buffer 10 pF fc = 1 MHz, Ta = 25/C0095C ICC Power Supply Current Freq = 1 MHz Icc op Icc idle Freq = 6 MHz Icc op Icc idle Freq ≥ 12 MHz Icc op = 1.25 Freq (MHz) + 5 mA Icc idle = 0.36 Freq (MHz) + 2.7 mA 1.8 mA mA mA mA Vcc = 5.5 V

Rev. G (14 Jan. 97)

12 MA TRA MHS

Absolute Maximum Ratings* Ambient Temperature Under Bias : * This value is based on the maximum allowable die temperature and the thermal resistance of the package * Notice Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. DC Parameters TA = –55°C + 125°C ; Vss = 0 V ; Vcc = 5 V ± 10 % ; F = 0 to 36 MHz SYMBOL PARAMETER MIN MAX UNIT TEST CONDITIONS VIL Input Low V oltage – 0.5 0.2 Vcc – 0.1 V VIH Input High V oltage (Except XTAL and RST) 0.2 Vcc + 1.4 Vcc + 0.5 V VIH1 Input High V oltage (for XTAL and RST) 0.7 Vcc Vcc + 0.5 V VOL Output Low V oltage (Port 1, 2 and 3) 0.45 V IOL = 1.6 mA (note 2) VOL1 Output Low V oltage (Port 0, ALE, PSEN) 0.45 V IOL = 3.2 mA (note 2) VOH Output High V oltage (Port 1, 2 and 3) 2.4 V IOH = – 60 µA Vcc = 5 V ± 10 %

0.75 Vcc V IOH = – 25 µA

0.9 Vcc V IOH = – 10 µA

(Port 0 in External Bus Mode, ALE, PEN)

2.4 V IOH = – 400 µA

Vcc = 5 V ± 10 %

0.75 Vcc V IOH = – 150 µA

0.9 Vcc V IOH = – 40 µA

IIL Logical 0 Input Current (Ports 1, 2 and 3) – 75 µA Vin = 0.45 V ILI Input leakage Current +/– 10 µA 0.45 < Vin < Vcc ITL Logical 1 to 0 Transition Current (Ports 1, 2 and 3) – 750 µA Vin = 2.0 V IPD Power Down Current 75 µA Vcc = 2.0 V to 5.5 V (note 1) RRST RST Pulldown Resistor 50 200 K Ω CIO Capacitance of I/O Buffer 10 pF fc = 1 MHz, Ta = 25/C0095C ICC Power Supply Current Freq = 1 MHz Icc op Icc idle Freq = 6 MHz Icc op Icc idle Freq ≥ 12 MHz Icc op = 1.25 Freq (MHz) + 5 mA Icc idle = 0.36 Freq (MHz) + 2.7 mA 1.8 mA mA mA mA Vcc = 5.5 V

Rev. G (14 Jan. 97) 13MA TRA MHS Absolute Maximum Ratings* Ambient Temperature Under Bias : /C0073 /C0061 /C0073/C0110/C0100/C0117/C0115/C0116/C0114/C0105/C0097/C0108 /C0045/C0052/C0048 /C0116/C0111 /C0056/C0053/C0176/C0067/C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 ** This value is based on the maximum allowable die temperature and the thermal resistance of the package * Notice Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. DC Characteristics TA = 0°C to 70°C ; Vcc = 2.7 V to 5.5 V ; Vss = 0 V ; F = 0 to 16 MHz TA = –40°C to 85°C ; Vcc = 2.7 V to 5.5 V SYMBOL PARAMETER MIN MAX UNIT TEST CONDITIONS VIL Input Low V oltage – 0.5 0.2 VCC – 0.1 V VIH Input High V oltage (Except XTAL and RST)0.2 VCC + 1.4 V CC + 0.5 V VIH2 Input High V oltage to RST for Reset 0.7 VCC V CC + 0.5 V VIH1 Input High V oltage to XTAL1 0.7 VCC V CC + 0.5 V VPD Power Down V oltage to Vcc in PD Mode 2.0 5.5 V VOL Output Low V oltage (Ports 1, 2, 3) 0.45 V IOL = 0.8 mA (note 2) VOL1 Output Low V oltage Port 0, ALE, PSEN 0.45 V IOL = 1.6 mA (note 2) VOH Output High V oltage Ports 1, 2, 3 0.9 Vcc V IOH = – 10 µA VOH1 Output High V oltage (Port 0 in External Bus Mode), ALE, PSEN IIL Logical 0 Input Current Ports 1, 2, 3 – 50 µA Vin = 0.45 V ILI Input Leakage Current ± 10 µA 0.45 < Vin < VCC ITL Logical 1 to 0 Transition Current (Ports 1, 2, 3) – 650 µA Vin = 2.0 V IPD Power Down Current 50 µA V CC = 2.0 V to 5.5 V (note 1) RRST RST Pulldown Resistor 50 200 kΩ CIO Capacitance of I/O Buffer 10 pF fc = 1 MHz, TA = 25/C0095C Maximum Icc (mA) OPERATING (NOTE 1) IDLE (NOTE 1) 1 MHz 0.8 mA 1 mA 1.1 mA 1.8 mA 400 µA 500 µA 600 µA 1 mA 6 MHz 4 mA 5 mA 6 mA 10 mA 1.5 mA 1.7 mA 2 mA 4 mA 12 MHz 8 mA 10 mA 12 mA 2.5 mA 3 mA 3.5 mA 16 MHz 10 mA 12 mA 14 mA 3 mA 3.8 mA 4.5 mA Freq > 12 MHz (Vcc = 5.5 V) Icc (mA) = 1.25 × Freq (MHz) + 5 Icc Idle (mA) = 0.36 × Freq (MHz) + 2.7

14 MA TRA MHS

higher if a crystal oscillator used. Trigger use is not necessary. Figure 9. ICC Test Condition, Idle Mode. All other pins are disconnected. Figure 10. ICC Test Condition, Active Mode. All other pins are disconnected. Figure 11. ICC Test Condition, Power Down Mode. All other pins are disconnected. Figure 12. Clock Signal Waveform for ICC Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns.

Rev. G (14 Jan. 97) 15MA TRA MHS Explanation of the AC Symbol Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Example : TA VLL = Time for Address Valid to ALE low. TLLPL = Time for ALE low to PSEN low. A : Address. C : Clock. D : Input data. H : Logic level HIGH I : Instruction (program memory contents). L : Logic level LOW, or ALE. P : PSEN. Q : Output data. R : READ signal. T : Time. V : Valid. W : WRITE signal. X : No longer a valid logic level. Z : Float. AC Parameters TA = 0 to + 70°C ; Vss = 0 V ; Vcc = 5 V ± 10 % ; F = 0 to 44 MHz TA = 0 to +70°C ; Vss = 0 V ; 2.7 V < Vcc < 5.5 V ; F = 0 to 16 MHz TA = –40° to + 85°C ; Vss = 0 V ; 2.7 V < Vcc < 5.5 V ; F = 0 to 16 MHz TA = –55° + 125°C ; Vss = 0 V ; Vcc = 5 V ± 10 % ; F = 0 to 36 MHz (Load Capacitance for PORT 0, ALE and PSEN = 100 pF ; Load Capacitance for all other outputs = 80 pF) External Program Memory Characteristics (values in ns)

16 MHz 20 MHz 25 MHz 30 MHz 36 MHz 40 MHz 42 MHz 44 MHz

PARAMETER min max min max min max min max min max min max min max min max TLHLL ALE Pulse Width 110 90 70 60 50 40 35 30 TA VLL Address valid to ALE 40 30 20 15 10 9 8 7 TLLAX Address Hold After ALE 35 35 35 35 35 30 25 17 TLLIV ALE to valid instr in 185 170 130 100 80 70 65 65 TLLPL ALE to PSEN 45 40 30 25 20 15 13 12 TPLPH PSEN pulse Width 165 130 100 80 75 65 60 54 TPLIV PSEN to valid instr in 125 110 85 65 50 45 40 35 TPXIX Input instr Hold After PSEN 0 0 0 0 0 0 0 0 TPXIZ Input instr Float After PSEN 50 45 35 30 25 20 15 10 TPXA V PSEN to Address Valid 55 50 40 35 30 25 20 15 TA VIV Address to Valid instr in 230 210 170 130 90 80 75 70 TPLAZ PSEN low to Address Float 10 10 8 6 5 5 5 5 External Program Memory Read Cycle TAVIV

Rev. G (14 Jan. 97)

16 MA TRA MHS

External Data Memory Characteristics (values in ns) BOL PARAMETER min max min max min max min max min max min max min max min max TRLRH RD pulse Width 340 270 210 180 120 100 90 80 TWLWH WR pulse Width 340 270 210 180 120 100 90 80 TLLAX Address Hold After ALE 85 85 70 55 35 30 25 25 TRLDV RD to Valid Data in 240 210 175 135 110 90 80 70 TRHDX Data hold after RD 0 0 0 0 0 0 0 0 TRHDZ Data float after RD 90 90 80 70 50 45 40 35 TLLDV ALE to Valid Data In 435 370 290 235 170 150 140 130 TA VDV Address to Valid Data IN 480 400 320 260 190 180 175 170 TLLWL ALE to WR or RD 150 250 135 170 120 130 90 115 70 100 60 95 55 90 50 85 TA VWL Address to WR or RD 180 180 140 115 75 65 60 55 TQVWX Data valid to WR transition 35 35 30 20 15 10 8 6 TQVWH Data Setup to WR transition380 325 250 215 170 160 150 140 TWHQX Data Hold after WR 40 35 30 20 15 10 8 6 TRLAZ RD low to Address Float 0 0 0 0 0 0 0 0 TWHLH RD or WR high to ALE high 35 90 35 60 25 45 20 40 20 40 15 35 13 33 13 33 External Data Memory Write Cycle TAVWL TQVWX External Data Memory Read Cycle

Rev. G (14 Jan. 97) 17MA TRA MHS Serial Port Timing – Shift Register Mode (values in ns) BOL PARAMETER min max min max min max min max min max min max min max min max TXLXL Serial Port Clock Cycle Time750 600 480 400 330 250 230 227 TQVXH Output Data Setup to Clock Rising Edge 563 480 380 300 220 170 150 140 TXHQX Output Data Hold after Clock Rising Edge 63 90 65 50 45 35 30 25 TXHDX Input Data Hold after Clock Rising Edge 0 0 0 0 0 0 0 0 TXHDV Clock Rising Edge to Input Data Valid 563 450 350 300 250 200 180 160 Shift Register Timing Waveforms

Rev. G (14 Jan. 97)

18 MA TRA MHS

External Clock Drive Characteristics (XTAL1) SYMBOL PARAMETER MIN MAX UNIT FCLCL Oscillator Frequency 44 MHz TCLCL Oscillator period 22.7 ns TCHCX High Time 5 ns TCLCX Low Time 5 ns TCLCH Rise Time 5 ns TCHCL Fall Time 5 ns External Clock Drive Waveforms AC Testing Input/Output Waveforms AC inputs during testing are driven at Vcc – 0.5 for a logic “1” and 0.45 V for a logic “0”. Timing measurements are made at VIH min for a logic “1” and VIL max for a logic “0”. Float Waveforms For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. Iol/IoH ≥ ± 20 mA.

Rev. G (14 Jan. 97) 19MA TRA MHS Clock Waveforms This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (T A = 25°C fully loaded) RD and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications.

Rev. G (14 Jan. 97)

20 MA TRA MHS

Ordering Information

blank : Commercial I : Industrial A : Automotive M : Military Part Number 80C52 Rom 8 K × 8 80C32 External ROM 80C52C Secret ROM version 80C52T Secret Tag version 80C32E Radiation Tolerant 80C52E Radiation Tolerant Customer Rom Code I 80C52C –12 : 12 MHz version –16 : 16 MHz version –20 : 20 MHz version –25 : 25 MHz version –30 : 30 MHz version –36 : 36 MHz version –40 : 40 MHz version (1) –42 : 42 MHz version (1) –44 : 44 MHz version (1) –L16 : Low Power (Vcc : 2.7-5.5 V Freq : 0-16 MHz) R : Tape and Reel D : Dry Pack Package Type P: PDIL 40 S: PLCC 44 F1: PQFP 44 (Foot print 13.9 mm) F2: PQFP 44 (Foot print 12.3 mm) V: VQFP (1.4 mm) T: TQFP (1.0 mm) D: CDIL 40 Q: CQFP 44 R: LCC 44 C: Side Braze 40 (.6) (1) Only for 80C31 at commercial range. Flow /883 MIL compliant P883 MIL compliant with PIND test SB SCC9000 level B SC SCC9000 level C