7809LP MAXWELL | Alldatasheet
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01.11.05 Rev 7
BUSY rises, or another conversion will start without time for signal acquisition. reduced. Results from the previous conversions are maintained in the output shift register. 23 LPVANA Latchup Protection Analog Supply. 24 LPVDIG Latchup Protection Digital Supply. TABLE 2. 7809LP ABSOLUTE MAXIMUM RATINGS
- Indefinite short to AGND2, momentarily short to V ANA.
TABLE 3. 7809LP DC ACCURACY SPECIFICATIONS TABLE 1. 7809LP PIN DESCRIPTION
- LSB stands for Least Significant Bit. One LSB is equal to 305 µ V.
- Typical rms noise at worst case transitions and temperatures.
- Measured with various fixed resistors.
- For bipolar input ranges, full scale error is the worst case of -Full Scale or +Full Scale untrimmed deviation from ideal fir st and
also includes the effect of offset error. TABLE 4. DELTA LIMITS TABLE 5. 7809LP DIGITAL INPUTS TABLE 3. 7809LP DC ACCURACY SPECIFICATIONS
TABLE 6. 7809LP ANALOG INPUT AND THROUGHPUT SPEED
- Tested by application of signal.
TABLE 7. 7809LP AC ACCURACY SPECIFICATIONS
- All specifications in dB are referred to a full-scale ±10 V input.
- Full-Power Bandwidth defined as Full-Scale input frequency at which Signal-to-Noise (Noise + Distortion) degrades to 60 dB.
TABLE 8. 7809LP SAMPLING DYNAMICS
- Recovers to specified performance after 2 X FS input overvoltage.
TABLE 9. 7809LP REFERENCE
- Tested by application of signal.
TABLE 10. 7809LP DIGITAL OUTPUTS TABLE 11. 7809LP POWER SUPPLIES
TABLE 12. 7809LP CONTROL LINE FUNCTIONS FOR READ AND CONVERT
- See Figure 4 for constraints on previous data valid during conversion.
TABLE 13. 7809LP INPUT RANGE CONNECTION TABLE 14. 7809LP CONVERSION AND DATA TIMING TABLE 12. 7809LP CONTROL LINE FUNCTIONS FOR READ AND CONVERT
TABLE 15. 7809LP CONVERSION DATA TIMING TABLE 14. 7809LP CONVERSION AND DATA TIMING
FIGURE 1. CONVERSION TIMING FIGURE 2. SERIAL DATA TIMING USING INTERNAL CLOCK (CS, EXT/INT AND TAG TIED LOW) FIGURE 3. CONVERSION AND READ TIMING WITH EXTERNAL CLOCK (EXT/INT TIED HIGH). READ AFTER
FIGURE 4. CONVERSION AND READ TIMING WITH EXTERNAL CLOCK (EXT/INT TIED HIGH). READ DURING
FIGURE 5. OFFSET/GAIN CIRCUITS FOR UNIPOLAR INPUT RANGES
FIGURE 6. OFFSET/GAIN CIRCUITS FOR BIPOLAR INPUT RANGES
block, and an active input protection block. Figure 7. 7809LP Simplified Block Diagram
15All data sheets are subject to change without notice ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected Analog to Digital Converter 7809LP Differences Between the 7809LP and the ADS7809 Because the 7809LP uses the ADS7809 die to perform the analog to digital conversion function, its operation and per- formance is very similar to the ADS7809 packaged part from Burr-Brown. In general the operation and application will be the same for both parts. There are three primary differences: the operation of the supply pins, the operation of the additional LPBIT and LPSTATUS pins, and the operation of the I/O pins when a latchup is detected. The ADS7809 provides separate analog and digital supply pins, VANA and VDIG. These same supply pins on the 7809LPRP should be connected to the analog and digital supplies. There is no limit to the capacitance that can be connected to these pins in the system application. The 7809LP package also provides access to the ADS7809 die supply pins with the LPVANA and LPVDIG pins. The signal paths between the supply input pins and the respective die supply pins are low resistance during normal device operation. When an excessive supply current due to a single event latchup is sensed on either of the supply pins, the LPT TM circuit opens both paths to the die supply pins allowing the latchup condition to clear. The LPVANA and LPV- DIG pins allow access to the current sense circuitry for electrical testing at the component level and provide optimal locations for attaching supply decoupling capacitors. CAUTION: The LPVANA and LPVDIG pins must not be con- nected to the respective power supplies since this will defeat the LPT TM power switch and could result in permanent latchup of the device during operation in a radiation environment. Electrolytic capacitors should not be connected to these decoupling pins because the large capacitance will increase the recovery time of the 7809LP . Low ESR ceramic capacitors should be used with a maximum of .2µ F per pin. The LPBIT input provides a means to electrically test the LPT TM circuit. A high level on the this pin causes a preset current to be drawn in addition to the normal device current through the analog and digital current sensors. If the high level is maintained for a sufficient duration, it will trigger the LPT TM circuit which will cycle the power to the protected device. If the LPBIT remains high, the LPTTM circuit will continuously cycle the supply voltages off then on. Driving this input with a 10 µ s high level pulse is sufficient duration to assure the LPT TM circuit cycles the power off then on one time only. A high level on the LPSTATUS output indicates that the LPT TM circuit has removed power from the protected device. The LPSTATUS returns low when the power is restored. LPSTATUS can be used to generate an input to the system data processor indicating that an LPT TM cycle has occurred and the protected device output accuracy may not be met until after the respective recovery time to the event. During the time that power is removed from the protected device, it is critical that external circuitry driving the device I/ O pins does not back-drive the device supply through input protection diodes or similar integrated structures. Back- driving of the supply through the device I/O pins could contribute to an extended or even a permanent latchup condi- tion. For the ADS7809 testing has shown that for the normal signal range of operation on the analog input pins R1IN, R2IN, and R3IN, latchup will not be sustained. In order to prevent back-driving the supply from the digital I/O pins DATA, SYNC, TAG, R/C, CS, and PWRD, the 7809LP incorporates active input protection circuits. These circuits act as transmission gates in series with the digital inputs. During normal operation, these gates are on and present low resistance connections between the package input pins and the respective die pins. When the LPT TM circuit detects a latchup, these gates are switched off and present a high resistance path between the package inputs and the die inputs. The protected I/O pins are crow barred during the latchup. The bidirectional signal, DATACLK, is also protected by a transmission gate.
During an LPTTM cycle, all outputs of the 7809LP are invalid and unpredictable until after the functional recovery time. A summary of the pin differences between the ADS7809 and the 7809LP is provided in the table below. TABLE 15. ADS7809 AND 7809LP PIN DIFFERENCES shall be low during normal operation. go low (inactive) after the 10 µ s decision period without power being removed. outputs. I/O pins must not be driven high while this signal is active. 13 VANA VANA Equivalent function to ADS7809 pin 19. Analog Supply Input. 14 VDIG VDIG Equivalent function to ADS7809 pin 20. Digital Supply Input.
surements are made with the ADS7809 in its lowest power state (PWRD = 5V). trigger the LPTTM circuit to be drawn through both the analog and digital supply sense circuits. indicates that power is removed from the ADS7809 die. When this signal is low, power is applied to the ADS7809 die. supply current rises (causing LPSTATUS to go high) and ends when the LPSTATUS signal stabilizes low again. TABLE 16. 7809LP LPTTM OPERATING CHARACTERISTICS
FIGURE 8. 7809LP LPTTM TEST CIRCUIT
20 USEC PULSEWIDTH
5 USEC PULSEWIDTH
200 R2 100
FIGURE 9. 7809LP LPTTM TIMING DIAGRAM
FIGURE 10. SEL CROSS SECTION FIGURE 11. SEU CROSS SECTION
21All data sheets are subject to change without notice ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected Analog to Digital Converter 7809LP Note: All dimensions in inches 24-PIN RAD-PAK® FLAT PACKAGE SYMBOL DIMENSION MIN NOM MAX A 0.255 0.278 0.302 b 0.015 0.017 0.022 c 0.006 0.008 0.010 D -- 0.596 0.640 E 0.900 0.400 0.410 E1 -- -- 0.440 E2 0.268 0.270 0.272 E3 0.055 0.065 -- e 0.050 BSC L 0.420 0.430 0.045 Q 0.040 0.045 0.006 S1 0.006 0.014 -- N2 4
22All data sheets are subject to change without notice ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected Analog to Digital Converter 7809LP Important Notice: These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech- nologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.
23All data sheets are subject to change without notice ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected Analog to Digital Converter 7809LP Feature Option Details7809LP RP F X Screening Flow Package Radiation Feature Base Product Nomenclature Multi Chip Module (MCM)1 K = Maxwell Self-Defined Class K H = Maxwell Self-Defined Class H I = Industrial (testing @ -40°C, +25°C, +85°C) E = Engineering (testing @ +25°C) F = Flat Pack RP = R AD-PAK® package 16-Bit Latchup Protected Analog to Digital Converter 1) Products are manufactured and screened to Maxwell Technologies self-defined Class H and Class K flows.